616 lines
16 KiB
C
616 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim Quad GMSL Deserializer MIPI txphy driver
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
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*
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* Author: Cai Wenzhong <cwz@rock-chips.com>
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*
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*/
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#include <linux/iopoll.h>
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#include "maxim4c_api.h"
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static int maxim4c_txphy_init_timing(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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int ret = 0;
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u16 reg_addr = 0;
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u8 reg_mask;
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u8 timing;
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u8 phy_idx = 0;
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if (!maxim4c->mipi_txphy.timing_override_en)
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return 0;
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timing = ((maxim4c->mipi_txphy.timing.t_hs_przero & 0x3) << 6 |
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(maxim4c->mipi_txphy.timing.t_hs_prep & 0x3) << 4 |
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(maxim4c->mipi_txphy.timing.t_clk_trail & 0x3) << 2 |
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(maxim4c->mipi_txphy.timing.t_clk_przero & 0x3) << 0);
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ret |= maxim4c_i2c_write_reg(client, 0x08A1, timing);
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reg_mask = 0x0F;
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timing = ((maxim4c->mipi_txphy.timing.t_lpx & 0x3) << 2 |
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(maxim4c->mipi_txphy.timing.t_hs_trail & 0x3) << 0);
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ret |= maxim4c_i2c_update_reg(client,
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0x08A2, reg_mask, timing);
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reg_mask = (0x3 << 6);
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timing = (maxim4c->mipi_txphy.timing.t_lpxesc & 0x3) << 6;
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ret |= maxim4c_i2c_update_reg(client,
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0x08A5, reg_mask, timing);
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reg_mask = (0x7 << 5);
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timing = (maxim4c->mipi_txphy.timing.t_lpxesc & 0x7) << 5;
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ret |= maxim4c_i2c_update_reg(client,
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0x08A8, reg_mask, timing);
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for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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reg_mask = 0xFF;
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reg_addr = 0x0905 + 0x40 * phy_idx;
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timing = maxim4c->mipi_txphy.timing.csi2_t_pre;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, reg_mask, timing);
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reg_addr = 0x0906 + 0x40 * phy_idx;
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timing = maxim4c->mipi_txphy.timing.csi2_t_post;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, reg_mask, timing);
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reg_addr = 0x0907 + 0x40 * phy_idx;
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timing = maxim4c->mipi_txphy.timing.csi2_tx_gap;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, reg_mask, timing);
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reg_addr = 0x0908 + 0x40 * phy_idx;
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timing = maxim4c->mipi_txphy.timing.csi2_twakeup & 0xFF;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, reg_mask, timing);
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timing = (maxim4c->mipi_txphy.timing.csi2_twakeup >> 8) & 0xFF;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr + 1, reg_mask, timing);
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reg_mask = 0x7;
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timing = (maxim4c->mipi_txphy.timing.csi2_twakeup >> 16) & 0x7;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr + 2, reg_mask, timing);
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}
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return ret;
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}
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static int maxim4c_txphy_auto_init_deskew(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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struct maxim4c_txphy_cfg *phy_cfg = NULL;
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u16 reg_addr = 0;
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u8 phy_idx = 0;
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int ret = 0;
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// D-PHY Deskew Initial Calibration Control
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for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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phy_cfg = &mipi_txphy->phy_cfg[phy_idx];
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if (phy_cfg->phy_enable && (phy_cfg->auto_deskew & BIT(7))) {
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reg_addr = 0x0903 + 0x40 * phy_idx;
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ret |= maxim4c_i2c_write_reg(client,
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reg_addr, phy_cfg->auto_deskew);
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}
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}
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return ret;
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}
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static int maxim4c_mipi_txphy_lane_mapping(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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struct maxim4c_txphy_cfg *phy_cfg = NULL;
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u8 reg_value = 0, reg_mask = 0;
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int ret = 0;
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// MIPI TXPHY A/B: data lane mapping
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reg_mask = 0;
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reg_value = 0;
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phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_A];
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if (phy_cfg->phy_enable) {
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reg_mask |= 0x0F;
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reg_value |= (phy_cfg->data_lane_map << 0);
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}
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phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_B];
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if (phy_cfg->phy_enable) {
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reg_mask |= 0xF0;
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reg_value |= (phy_cfg->data_lane_map << 4);
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}
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if (reg_mask != 0) {
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ret |= maxim4c_i2c_update_reg(client,
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0x08A3, reg_mask, reg_value);
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}
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// MIPI TXPHY C/D: data lane mapping
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reg_mask = 0;
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reg_value = 0;
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phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_C];
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if (phy_cfg->phy_enable) {
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reg_mask |= 0x0F;
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reg_value |= (phy_cfg->data_lane_map << 0);
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}
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phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_D];
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if (phy_cfg->phy_enable) {
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reg_mask |= 0xF0;
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reg_value |= (phy_cfg->data_lane_map << 4);
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}
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if (reg_mask != 0) {
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ret |= maxim4c_i2c_update_reg(client,
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0x08A4, reg_mask, reg_value);
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}
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return ret;
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}
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static int maxim4c_mipi_txphy_type_vcx_lane_num(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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struct maxim4c_txphy_cfg *phy_cfg = NULL;
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u8 phy_idx = 0;
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u8 reg_mask = 0, reg_value = 0;
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u16 reg_addr = 0;
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int ret = 0;
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for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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phy_cfg = &mipi_txphy->phy_cfg[phy_idx];
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if (phy_cfg->phy_enable == 0)
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continue;
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reg_mask = 0xF0;
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reg_value = 0;
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if (phy_cfg->phy_type == MAXIM4C_TXPHY_TYPE_CPHY)
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reg_value |= BIT(5);
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if (phy_cfg->vc_ext_en)
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reg_value |= BIT(4);
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reg_value |= ((phy_cfg->data_lane_num - 1) << 6);
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reg_addr = 0x090A + 0x40 * phy_idx;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, reg_mask, reg_value);
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}
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return ret;
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}
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int maxim4c_mipi_txphy_enable(maxim4c_t *maxim4c, bool enable)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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u8 phy_idx = 0;
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u8 reg_mask = 0, reg_value = 0;
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int ret = 0;
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dev_dbg(dev, "%s: enable = %d\n", __func__, enable);
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reg_mask = 0xF0;
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reg_value = 0;
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if (enable) {
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for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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if (mipi_txphy->phy_cfg[phy_idx].phy_enable)
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reg_value |= BIT(4 + phy_idx);
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}
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}
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ret |= maxim4c_i2c_update_reg(client,
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0x08A2, reg_mask, reg_value);
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return ret;
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}
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int maxim4c_dphy_dpll_predef_set(maxim4c_t *maxim4c, s64 link_freq_hz)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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struct maxim4c_txphy_cfg *phy_cfg = NULL;
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u32 link_freq_mhz = 0;
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u16 reg_addr = 0;
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u8 phy_idx = 0;
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u8 dpll_mask = 0, dpll_val = 0, dpll_lock = 0;
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int ret = 0;
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dpll_mask = 0;
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link_freq_mhz = (u32)div_s64(link_freq_hz, 1000000L);
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dpll_val = DIV_ROUND_UP(link_freq_mhz * 2, 100) & 0x1F;
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if (dpll_val == 0)
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dpll_val = 15; /* default 1500MBps */
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// Disable software override for frequency fine tuning
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dpll_val |= BIT(5);
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for (phy_idx = 0; phy_idx < MAXIM4C_TXPHY_ID_MAX; phy_idx++) {
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phy_cfg = &mipi_txphy->phy_cfg[phy_idx];
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if ((phy_cfg->phy_enable == 0) || (phy_cfg->clock_master == 0))
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continue;
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if (phy_cfg->clock_mode != MAXIM4C_TXPHY_DPLL_PREDEF)
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continue;
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dpll_mask |= BIT(phy_idx + 4);
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// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
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reg_addr = 0x1C00 + 0x100 * phy_idx;
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ret |= maxim4c_i2c_write_reg(client, reg_addr, 0xf4);
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reg_addr = 0x1C03 + 0x100 * phy_idx;
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ret |= maxim4c_i2c_update_reg(client,
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reg_addr, 0x07, phy_cfg->ssc_ratio);
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// Set dpll data rate
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reg_addr = 0x0415 + 0x03 * phy_idx;
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ret |= maxim4c_i2c_update_reg(client, reg_addr, 0x3F, dpll_val);
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// Release reset to DPLL (config_soft_rst_n = 1)
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reg_addr = 0x1C00 + 0x100 * phy_idx;
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ret |= maxim4c_i2c_write_reg(client, reg_addr, 0xf5);
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}
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if (ret) {
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dev_err(dev, "DPLL predef set error!\n");
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return ret;
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}
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ret = read_poll_timeout(maxim4c_i2c_read_reg, ret,
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!(ret < 0) && (dpll_lock & dpll_mask),
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1000, 10000, false,
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client, 0x0400, &dpll_lock);
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if (ret < 0) {
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dev_err(dev, "DPLL is unlocked: 0x%02x\n", dpll_lock);
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return ret;
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} else {
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dev_info(dev, "DPLL is locked: 0x%02x\n", dpll_lock);
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return 0;
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}
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}
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EXPORT_SYMBOL(maxim4c_dphy_dpll_predef_set);
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int maxim4c_mipi_csi_output(maxim4c_t *maxim4c, bool enable)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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u8 reg_mask = 0, reg_value = 0;
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int ret = 0;
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dev_dbg(dev, "%s: enable = %d\n", __func__, enable);
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if (mipi_txphy->force_clock_out_en != 0) {
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reg_mask = BIT(7);
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reg_value = enable ? BIT(7) : 0;
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// Force all MIPI clocks running Config
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ret |= maxim4c_i2c_update_reg(client,
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0x08A0, reg_mask, reg_value);
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}
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/* Bit1 of the register 0x040B: CSI_OUT_EN
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* 1 = CSI output enabled
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* 0 = CSI output disabled
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*/
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reg_mask = BIT(1);
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reg_value = enable ? BIT(1) : 0;
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// MIPI CSI output Setting
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ret |= maxim4c_i2c_update_reg(client,
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0x040B, reg_mask, reg_value);
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return ret;
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}
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EXPORT_SYMBOL(maxim4c_mipi_csi_output);
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static int maxim4c_mipi_txphy_config_parse_dt(struct device *dev,
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maxim4c_mipi_txphy_t *mipi_txphy,
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struct device_node *parent_node)
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{
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struct device_node *node = NULL;
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struct maxim4c_txphy_cfg *phy_cfg = NULL;
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const char *txphy_cfg_name = "mipi-txphy-config";
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u32 value = 0;
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u32 sub_idx = 0, phy_id = 0;
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int ret;
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node = NULL;
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sub_idx = 0;
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while ((node = of_get_next_child(parent_node, node))) {
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if (!strncasecmp(node->name,
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txphy_cfg_name,
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strlen(txphy_cfg_name))) {
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if (sub_idx >= MAXIM4C_TXPHY_ID_MAX) {
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dev_err(dev, "%pOF: Too many matching %s node\n",
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parent_node, txphy_cfg_name);
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of_node_put(node);
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break;
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}
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if (!of_device_is_available(node)) {
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dev_info(dev, "%pOF is disabled\n", node);
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sub_idx++;
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continue;
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}
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/* MIPI TXPHY: phy id */
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ret = of_property_read_u32(node, "phy-id", &phy_id);
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if (ret) {
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// if mipi txphy phy_id is error, parse next node
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dev_err(dev, "Can not get phy-id property!");
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sub_idx++;
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continue;
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}
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if (phy_id >= MAXIM4C_TXPHY_ID_MAX) {
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// if mipi txphy phy_id is error, parse next node
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dev_err(dev, "Error phy-id = %d!", phy_id);
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sub_idx++;
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continue;
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}
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phy_cfg = &mipi_txphy->phy_cfg[phy_id];
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/* MIPI TXPHY: phy enable */
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phy_cfg->phy_enable = 1;
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dev_info(dev, "mipi txphy id = %d: phy_enable = %d\n",
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phy_id, phy_cfg->phy_enable);
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/* MIPI TXPHY: other config */
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ret = of_property_read_u32(node, "phy-type", &value);
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if (ret == 0) {
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dev_info(dev, "phy-type property: %d", value);
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phy_cfg->phy_type = value;
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}
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ret = of_property_read_u32(node, "auto-deskew", &value);
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if (ret == 0) {
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dev_info(dev, "auto-deskew property: 0x%x", value);
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phy_cfg->auto_deskew = value;
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}
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ret = of_property_read_u32(node, "data-lane-num", &value);
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if (ret == 0) {
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dev_info(dev, "data-lane-num property: %d", value);
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phy_cfg->data_lane_num = value;
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}
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ret = of_property_read_u32(node, "data-lane-map", &value);
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if (ret == 0) {
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dev_info(dev, "data-lane-map property: 0x%x", value);
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phy_cfg->data_lane_map = value;
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}
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ret = of_property_read_u32(node, "vc-ext-en", &value);
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if (ret == 0) {
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dev_info(dev, "vc-ext-en property: %d", value);
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phy_cfg->vc_ext_en = value;
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}
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ret = of_property_read_u32(node, "clock-mode", &value);
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if (ret == 0) {
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dev_info(dev, "clock-mode property: %d", value);
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phy_cfg->clock_mode = value;
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}
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ret = of_property_read_u32(node, "ssc-ratio", &value);
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if (ret == 0) {
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dev_info(dev, "ssc-ratio property: %d", value);
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phy_cfg->ssc_ratio = value;
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}
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sub_idx++;
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}
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}
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return 0;
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}
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int maxim4c_mipi_txphy_parse_dt(maxim4c_t *maxim4c, struct device_node *of_node)
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{
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struct device *dev = &maxim4c->client->dev;
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struct device_node *node = NULL;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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u32 value = 0;
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int ret = 0;
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dev_info(dev, "=== maxim4c mipi txphy parse dt ===\n");
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node = of_get_child_by_name(of_node, "mipi-txphys");
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if (IS_ERR_OR_NULL(node)) {
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dev_err(dev, "%pOF has no child node: mipi-txphys\n",
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of_node);
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return -ENODEV;
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}
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if (!of_device_is_available(node)) {
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dev_info(dev, "%pOF is disabled\n", node);
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of_node_put(node);
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return -ENODEV;
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}
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/* mipi txphy mode */
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ret = of_property_read_u32(node, "phy-mode", &value);
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if (ret == 0) {
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dev_info(dev, "phy-mode property: %d\n", value);
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mipi_txphy->phy_mode = value;
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}
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dev_info(dev, "mipi txphy mode: %d\n", mipi_txphy->phy_mode);
|
|
|
|
/* MIPI clocks running mode */
|
|
ret = of_property_read_u32(node, "phy-force-clock-out", &value);
|
|
if (ret == 0) {
|
|
dev_info(dev, "phy-force-clock-out property: %d\n", value);
|
|
mipi_txphy->force_clock_out_en = value;
|
|
}
|
|
dev_info(dev, "mipi txphy force clock out enable: %d\n",
|
|
mipi_txphy->force_clock_out_en);
|
|
|
|
ret = of_property_read_u32(node, "phy-force-clk0-en", &value);
|
|
if (ret == 0) {
|
|
dev_info(dev, "phy-force-clk0-en property: %d\n", value);
|
|
mipi_txphy->force_clk0_en = value;
|
|
}
|
|
|
|
ret = of_property_read_u32(node, "phy-force-clk3-en", &value);
|
|
if (ret == 0) {
|
|
dev_info(dev, "phy-force-clk3-en property: %d\n", value);
|
|
mipi_txphy->force_clk3_en = value;
|
|
}
|
|
|
|
ret = maxim4c_mipi_txphy_config_parse_dt(dev, mipi_txphy, node);
|
|
|
|
of_node_put(node);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(maxim4c_mipi_txphy_parse_dt);
|
|
|
|
int maxim4c_mipi_txphy_hw_init(maxim4c_t *maxim4c)
|
|
{
|
|
struct i2c_client *client = maxim4c->client;
|
|
struct device *dev = &client->dev;
|
|
maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
|
|
struct maxim4c_txphy_cfg *phy_cfg = NULL;
|
|
u8 mode = 0;
|
|
int ret = 0, i = 0;
|
|
|
|
mode = 0;
|
|
switch (mipi_txphy->phy_mode) {
|
|
case MAXIM4C_TXPHY_MODE_4X2LANES:
|
|
mode |= BIT(0);
|
|
|
|
// clock master
|
|
for (i = 0; i < MAXIM4C_TXPHY_ID_MAX; i++) {
|
|
if (mipi_txphy->phy_cfg[i].phy_enable)
|
|
mipi_txphy->phy_cfg[i].clock_master = 1;
|
|
}
|
|
|
|
break;
|
|
case MAXIM4C_TXPHY_MODE_1X4LANES_2X2LANES:
|
|
mode |= BIT(3);
|
|
// MIPI master clock setting
|
|
if (mipi_txphy->force_clk0_en != 0)
|
|
mode |= BIT(5);
|
|
|
|
// clock master
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_B];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_C];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_D];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
break;
|
|
case MAXIM4C_TXPHY_MODE_2X2LANES_1X4LANES:
|
|
mode |= BIT(4);
|
|
// MIPI master clock setting
|
|
if (mipi_txphy->force_clk3_en != 0)
|
|
mode |= BIT(6);
|
|
|
|
// clock master
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_A];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_B];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_C];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
break;
|
|
case MAXIM4C_TXPHY_MODE_2X4LANES:
|
|
default:
|
|
mode |= BIT(2);
|
|
// MIPI master clock setting
|
|
if (mipi_txphy->force_clk0_en != 0)
|
|
mode |= BIT(5);
|
|
if (mipi_txphy->force_clk3_en != 0)
|
|
mode |= BIT(6);
|
|
// clock master
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_B];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
|
|
phy_cfg = &mipi_txphy->phy_cfg[MAXIM4C_TXPHY_ID_C];
|
|
if (phy_cfg->phy_enable)
|
|
phy_cfg->clock_master = 1;
|
|
break;
|
|
}
|
|
|
|
// MIPI TXPHY Mode setting
|
|
ret |= maxim4c_i2c_write_reg(client, 0x08A0, mode);
|
|
|
|
// mipi txphy data lane mapping
|
|
ret |= maxim4c_mipi_txphy_lane_mapping(maxim4c);
|
|
|
|
// mipi txphy type, lane number, virtual channel extension
|
|
ret |= maxim4c_mipi_txphy_type_vcx_lane_num(maxim4c);
|
|
|
|
// mipi txphy auto init deskew
|
|
ret |= maxim4c_txphy_auto_init_deskew(maxim4c);
|
|
|
|
// mipi txphy timing init
|
|
ret |= maxim4c_txphy_init_timing(maxim4c);
|
|
|
|
if (ret) {
|
|
dev_err(dev, "%s: txphy hw init error\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(maxim4c_mipi_txphy_hw_init);
|
|
|
|
void maxim4c_mipi_txphy_data_init(maxim4c_t *maxim4c)
|
|
{
|
|
maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
|
|
struct maxim4c_txphy_cfg *phy_cfg = NULL;
|
|
int i = 0;
|
|
|
|
mipi_txphy->phy_mode = MAXIM4C_TXPHY_MODE_2X4LANES;
|
|
mipi_txphy->force_clock_out_en = 1;
|
|
mipi_txphy->force_clk0_en = 0;
|
|
mipi_txphy->force_clk3_en = 0;
|
|
mipi_txphy->timing.t_lpx = 1;
|
|
mipi_txphy->timing.csi2_t_pre = 0x71;
|
|
mipi_txphy->timing.csi2_t_post = 0x19;
|
|
mipi_txphy->timing.csi2_tx_gap = 0x1C;
|
|
mipi_txphy->timing.csi2_twakeup = 0x100;
|
|
|
|
for (i = 0; i < MAXIM4C_TXPHY_ID_MAX; i++) {
|
|
phy_cfg = &mipi_txphy->phy_cfg[i];
|
|
|
|
phy_cfg->phy_enable = 0;
|
|
phy_cfg->phy_type = MAXIM4C_TXPHY_TYPE_DPHY;
|
|
phy_cfg->auto_deskew = 0;
|
|
phy_cfg->data_lane_num = 4;
|
|
phy_cfg->data_lane_map = 0xe4;
|
|
phy_cfg->vc_ext_en = 0;
|
|
phy_cfg->clock_master = 0;
|
|
phy_cfg->clock_mode = MAXIM4C_TXPHY_DPLL_PREDEF;
|
|
phy_cfg->ssc_ratio = 0;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(maxim4c_mipi_txphy_data_init);
|