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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
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369
include/linux/mfd/88pm80x.h Normal file
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/*
* Marvell 88PM80x Interface
*
* Copyright (C) 2012 Marvell International Ltd.
* Qiao Zhou <zhouqiao@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_88PM80X_H
#define __LINUX_MFD_88PM80X_H
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/atomic.h>
#define PM80X_VERSION_MASK (0xFF) /* 80X chip ID mask */
enum {
CHIP_INVALID = 0,
CHIP_PM800,
CHIP_PM805,
CHIP_MAX,
};
enum {
PM800_ID_BUCK1 = 0,
PM800_ID_BUCK2,
PM800_ID_BUCK3,
PM800_ID_BUCK4,
PM800_ID_BUCK5,
PM800_ID_LDO1,
PM800_ID_LDO2,
PM800_ID_LDO3,
PM800_ID_LDO4,
PM800_ID_LDO5,
PM800_ID_LDO6,
PM800_ID_LDO7,
PM800_ID_LDO8,
PM800_ID_LDO9,
PM800_ID_LDO10,
PM800_ID_LDO11,
PM800_ID_LDO12,
PM800_ID_LDO13,
PM800_ID_LDO14,
PM800_ID_LDO15,
PM800_ID_LDO16,
PM800_ID_LDO17,
PM800_ID_LDO18,
PM800_ID_LDO19,
PM800_ID_RG_MAX,
};
#define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */
#define PM800_NUM_BUCK (5) /*5 Bucks */
#define PM800_NUM_LDO (19) /*19 Bucks */
/* page 0 basic: slave adder 0x60 */
#define PM800_STATUS_1 (0x01)
#define PM800_ONKEY_STS1 (1 << 0)
#define PM800_EXTON_STS1 (1 << 1)
#define PM800_CHG_STS1 (1 << 2)
#define PM800_BAT_STS1 (1 << 3)
#define PM800_VBUS_STS1 (1 << 4)
#define PM800_LDO_PGOOD_STS1 (1 << 5)
#define PM800_BUCK_PGOOD_STS1 (1 << 6)
#define PM800_STATUS_2 (0x02)
#define PM800_RTC_ALARM_STS2 (1 << 0)
/* Wakeup Registers */
#define PM800_WAKEUP1 (0x0D)
#define PM800_WAKEUP2 (0x0E)
#define PM800_WAKEUP2_INV_INT (1 << 0)
#define PM800_WAKEUP2_INT_CLEAR (1 << 1)
#define PM800_WAKEUP2_INT_MASK (1 << 2)
#define PM800_POWER_UP_LOG (0x10)
/* Referance and low power registers */
#define PM800_LOW_POWER1 (0x20)
#define PM800_LOW_POWER2 (0x21)
#define PM800_LOW_POWER_CONFIG3 (0x22)
#define PM800_LOW_POWER_CONFIG4 (0x23)
/* GPIO register */
#define PM800_GPIO_0_1_CNTRL (0x30)
#define PM800_GPIO0_VAL (1 << 0)
#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
#define PM800_GPIO1_VAL (1 << 4)
#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
#define PM800_GPIO_2_3_CNTRL (0x31)
#define PM800_GPIO2_VAL (1 << 0)
#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
#define PM800_GPIO3_VAL (1 << 4)
#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
#define PM800_GPIO3_MODE_MASK 0x1F
#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
#define PM800_GPIO_4_CNTRL (0x32)
#define PM800_GPIO4_VAL (1 << 0)
#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
#define PM800_HEADSET_CNTRL (0x38)
#define PM800_HEADSET_DET_EN (1 << 7)
#define PM800_HSDET_SLP (1 << 1)
/* PWM register */
#define PM800_PWM1 (0x40)
#define PM800_PWM2 (0x41)
#define PM800_PWM3 (0x42)
#define PM800_PWM4 (0x43)
/* RTC Registers */
#define PM800_RTC_CONTROL (0xD0)
#define PM800_RTC_MISC1 (0xE1)
#define PM800_RTC_MISC2 (0xE2)
#define PM800_RTC_MISC3 (0xE3)
#define PM800_RTC_MISC4 (0xE4)
#define PM800_RTC_MISC5 (0xE7)
/* bit definitions of RTC Register 1 (0xD0) */
#define PM800_ALARM1_EN (1 << 0)
#define PM800_ALARM_WAKEUP (1 << 4)
#define PM800_ALARM (1 << 5)
#define PM800_RTC1_USE_XO (1 << 7)
/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
/* buck registers */
#define PM800_SLEEP_BUCK1 (0x30)
/* BUCK Sleep Mode Register 1: BUCK[1..4] */
#define PM800_BUCK_SLP1 (0x5A)
#define PM800_BUCK1_SLP1_SHIFT 0
#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
/* page 2 GPADC: slave adder 0x02 */
#define PM800_GPADC_MEAS_EN1 (0x01)
#define PM800_MEAS_EN1_VBAT (1 << 2)
#define PM800_GPADC_MEAS_EN2 (0x02)
#define PM800_MEAS_EN2_RFTMP (1 << 0)
#define PM800_MEAS_GP0_EN (1 << 2)
#define PM800_MEAS_GP1_EN (1 << 3)
#define PM800_MEAS_GP2_EN (1 << 4)
#define PM800_MEAS_GP3_EN (1 << 5)
#define PM800_MEAS_GP4_EN (1 << 6)
#define PM800_GPADC_MISC_CONFIG1 (0x05)
#define PM800_GPADC_MISC_CONFIG2 (0x06)
#define PM800_GPADC_MISC_GPFSM_EN (1 << 0)
#define PM800_GPADC_SLOW_MODE(x) (x << 3)
#define PM800_GPADC_MISC_CONFIG3 (0x09)
#define PM800_GPADC_MISC_CONFIG4 (0x0A)
#define PM800_GPADC_PREBIAS1 (0x0F)
#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
#define PM800_GPADC_PREBIAS2 (0x10)
#define PM800_GP_BIAS_ENA1 (0x14)
#define PM800_GPADC_GP_BIAS_EN0 (1 << 0)
#define PM800_GPADC_GP_BIAS_EN1 (1 << 1)
#define PM800_GPADC_GP_BIAS_EN2 (1 << 2)
#define PM800_GPADC_GP_BIAS_EN3 (1 << 3)
#define PM800_GP_BIAS_OUT1 (0x15)
#define PM800_BIAS_OUT_GP0 (1 << 0)
#define PM800_BIAS_OUT_GP1 (1 << 1)
#define PM800_BIAS_OUT_GP2 (1 << 2)
#define PM800_BIAS_OUT_GP3 (1 << 3)
#define PM800_GPADC0_LOW_TH 0x20
#define PM800_GPADC1_LOW_TH 0x21
#define PM800_GPADC2_LOW_TH 0x22
#define PM800_GPADC3_LOW_TH 0x23
#define PM800_GPADC4_LOW_TH 0x24
#define PM800_GPADC0_UPP_TH 0x30
#define PM800_GPADC1_UPP_TH 0x31
#define PM800_GPADC2_UPP_TH 0x32
#define PM800_GPADC3_UPP_TH 0x33
#define PM800_GPADC4_UPP_TH 0x34
#define PM800_VBBAT_MEAS1 0x40
#define PM800_VBBAT_MEAS2 0x41
#define PM800_VBAT_MEAS1 0x42
#define PM800_VBAT_MEAS2 0x43
#define PM800_VSYS_MEAS1 0x44
#define PM800_VSYS_MEAS2 0x45
#define PM800_VCHG_MEAS1 0x46
#define PM800_VCHG_MEAS2 0x47
#define PM800_TINT_MEAS1 0x50
#define PM800_TINT_MEAS2 0x51
#define PM800_PMOD_MEAS1 0x52
#define PM800_PMOD_MEAS2 0x53
#define PM800_GPADC0_MEAS1 0x54
#define PM800_GPADC0_MEAS2 0x55
#define PM800_GPADC1_MEAS1 0x56
#define PM800_GPADC1_MEAS2 0x57
#define PM800_GPADC2_MEAS1 0x58
#define PM800_GPADC2_MEAS2 0x59
#define PM800_GPADC3_MEAS1 0x5A
#define PM800_GPADC3_MEAS2 0x5B
#define PM800_GPADC4_MEAS1 0x5C
#define PM800_GPADC4_MEAS2 0x5D
#define PM800_GPADC4_AVG1 0xA8
#define PM800_GPADC4_AVG2 0xA9
/* 88PM805 Registers */
#define PM805_MAIN_POWERUP (0x01)
#define PM805_INT_STATUS0 (0x02) /* for ena/dis all interrupts */
#define PM805_STATUS0_INT_CLEAR (1 << 0)
#define PM805_STATUS0_INV_INT (1 << 1)
#define PM800_STATUS0_INT_MASK (1 << 2)
#define PM805_INT_STATUS1 (0x03)
#define PM805_INT1_HP1_SHRT (1 << 0)
#define PM805_INT1_HP2_SHRT (1 << 1)
#define PM805_INT1_MIC_CONFLICT (1 << 2)
#define PM805_INT1_CLIP_FAULT (1 << 3)
#define PM805_INT1_LDO_OFF (1 << 4)
#define PM805_INT1_SRC_DPLL_LOCK (1 << 5)
#define PM805_INT_STATUS2 (0x04)
#define PM805_INT2_MIC_DET (1 << 0)
#define PM805_INT2_SHRT_BTN_DET (1 << 1)
#define PM805_INT2_VOLM_BTN_DET (1 << 2)
#define PM805_INT2_VOLP_BTN_DET (1 << 3)
#define PM805_INT2_RAW_PLL_FAULT (1 << 4)
#define PM805_INT2_FINE_PLL_FAULT (1 << 5)
#define PM805_INT_MASK1 (0x05)
#define PM805_INT_MASK2 (0x06)
#define PM805_SHRT_BTN_DET (1 << 1)
/* number of status and int reg in a row */
#define PM805_INT_REG_NUM (2)
#define PM805_MIC_DET1 (0x07)
#define PM805_MIC_DET_EN_MIC_DET (1 << 0)
#define PM805_MIC_DET2 (0x08)
#define PM805_MIC_DET_STATUS1 (0x09)
#define PM805_MIC_DET_STATUS3 (0x0A)
#define PM805_AUTO_SEQ_STATUS1 (0x0B)
#define PM805_AUTO_SEQ_STATUS2 (0x0C)
#define PM805_ADC_SETTING1 (0x10)
#define PM805_ADC_SETTING2 (0x11)
#define PM805_ADC_SETTING3 (0x11)
#define PM805_ADC_GAIN1 (0x12)
#define PM805_ADC_GAIN2 (0x13)
#define PM805_DMIC_SETTING (0x15)
#define PM805_DWS_SETTING (0x16)
#define PM805_MIC_CONFLICT_STS (0x17)
#define PM805_PDM_SETTING1 (0x20)
#define PM805_PDM_SETTING2 (0x21)
#define PM805_PDM_SETTING3 (0x22)
#define PM805_PDM_CONTROL1 (0x23)
#define PM805_PDM_CONTROL2 (0x24)
#define PM805_PDM_CONTROL3 (0x25)
#define PM805_HEADPHONE_SETTING (0x26)
#define PM805_HEADPHONE_GAIN_A2A (0x27)
#define PM805_HEADPHONE_SHORT_STATE (0x28)
#define PM805_EARPHONE_SETTING (0x29)
#define PM805_AUTO_SEQ_SETTING (0x2A)
struct pm80x_rtc_pdata {
int vrtc;
int rtc_wakeup;
};
struct pm80x_subchip {
struct i2c_client *power_page; /* chip client for power page */
struct i2c_client *gpadc_page; /* chip client for gpadc page */
struct regmap *regmap_power;
struct regmap *regmap_gpadc;
unsigned short power_page_addr; /* power page I2C address */
unsigned short gpadc_page_addr; /* gpadc page I2C address */
};
struct pm80x_chip {
struct pm80x_subchip *subchip;
struct device *dev;
struct i2c_client *client;
struct i2c_client *companion;
struct regmap *regmap;
struct regmap_irq_chip *regmap_irq_chip;
struct regmap_irq_chip_data *irq_data;
unsigned char version;
int id;
int irq;
int irq_mode;
unsigned long wu_flag;
spinlock_t lock;
};
struct pm80x_platform_data {
struct pm80x_rtc_pdata *rtc;
unsigned short power_page_addr; /* power page I2C address */
unsigned short gpadc_page_addr; /* gpadc page I2C address */
int irq_mode; /* Clear interrupt by read/write(0/1) */
int batt_det; /* enable/disable */
int (*plat_config)(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata);
};
extern const struct dev_pm_ops pm80x_pm_ops;
extern const struct regmap_config pm80x_regmap_config;
static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
irq_handler_t handler, unsigned long flags,
const char *name, void *data)
{
if (!pm80x->irq_data)
return -EINVAL;
return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
NULL, handler, flags, name, data);
}
static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
{
if (!pm80x->irq_data)
return;
free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
}
#ifdef CONFIG_PM
static inline int pm80x_dev_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
int irq = platform_get_irq(pdev, 0);
if (device_may_wakeup(dev))
set_bit((1 << irq), &chip->wu_flag);
return 0;
}
static inline int pm80x_dev_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
int irq = platform_get_irq(pdev, 0);
if (device_may_wakeup(dev))
clear_bit((1 << irq), &chip->wu_flag);
return 0;
}
#endif
extern int pm80x_init(struct i2c_client *client,
const struct i2c_device_id *id);
extern int pm80x_deinit(void);
#endif /* __LINUX_MFD_88PM80X_H */

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include/linux/mfd/88pm860x.h Normal file
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/*
* Marvell 88PM860x Interface
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_88PM860X_H
#define __LINUX_MFD_88PM860X_H
#include <linux/interrupt.h>
#define MFD_NAME_SIZE (40)
enum {
CHIP_INVALID = 0,
CHIP_PM8606,
CHIP_PM8607,
CHIP_MAX,
};
enum {
PM8606_ID_INVALID,
PM8606_ID_BACKLIGHT,
PM8606_ID_LED,
PM8606_ID_VIBRATOR,
PM8606_ID_TOUCH,
PM8606_ID_SOUND,
PM8606_ID_CHARGER,
PM8606_ID_MAX,
};
/* 8606 Registers */
#define PM8606_DCM_BOOST (0x00)
#define PM8606_PWM (0x01)
#define PM8607_MISC2 (0x42)
/* Power Up Log Register */
#define PM8607_POWER_UP_LOG (0x3F)
/* Charger Control Registers */
#define PM8607_CCNT (0x47)
#define PM8607_CHG_CTRL1 (0x48)
#define PM8607_CHG_CTRL2 (0x49)
#define PM8607_CHG_CTRL3 (0x4A)
#define PM8607_CHG_CTRL4 (0x4B)
#define PM8607_CHG_CTRL5 (0x4C)
#define PM8607_CHG_CTRL6 (0x4D)
#define PM8607_CHG_CTRL7 (0x4E)
/* Backlight Registers */
#define PM8606_WLED1A (0x02)
#define PM8606_WLED1B (0x03)
#define PM8606_WLED2A (0x04)
#define PM8606_WLED2B (0x05)
#define PM8606_WLED3A (0x06)
#define PM8606_WLED3B (0x07)
/* LED Registers */
#define PM8606_RGB2A (0x08)
#define PM8606_RGB2B (0x09)
#define PM8606_RGB2C (0x0A)
#define PM8606_RGB2D (0x0B)
#define PM8606_RGB1A (0x0C)
#define PM8606_RGB1B (0x0D)
#define PM8606_RGB1C (0x0E)
#define PM8606_RGB1D (0x0F)
#define PM8606_PREREGULATORA (0x10)
#define PM8606_PREREGULATORB (0x11)
#define PM8606_VIBRATORA (0x12)
#define PM8606_VIBRATORB (0x13)
#define PM8606_VCHG (0x14)
#define PM8606_VSYS (0x15)
#define PM8606_MISC (0x16)
#define PM8606_CHIP_ID (0x17)
#define PM8606_STATUS (0x18)
#define PM8606_FLAGS (0x19)
#define PM8606_PROTECTA (0x1A)
#define PM8606_PROTECTB (0x1B)
#define PM8606_PROTECTC (0x1C)
/* Bit definitions of PM8606 registers */
#define PM8606_DCM_500MA (0x0) /* current limit */
#define PM8606_DCM_750MA (0x1)
#define PM8606_DCM_1000MA (0x2)
#define PM8606_DCM_1250MA (0x3)
#define PM8606_DCM_250MV (0x0 << 2)
#define PM8606_DCM_300MV (0x1 << 2)
#define PM8606_DCM_350MV (0x2 << 2)
#define PM8606_DCM_400MV (0x3 << 2)
#define PM8606_PWM_31200HZ (0x0)
#define PM8606_PWM_15600HZ (0x1)
#define PM8606_PWM_7800HZ (0x2)
#define PM8606_PWM_3900HZ (0x3)
#define PM8606_PWM_1950HZ (0x4)
#define PM8606_PWM_976HZ (0x5)
#define PM8606_PWM_488HZ (0x6)
#define PM8606_PWM_244HZ (0x7)
#define PM8606_PWM_FREQ_MASK (0x7)
#define PM8606_WLED_ON (1 << 0)
#define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1)
#define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5)
#define PM8606_VSYS_EN (1 << 1)
#define PM8606_MISC_OSC_EN (1 << 4)
enum {
PM8607_ID_BUCK1 = 0,
PM8607_ID_BUCK2,
PM8607_ID_BUCK3,
PM8607_ID_LDO1,
PM8607_ID_LDO2,
PM8607_ID_LDO3,
PM8607_ID_LDO4,
PM8607_ID_LDO5,
PM8607_ID_LDO6,
PM8607_ID_LDO7,
PM8607_ID_LDO8,
PM8607_ID_LDO9,
PM8607_ID_LDO10,
PM8607_ID_LDO11,
PM8607_ID_LDO12,
PM8607_ID_LDO13,
PM8607_ID_LDO14,
PM8607_ID_LDO15,
PM8606_ID_PREG,
PM8607_ID_RG_MAX,
};
/* 8607 chip ID is 0x40 or 0x50 */
#define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */
/* Interrupt Registers */
#define PM8607_STATUS_1 (0x01)
#define PM8607_STATUS_2 (0x02)
#define PM8607_INT_STATUS1 (0x03)
#define PM8607_INT_STATUS2 (0x04)
#define PM8607_INT_STATUS3 (0x05)
#define PM8607_INT_MASK_1 (0x06)
#define PM8607_INT_MASK_2 (0x07)
#define PM8607_INT_MASK_3 (0x08)
/* Regulator Control Registers */
#define PM8607_LDO1 (0x10)
#define PM8607_LDO2 (0x11)
#define PM8607_LDO3 (0x12)
#define PM8607_LDO4 (0x13)
#define PM8607_LDO5 (0x14)
#define PM8607_LDO6 (0x15)
#define PM8607_LDO7 (0x16)
#define PM8607_LDO8 (0x17)
#define PM8607_LDO9 (0x18)
#define PM8607_LDO10 (0x19)
#define PM8607_LDO12 (0x1A)
#define PM8607_LDO14 (0x1B)
#define PM8607_SLEEP_MODE1 (0x1C)
#define PM8607_SLEEP_MODE2 (0x1D)
#define PM8607_SLEEP_MODE3 (0x1E)
#define PM8607_SLEEP_MODE4 (0x1F)
#define PM8607_GO (0x20)
#define PM8607_SLEEP_BUCK1 (0x21)
#define PM8607_SLEEP_BUCK2 (0x22)
#define PM8607_SLEEP_BUCK3 (0x23)
#define PM8607_BUCK1 (0x24)
#define PM8607_BUCK2 (0x25)
#define PM8607_BUCK3 (0x26)
#define PM8607_BUCK_CONTROLS (0x27)
#define PM8607_SUPPLIES_EN11 (0x2B)
#define PM8607_SUPPLIES_EN12 (0x2C)
#define PM8607_GROUP1 (0x2D)
#define PM8607_GROUP2 (0x2E)
#define PM8607_GROUP3 (0x2F)
#define PM8607_GROUP4 (0x30)
#define PM8607_GROUP5 (0x31)
#define PM8607_GROUP6 (0x32)
#define PM8607_SUPPLIES_EN21 (0x33)
#define PM8607_SUPPLIES_EN22 (0x34)
/* Vibrator Control Registers */
#define PM8607_VIBRATOR_SET (0x28)
#define PM8607_VIBRATOR_PWM (0x29)
/* GPADC Registers */
#define PM8607_GP_BIAS1 (0x4F)
#define PM8607_MEAS_EN1 (0x50)
#define PM8607_MEAS_EN2 (0x51)
#define PM8607_MEAS_EN3 (0x52)
#define PM8607_MEAS_OFF_TIME1 (0x53)
#define PM8607_MEAS_OFF_TIME2 (0x54)
#define PM8607_TSI_PREBIAS (0x55) /* prebias time */
#define PM8607_PD_PREBIAS (0x56) /* prebias time */
#define PM8607_GPADC_MISC1 (0x57)
/* bit definitions of MEAS_EN1*/
#define PM8607_MEAS_EN1_VBAT (1 << 0)
#define PM8607_MEAS_EN1_VCHG (1 << 1)
#define PM8607_MEAS_EN1_VSYS (1 << 2)
#define PM8607_MEAS_EN1_TINT (1 << 3)
#define PM8607_MEAS_EN1_RFTMP (1 << 4)
#define PM8607_MEAS_EN1_TBAT (1 << 5)
#define PM8607_MEAS_EN1_GPADC2 (1 << 6)
#define PM8607_MEAS_EN1_GPADC3 (1 << 7)
/* Battery Monitor Registers */
#define PM8607_GP_BIAS2 (0x5A)
#define PM8607_VBAT_LOWTH (0x5B)
#define PM8607_VCHG_LOWTH (0x5C)
#define PM8607_VSYS_LOWTH (0x5D)
#define PM8607_TINT_LOWTH (0x5E)
#define PM8607_GPADC0_LOWTH (0x5F)
#define PM8607_GPADC1_LOWTH (0x60)
#define PM8607_GPADC2_LOWTH (0x61)
#define PM8607_GPADC3_LOWTH (0x62)
#define PM8607_VBAT_HIGHTH (0x63)
#define PM8607_VCHG_HIGHTH (0x64)
#define PM8607_VSYS_HIGHTH (0x65)
#define PM8607_TINT_HIGHTH (0x66)
#define PM8607_GPADC0_HIGHTH (0x67)
#define PM8607_GPADC1_HIGHTH (0x68)
#define PM8607_GPADC2_HIGHTH (0x69)
#define PM8607_GPADC3_HIGHTH (0x6A)
#define PM8607_IBAT_MEAS1 (0x6B)
#define PM8607_IBAT_MEAS2 (0x6C)
#define PM8607_VBAT_MEAS1 (0x6D)
#define PM8607_VBAT_MEAS2 (0x6E)
#define PM8607_VCHG_MEAS1 (0x6F)
#define PM8607_VCHG_MEAS2 (0x70)
#define PM8607_VSYS_MEAS1 (0x71)
#define PM8607_VSYS_MEAS2 (0x72)
#define PM8607_TINT_MEAS1 (0x73)
#define PM8607_TINT_MEAS2 (0x74)
#define PM8607_GPADC0_MEAS1 (0x75)
#define PM8607_GPADC0_MEAS2 (0x76)
#define PM8607_GPADC1_MEAS1 (0x77)
#define PM8607_GPADC1_MEAS2 (0x78)
#define PM8607_GPADC2_MEAS1 (0x79)
#define PM8607_GPADC2_MEAS2 (0x7A)
#define PM8607_GPADC3_MEAS1 (0x7B)
#define PM8607_GPADC3_MEAS2 (0x7C)
#define PM8607_CCNT_MEAS1 (0x95)
#define PM8607_CCNT_MEAS2 (0x96)
#define PM8607_VBAT_AVG (0x97)
#define PM8607_VCHG_AVG (0x98)
#define PM8607_VSYS_AVG (0x99)
#define PM8607_VBAT_MIN (0x9A)
#define PM8607_VCHG_MIN (0x9B)
#define PM8607_VSYS_MIN (0x9C)
#define PM8607_VBAT_MAX (0x9D)
#define PM8607_VCHG_MAX (0x9E)
#define PM8607_VSYS_MAX (0x9F)
#define PM8607_GPADC_MISC2 (0x59)
#define PM8607_GPADC0_GP_BIAS_A0 (1 << 0)
#define PM8607_GPADC1_GP_BIAS_A1 (1 << 1)
#define PM8607_GPADC2_GP_BIAS_A2 (1 << 2)
#define PM8607_GPADC3_GP_BIAS_A3 (1 << 3)
#define PM8607_GPADC2_GP_BIAS_OUT2 (1 << 6)
/* RTC Control Registers */
#define PM8607_RTC1 (0xA0)
#define PM8607_RTC_COUNTER1 (0xA1)
#define PM8607_RTC_COUNTER2 (0xA2)
#define PM8607_RTC_COUNTER3 (0xA3)
#define PM8607_RTC_COUNTER4 (0xA4)
#define PM8607_RTC_EXPIRE1 (0xA5)
#define PM8607_RTC_EXPIRE2 (0xA6)
#define PM8607_RTC_EXPIRE3 (0xA7)
#define PM8607_RTC_EXPIRE4 (0xA8)
#define PM8607_RTC_TRIM1 (0xA9)
#define PM8607_RTC_TRIM2 (0xAA)
#define PM8607_RTC_TRIM3 (0xAB)
#define PM8607_RTC_TRIM4 (0xAC)
#define PM8607_RTC_MISC1 (0xAD)
#define PM8607_RTC_MISC2 (0xAE)
#define PM8607_RTC_MISC3 (0xAF)
/* Misc Registers */
#define PM8607_CHIP_ID (0x00)
#define PM8607_B0_MISC1 (0x0C)
#define PM8607_LDO1 (0x10)
#define PM8607_DVC3 (0x26)
#define PM8607_A1_MISC1 (0x40)
/* bit definitions of Status Query Interface */
#define PM8607_STATUS_CC (1 << 3)
#define PM8607_STATUS_PEN (1 << 4)
#define PM8607_STATUS_HEADSET (1 << 5)
#define PM8607_STATUS_HOOK (1 << 6)
#define PM8607_STATUS_MICIN (1 << 7)
#define PM8607_STATUS_ONKEY (1 << 8)
#define PM8607_STATUS_EXTON (1 << 9)
#define PM8607_STATUS_CHG (1 << 10)
#define PM8607_STATUS_BAT (1 << 11)
#define PM8607_STATUS_VBUS (1 << 12)
#define PM8607_STATUS_OV (1 << 13)
/* bit definitions of BUCK3 */
#define PM8607_BUCK3_DOUBLE (1 << 6)
/* bit definitions of Misc1 */
#define PM8607_A1_MISC1_PI2C (1 << 0)
#define PM8607_B0_MISC1_INV_INT (1 << 0)
#define PM8607_B0_MISC1_INT_CLEAR (1 << 1)
#define PM8607_B0_MISC1_INT_MASK (1 << 2)
#define PM8607_B0_MISC1_PI2C (1 << 3)
#define PM8607_B0_MISC1_RESET (1 << 6)
/* bits definitions of GPADC */
#define PM8607_GPADC_EN (1 << 0)
#define PM8607_GPADC_PREBIAS_MASK (3 << 1)
#define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */
#define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */
#define PM8607_GPADC_SW_CAL_MASK (1 << 7)
#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
#define PM8607_PD_PRECHG_MASK (7 << 5)
#define PM8606_REF_GP_OSC_OFF 0
#define PM8606_REF_GP_OSC_ON 1
#define PM8606_REF_GP_OSC_UNKNOWN 2
/* Clients of reference group and 8MHz oscillator in 88PM8606 */
enum pm8606_ref_gp_and_osc_clients {
REF_GP_NO_CLIENTS = 0,
WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/
WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/
WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/
RGB1_ENABLE = (1<<3), /*PF 0x07.1*/
RGB2_ENABLE = (1<<4), /*PF 0x07.2*/
LDO_VBR_EN = (1<<5), /*PF 0x12.0*/
REF_GP_MAX_CLIENT = 0xFFFF
};
/* Interrupt Number in 88PM8607 */
enum {
PM8607_IRQ_ONKEY,
PM8607_IRQ_EXTON,
PM8607_IRQ_CHG,
PM8607_IRQ_BAT,
PM8607_IRQ_RTC,
PM8607_IRQ_CC,
PM8607_IRQ_VBAT,
PM8607_IRQ_VCHG,
PM8607_IRQ_VSYS,
PM8607_IRQ_TINT,
PM8607_IRQ_GPADC0,
PM8607_IRQ_GPADC1,
PM8607_IRQ_GPADC2,
PM8607_IRQ_GPADC3,
PM8607_IRQ_AUDIO_SHORT,
PM8607_IRQ_PEN,
PM8607_IRQ_HEADSET,
PM8607_IRQ_HOOK,
PM8607_IRQ_MICIN,
PM8607_IRQ_CHG_FAIL,
PM8607_IRQ_CHG_DONE,
PM8607_IRQ_CHG_FAULT,
};
enum {
PM8607_CHIP_A0 = 0x40,
PM8607_CHIP_A1 = 0x41,
PM8607_CHIP_B0 = 0x48,
};
struct pm860x_chip {
struct device *dev;
struct mutex irq_lock;
struct mutex osc_lock;
struct i2c_client *client;
struct i2c_client *companion; /* companion chip client */
struct regmap *regmap;
struct regmap *regmap_companion;
int buck3_double; /* DVC ramp slope double */
int companion_addr;
unsigned short osc_vote;
int id;
int irq_mode;
int irq_base;
int core_irq;
unsigned char chip_version;
unsigned char osc_status;
unsigned int wakeup_flag;
};
enum {
GI2C_PORT = 0,
PI2C_PORT,
};
struct pm860x_backlight_pdata {
int pwm;
int iset;
};
struct pm860x_led_pdata {
int iset;
};
struct pm860x_rtc_pdata {
int (*sync)(unsigned int ticks);
int vrtc;
};
struct pm860x_touch_pdata {
int gpadc_prebias;
int slot_cycle;
int off_scale;
int sw_cal;
int tsi_prebias; /* time, slot */
int pen_prebias; /* time, slot */
int pen_prechg; /* time, slot */
int res_x; /* resistor of Xplate */
unsigned long flags;
};
struct pm860x_power_pdata {
int max_capacity;
int resistor;
};
struct pm860x_platform_data {
struct pm860x_backlight_pdata *backlight;
struct pm860x_led_pdata *led;
struct pm860x_rtc_pdata *rtc;
struct pm860x_touch_pdata *touch;
struct pm860x_power_pdata *power;
struct regulator_init_data *buck1;
struct regulator_init_data *buck2;
struct regulator_init_data *buck3;
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldo8;
struct regulator_init_data *ldo9;
struct regulator_init_data *ldo10;
struct regulator_init_data *ldo12;
struct regulator_init_data *ldo_vibrator;
struct regulator_init_data *ldo14;
struct charger_desc *chg_desc;
int companion_addr; /* I2C address of companion chip */
int i2c_port; /* Controlled by GI2C or PI2C */
int irq_mode; /* Clear interrupt by read/write(0/1) */
int irq_base; /* IRQ base number of 88pm860x */
int num_leds;
int num_backlights;
};
extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
extern int pm860x_reg_read(struct i2c_client *, int);
extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_page_reg_read(struct i2c_client *, int);
extern int pm860x_page_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_page_bulk_read(struct i2c_client *, int, int,
unsigned char *);
extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
unsigned char *);
extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
#endif /* __LINUX_MFD_88PM860X_H */

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/*
* linux/include/linux/mfd/aat2870.h
*
* Copyright (c) 2011, NVIDIA Corporation.
* Author: Jin Park <jinyoungp@nvidia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __LINUX_MFD_AAT2870_H
#define __LINUX_MFD_AAT2870_H
#include <linux/debugfs.h>
#include <linux/i2c.h>
/* Register offsets */
#define AAT2870_BL_CH_EN 0x00
#define AAT2870_BLM 0x01
#define AAT2870_BLS 0x02
#define AAT2870_BL1 0x03
#define AAT2870_BL2 0x04
#define AAT2870_BL3 0x05
#define AAT2870_BL4 0x06
#define AAT2870_BL5 0x07
#define AAT2870_BL6 0x08
#define AAT2870_BL7 0x09
#define AAT2870_BL8 0x0A
#define AAT2870_FLR 0x0B
#define AAT2870_FM 0x0C
#define AAT2870_FS 0x0D
#define AAT2870_ALS_CFG0 0x0E
#define AAT2870_ALS_CFG1 0x0F
#define AAT2870_ALS_CFG2 0x10
#define AAT2870_AMB 0x11
#define AAT2870_ALS0 0x12
#define AAT2870_ALS1 0x13
#define AAT2870_ALS2 0x14
#define AAT2870_ALS3 0x15
#define AAT2870_ALS4 0x16
#define AAT2870_ALS5 0x17
#define AAT2870_ALS6 0x18
#define AAT2870_ALS7 0x19
#define AAT2870_ALS8 0x1A
#define AAT2870_ALS9 0x1B
#define AAT2870_ALSA 0x1C
#define AAT2870_ALSB 0x1D
#define AAT2870_ALSC 0x1E
#define AAT2870_ALSD 0x1F
#define AAT2870_ALSE 0x20
#define AAT2870_ALSF 0x21
#define AAT2870_SUB_SET 0x22
#define AAT2870_SUB_CTRL 0x23
#define AAT2870_LDO_AB 0x24
#define AAT2870_LDO_CD 0x25
#define AAT2870_LDO_EN 0x26
#define AAT2870_REG_NUM 0x27
/* Device IDs */
enum aat2870_id {
AAT2870_ID_BL,
AAT2870_ID_LDOA,
AAT2870_ID_LDOB,
AAT2870_ID_LDOC,
AAT2870_ID_LDOD
};
/* Backlight channels */
#define AAT2870_BL_CH1 0x01
#define AAT2870_BL_CH2 0x02
#define AAT2870_BL_CH3 0x04
#define AAT2870_BL_CH4 0x08
#define AAT2870_BL_CH5 0x10
#define AAT2870_BL_CH6 0x20
#define AAT2870_BL_CH7 0x40
#define AAT2870_BL_CH8 0x80
#define AAT2870_BL_CH_ALL 0xFF
/* Backlight current magnitude (mA) */
enum aat2870_current {
AAT2870_CURRENT_0_45 = 1,
AAT2870_CURRENT_0_90,
AAT2870_CURRENT_1_80,
AAT2870_CURRENT_2_70,
AAT2870_CURRENT_3_60,
AAT2870_CURRENT_4_50,
AAT2870_CURRENT_5_40,
AAT2870_CURRENT_6_30,
AAT2870_CURRENT_7_20,
AAT2870_CURRENT_8_10,
AAT2870_CURRENT_9_00,
AAT2870_CURRENT_9_90,
AAT2870_CURRENT_10_8,
AAT2870_CURRENT_11_7,
AAT2870_CURRENT_12_6,
AAT2870_CURRENT_13_5,
AAT2870_CURRENT_14_4,
AAT2870_CURRENT_15_3,
AAT2870_CURRENT_16_2,
AAT2870_CURRENT_17_1,
AAT2870_CURRENT_18_0,
AAT2870_CURRENT_18_9,
AAT2870_CURRENT_19_8,
AAT2870_CURRENT_20_7,
AAT2870_CURRENT_21_6,
AAT2870_CURRENT_22_5,
AAT2870_CURRENT_23_4,
AAT2870_CURRENT_24_3,
AAT2870_CURRENT_25_2,
AAT2870_CURRENT_26_1,
AAT2870_CURRENT_27_0,
AAT2870_CURRENT_27_9
};
struct aat2870_register {
bool readable;
bool writeable;
u8 value;
};
struct aat2870_data {
struct device *dev;
struct i2c_client *client;
struct mutex io_lock;
struct aat2870_register *reg_cache; /* register cache */
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
bool is_enable;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
/* i2c io funcntions */
int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
/* for debugfs */
struct dentry *dentry_root;
struct dentry *dentry_reg;
};
struct aat2870_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct aat2870_platform_data {
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
struct aat2870_subdev_info *subdevs;
int num_subdevs;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
};
struct aat2870_bl_platform_data {
/* backlight channels, default is AAT2870_BL_CH_ALL */
int channels;
/* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
int max_current;
/* maximum brightness, default is 255 */
int max_brightness;
};
#endif /* __LINUX_MFD_AAT2870_H */

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/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
*
*/
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_AB3100_H
#define MFD_AB3100_H
#define AB3100_P1A 0xc0
#define AB3100_P1B 0xc1
#define AB3100_P1C 0xc2
#define AB3100_P1D 0xc3
#define AB3100_P1E 0xc4
#define AB3100_P1F 0xc5
#define AB3100_P1G 0xc6
#define AB3100_R2A 0xc7
#define AB3100_R2B 0xc8
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
* for event notification broadcasts.
*/
#define AB3100_EVENTA1_ONSWA (0x01<<16)
#define AB3100_EVENTA1_ONSWB (0x02<<16)
#define AB3100_EVENTA1_ONSWC (0x04<<16)
#define AB3100_EVENTA1_DCIO (0x08<<16)
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
#define AB3100_EVENTA1_VBUS (0x40<<16)
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
#define AB3100_EVENTA2_READY_TX (0x01<<8)
#define AB3100_EVENTA2_READY_RX (0x02<<8)
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
#define AB3100_EVENTA2_MIDR (0x20<<8)
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
#define AB3100_EVENTA2_ALARM (0x80<<8)
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
/* AB3100, STR register flags */
#define AB3100_STR_ONSWA (0x01)
#define AB3100_STR_ONSWB (0x02)
#define AB3100_STR_ONSWC (0x04)
#define AB3100_STR_DCIO (0x08)
#define AB3100_STR_BOOT_MODE (0x10)
#define AB3100_STR_SIM_OFF (0x20)
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
/*
* AB3100 contains 8 regulators, one external regulator controller
* and a buck converter, further the LDO E and buck converter can
* have separate settings if they are in sleep mode, this is
* modeled as a separate regulator.
*/
#define AB3100_NUM_REGULATORS 10
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
* @dev: pointer to the containing device
* @i2c_client: I2C client for this chip
* @testreg_client: secondary client for test registers
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @event_subscribers: event subscribers are listed here
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*
* This struct is PRIVATE and devices using it should NOT
* access ANY fields. It is used as a token for calling the
* AB3100 functions.
*/
struct ab3100 {
struct mutex access_mutex;
struct device *dev;
struct i2c_client *i2c_client;
struct i2c_client *testreg_client;
char chip_name[32];
u8 chip_id;
struct blocking_notifier_head event_subscribers;
u8 startup_events[3];
bool startup_events_read;
};
/**
* struct ab3100_platform_data
* Data supplied to initialize board connections to the AB3100
* @reg_constraints: regulator constraints for target board
* the order of these constraints are: LDO A, C, D, E,
* F, G, H, K, EXT and BUCK.
* @reg_initvals: initial values for the regulator registers
* plus two sleep settings for LDO E and the BUCK converter.
* exactly AB3100_NUM_REGULATORS+2 values must be sent in.
* Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
* BUCK sleep, LDO D. (LDO D need to be initialized last.)
* @external_voltage: voltage level of the external regulator.
*/
struct ab3100_platform_data {
struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
u8 reg_initvals[AB3100_NUM_REGULATORS+2];
int external_voltage;
};
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
#endif /* MFD_AB3100_H */

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/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* ABX500 core access functions.
* The abx500 interface is used for the Analog Baseband chips.
*
* Author: Mattias Wallin <mattias.wallin@stericsson.com>
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
* Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_ABX500_H
#define MFD_ABX500_H
/**
* struct abx500_init_setting
* Initial value of the registers for driver to use during setup.
*/
struct abx500_init_settings {
u8 bank;
u8 reg;
u8 setting;
};
/* Battery driver related data */
/*
* ADC for the battery thermistor.
* When using the ABx500_ADC_THERM_BATCTRL the battery ID resistor is combined
* with a NTC resistor to both identify the battery and to measure its
* temperature. Different phone manufactures uses different techniques to both
* identify the battery and to read its temperature.
*/
enum abx500_adc_therm {
ABx500_ADC_THERM_BATCTRL,
ABx500_ADC_THERM_BATTEMP,
};
/**
* struct abx500_res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct abx500_res_to_temp {
int temp;
int resist;
};
/**
* struct abx500_v_to_cap - Table for translating voltage to capacity
* @voltage: Voltage in mV
* @capacity: Capacity in percent
*/
struct abx500_v_to_cap {
int voltage;
int capacity;
};
/* Forward declaration */
struct abx500_fg;
/**
* struct abx500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @overbat_threshold: Over battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
* @pcut_enable: Enable power cut feature in ab8505
* @pcut_max_time: Max time threshold
* @pcut_flag_time: Flagtime threshold
* @pcut_max_restart: Max number of restarts
* @pcut_debounce_time: Sets battery debounce time
*/
struct abx500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int overbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
bool pcut_enable;
u8 pcut_max_time;
u8 pcut_flag_time;
u8 pcut_max_restart;
u8 pcut_debounce_time;
};
/**
* struct abx500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct abx500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct abx500_battery_type - different batteries supported
* @name: battery technology
* @resis_high: battery upper resistance limit
* @resis_low: battery lower resistance limit
* @charge_full_design: Maximum battery capacity in mAh
* @nominal_voltage: Nominal voltage of the battery in mV
* @termination_vol: max voltage upto which battery can be charged
* @termination_curr battery charging termination current in mA
* @recharge_cap battery capacity limit that will trigger a new
* full charging cycle in the case where maintenan-
* -ce charging has been disabled
* @normal_cur_lvl: charger current in normal state in mA
* @normal_vol_lvl: charger voltage in normal state in mV
* @maint_a_cur_lvl: charger current in maintenance A state in mA
* @maint_a_vol_lvl: charger voltage in maintenance A state in mV
* @maint_a_chg_timer_h: charge time in maintenance A state
* @maint_b_cur_lvl: charger current in maintenance B state in mA
* @maint_b_vol_lvl: charger voltage in maintenance B state in mV
* @maint_b_chg_timer_h: charge time in maintenance B state
* @low_high_cur_lvl: charger current in temp low/high state in mA
* @low_high_vol_lvl: charger voltage in temp low/high state in mV'
* @battery_resistance: battery inner resistance in mOhm.
* @n_r_t_tbl_elements: number of elements in r_to_t_tbl
* @r_to_t_tbl: table containing resistance to temp points
* @n_v_cap_tbl_elements: number of elements in v_to_cap_tbl
* @v_to_cap_tbl: Voltage to capacity (in %) table
* @n_batres_tbl_elements number of elements in the batres_tbl
* @batres_tbl battery internal resistance vs temperature table
*/
struct abx500_battery_type {
int name;
int resis_high;
int resis_low;
int charge_full_design;
int nominal_voltage;
int termination_vol;
int termination_curr;
int recharge_cap;
int normal_cur_lvl;
int normal_vol_lvl;
int maint_a_cur_lvl;
int maint_a_vol_lvl;
int maint_a_chg_timer_h;
int maint_b_cur_lvl;
int maint_b_vol_lvl;
int maint_b_chg_timer_h;
int low_high_cur_lvl;
int low_high_vol_lvl;
int battery_resistance;
int n_temp_tbl_elements;
const struct abx500_res_to_temp *r_to_t_tbl;
int n_v_cap_tbl_elements;
const struct abx500_v_to_cap *v_to_cap_tbl;
int n_batres_tbl_elements;
const struct batres_vs_temp *batres_tbl;
};
/**
* struct abx500_bm_capacity_levels - abx500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct abx500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct abx500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct abx500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct abx500_bm_data - abx500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_now present battery temperature
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @capacity_scaling indicates whether capacity scaling is to be used
* @abx500_adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @auto_trig flag to enable auto adc trigger
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @n_chg_out_curr number of elements in array chg_output_curr
* @n_chg_in_curr number of elements in array chg_input_curr
* @chg_output_curr charger output current level map
* @chg_input_curr charger input current level map
* @maxi maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct abx500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_now;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool autopower_cfg;
bool ac_enabled;
bool usb_enabled;
bool usb_power_path;
bool no_maintenance;
bool capacity_scaling;
bool chg_unknown_bat;
bool enable_overshoot;
bool auto_trig;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
int n_chg_out_curr;
int n_chg_in_curr;
int *chg_output_curr;
int *chg_input_curr;
const struct abx500_maxim_parameters *maxi;
const struct abx500_bm_capacity_levels *cap_levels;
struct abx500_battery_type *bat_type;
const struct abx500_bm_charger_parameters *chg_params;
const struct abx500_fg_parameters *fg_params;
};
enum {
NTC_EXTERNAL = 0,
NTC_INTERNAL,
};
int ab8500_bm_of_probe(struct device *dev,
struct device_node *np,
struct abx500_bm_data *bm);
int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 value);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 *value);
int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
/**
* abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
* target register
*
* @dev: The AB sub device.
* @bank: The i2c bank number.
* @bitmask: The bit mask to use.
* @bitvalues: The new bit values.
*
* Updates the value of an AB register:
* value -> ((value & ~bitmask) | (bitvalues & bitmask))
*/
int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
u8 reg, u8 bitmask, u8 bitvalues);
int abx500_get_chip_id(struct device *dev);
int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
void abx500_dump_all_banks(void);
struct abx500_ops {
int (*get_chip_id) (struct device *);
int (*get_register) (struct device *, u8, u8, u8 *);
int (*set_register) (struct device *, u8, u8, u8);
int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
int (*event_registers_startup_state_get) (struct device *, u8 *);
int (*startup_irq_enabled) (struct device *, unsigned int);
void (*dump_all_banks) (struct device *);
};
int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
void abx500_remove_ops(struct device *dev);
#endif

479
include/linux/mfd/abx500/ab8500-bm.h Normal file
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/*
* Copyright ST-Ericsson 2012.
*
* Author: Arun Murthy <arun.murthy@stericsson.com>
* Licensed under GPLv2.
*/
#ifndef _AB8500_BM_H
#define _AB8500_BM_H
#include <linux/kernel.h>
#include <linux/mfd/abx500.h>
/*
* System control 2 register offsets.
* bank = 0x02
*/
#define AB8500_MAIN_WDOG_CTRL_REG 0x01
#define AB8500_LOW_BAT_REG 0x03
#define AB8500_BATT_OK_REG 0x04
/*
* USB/ULPI register offsets
* Bank : 0x5
*/
#define AB8500_USB_LINE_STAT_REG 0x80
#define AB8500_USB_LINE_CTRL2_REG 0x82
#define AB8500_USB_LINK1_STAT_REG 0x94
/*
* Charger / status register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_STATUS1_REG 0x00
#define AB8500_CH_STATUS2_REG 0x01
#define AB8500_CH_USBCH_STAT1_REG 0x02
#define AB8500_CH_USBCH_STAT2_REG 0x03
#define AB8540_CH_USBCH_STAT3_REG 0x04
#define AB8500_CH_STAT_REG 0x05
/*
* Charger / control register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_VOLT_LVL_REG 0x40
#define AB8500_CH_VOLT_LVL_MAX_REG 0x41 /*Only in Cut2.0*/
#define AB8500_CH_OPT_CRNTLVL_REG 0x42
#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x43 /*Only in Cut2.0*/
#define AB8500_CH_WD_TIMER_REG 0x50
#define AB8500_CHARG_WD_CTRL 0x51
#define AB8500_BTEMP_HIGH_TH 0x52
#define AB8500_LED_INDICATOR_PWM_CTRL 0x53
#define AB8500_LED_INDICATOR_PWM_DUTY 0x54
#define AB8500_BATT_OVV 0x55
#define AB8500_CHARGER_CTRL 0x56
#define AB8500_BAT_CTRL_CURRENT_SOURCE 0x60 /*Only in Cut2.0*/
/*
* Charger / main control register offsets
* Bank : 0x0B
*/
#define AB8500_MCH_CTRL1 0x80
#define AB8500_MCH_CTRL2 0x81
#define AB8500_MCH_IPT_CURLVL_REG 0x82
#define AB8500_CH_WD_REG 0x83
/*
* Charger / USB control register offsets
* Bank : 0x0B
*/
#define AB8500_USBCH_CTRL1_REG 0xC0
#define AB8500_USBCH_CTRL2_REG 0xC1
#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2
#define AB8540_USB_PP_MODE_REG 0xC5
#define AB8540_USB_PP_CHR_REG 0xC6
/*
* Gas Gauge register offsets
* Bank : 0x0C
*/
#define AB8500_GASG_CC_CTRL_REG 0x00
#define AB8500_GASG_CC_ACCU1_REG 0x01
#define AB8500_GASG_CC_ACCU2_REG 0x02
#define AB8500_GASG_CC_ACCU3_REG 0x03
#define AB8500_GASG_CC_ACCU4_REG 0x04
#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x05
#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x06
#define AB8500_GASG_CC_SMPL_CNVL_REG 0x07
#define AB8500_GASG_CC_SMPL_CNVH_REG 0x08
#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x09
#define AB8500_GASG_CC_OFFSET_REG 0x0A
#define AB8500_GASG_CC_NCOV_ACCU 0x10
#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x11
#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x12
#define AB8500_GASG_CC_NCOV_ACCU_MED 0x13
#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x14
/*
* Interrupt register offsets
* Bank : 0x0E
*/
#define AB8500_IT_SOURCE2_REG 0x01
#define AB8500_IT_SOURCE21_REG 0x14
/*
* RTC register offsets
* Bank: 0x0F
*/
#define AB8500_RTC_BACKUP_CHG_REG 0x0C
#define AB8500_RTC_CC_CONF_REG 0x01
#define AB8500_RTC_CTRL_REG 0x0B
#define AB8500_RTC_CTRL1_REG 0x11
/*
* OTP register offsets
* Bank : 0x15
*/
#define AB8500_OTP_CONF_15 0x0E
/* GPADC constants from AB8500 spec, UM0836 */
#define ADC_RESOLUTION 1024
#define ADC_CH_MAIN_MIN 0
#define ADC_CH_MAIN_MAX 20030
#define ADC_CH_VBUS_MIN 0
#define ADC_CH_VBUS_MAX 20030
#define ADC_CH_VBAT_MIN 2300
#define ADC_CH_VBAT_MAX 4800
#define ADC_CH_BKBAT_MIN 0
#define ADC_CH_BKBAT_MAX 3200
/* Main charge i/p current */
#define MAIN_CH_IP_CUR_0P9A 0x80
#define MAIN_CH_IP_CUR_1P0A 0x90
#define MAIN_CH_IP_CUR_1P1A 0xA0
#define MAIN_CH_IP_CUR_1P2A 0xB0
#define MAIN_CH_IP_CUR_1P3A 0xC0
#define MAIN_CH_IP_CUR_1P4A 0xD0
#define MAIN_CH_IP_CUR_1P5A 0xE0
/* ChVoltLevel */
#define CH_VOL_LVL_3P5 0x00
#define CH_VOL_LVL_4P0 0x14
#define CH_VOL_LVL_4P05 0x16
#define CH_VOL_LVL_4P1 0x1B
#define CH_VOL_LVL_4P15 0x20
#define CH_VOL_LVL_4P2 0x25
#define CH_VOL_LVL_4P6 0x4D
/* ChOutputCurrentLevel */
#define CH_OP_CUR_LVL_0P1 0x00
#define CH_OP_CUR_LVL_0P2 0x01
#define CH_OP_CUR_LVL_0P3 0x02
#define CH_OP_CUR_LVL_0P4 0x03
#define CH_OP_CUR_LVL_0P5 0x04
#define CH_OP_CUR_LVL_0P6 0x05
#define CH_OP_CUR_LVL_0P7 0x06
#define CH_OP_CUR_LVL_0P8 0x07
#define CH_OP_CUR_LVL_0P9 0x08
#define CH_OP_CUR_LVL_1P4 0x0D
#define CH_OP_CUR_LVL_1P5 0x0E
#define CH_OP_CUR_LVL_1P6 0x0F
#define CH_OP_CUR_LVL_2P 0x3F
/* BTEMP High thermal limits */
#define BTEMP_HIGH_TH_57_0 0x00
#define BTEMP_HIGH_TH_52 0x01
#define BTEMP_HIGH_TH_57_1 0x02
#define BTEMP_HIGH_TH_62 0x03
/* current is mA */
#define USB_0P1A 100
#define USB_0P2A 200
#define USB_0P3A 300
#define USB_0P4A 400
#define USB_0P5A 500
#define LOW_BAT_3P1V 0x20
#define LOW_BAT_2P3V 0x00
#define LOW_BAT_RESET 0x01
#define LOW_BAT_ENABLE 0x01
/* Backup battery constants */
#define BUP_ICH_SEL_50UA 0x00
#define BUP_ICH_SEL_150UA 0x04
#define BUP_ICH_SEL_300UA 0x08
#define BUP_ICH_SEL_700UA 0x0C
enum bup_vch_sel {
BUP_VCH_SEL_2P5V,
BUP_VCH_SEL_2P6V,
BUP_VCH_SEL_2P8V,
BUP_VCH_SEL_3P1V,
/*
* Note that the following 5 values 2.7v, 2.9v, 3.0v, 3.2v, 3.3v
* are only available on ab8540. You can't choose these 5
* voltage on ab8500/ab8505/ab9540.
*/
BUP_VCH_SEL_2P7V,
BUP_VCH_SEL_2P9V,
BUP_VCH_SEL_3P0V,
BUP_VCH_SEL_3P2V,
BUP_VCH_SEL_3P3V,
};
#define BUP_VCH_RANGE 0x02
#define VBUP33_VRTCN 0x01
/* Battery OVV constants */
#define BATT_OVV_ENA 0x02
#define BATT_OVV_TH_3P7 0x00
#define BATT_OVV_TH_4P75 0x01
/* A value to indicate over voltage */
#define BATT_OVV_VALUE 4750
/* VBUS OVV constants */
#define VBUS_OVV_SELECT_MASK 0x78
#define VBUS_OVV_SELECT_5P6V 0x00
#define VBUS_OVV_SELECT_5P7V 0x08
#define VBUS_OVV_SELECT_5P8V 0x10
#define VBUS_OVV_SELECT_5P9V 0x18
#define VBUS_OVV_SELECT_6P0V 0x20
#define VBUS_OVV_SELECT_6P1V 0x28
#define VBUS_OVV_SELECT_6P2V 0x30
#define VBUS_OVV_SELECT_6P3V 0x38
#define VBUS_AUTO_IN_CURR_LIM_ENA 0x04
/* Fuel Gauge constants */
#define RESET_ACCU 0x02
#define READ_REQ 0x01
#define CC_DEEP_SLEEP_ENA 0x02
#define CC_PWR_UP_ENA 0x01
#define CC_SAMPLES_40 0x28
#define RD_NCONV_ACCU_REQ 0x01
#define CC_CALIB 0x08
#define CC_INTAVGOFFSET_ENA 0x10
#define CC_MUXOFFSET 0x80
#define CC_INT_CAL_N_AVG_MASK 0x60
#define CC_INT_CAL_SAMPLES_16 0x40
#define CC_INT_CAL_SAMPLES_8 0x20
#define CC_INT_CAL_SAMPLES_4 0x00
/* RTC constants */
#define RTC_BUP_CH_ENA 0x10
/* BatCtrl Current Source Constants */
#define BAT_CTRL_7U_ENA 0x01
#define BAT_CTRL_20U_ENA 0x02
#define BAT_CTRL_18U_ENA 0x01
#define BAT_CTRL_16U_ENA 0x02
#define BAT_CTRL_60U_ENA 0x01
#define BAT_CTRL_120U_ENA 0x02
#define BAT_CTRL_CMP_ENA 0x04
#define FORCE_BAT_CTRL_CMP_HIGH 0x08
#define BAT_CTRL_PULL_UP_ENA 0x10
/* Battery type */
#define BATTERY_UNKNOWN 00
/* Registers for pcut feature in ab8505 and ab9540 */
#define AB8505_RTC_PCUT_CTL_STATUS_REG 0x12
#define AB8505_RTC_PCUT_TIME_REG 0x13
#define AB8505_RTC_PCUT_MAX_TIME_REG 0x14
#define AB8505_RTC_PCUT_FLAG_TIME_REG 0x15
#define AB8505_RTC_PCUT_RESTART_REG 0x16
#define AB8505_RTC_PCUT_DEBOUNCE_REG 0x17
/* USB Power Path constants for ab8540 */
#define BUS_VSYS_VOL_SELECT_MASK 0x06
#define BUS_VSYS_VOL_SELECT_3P6V 0x00
#define BUS_VSYS_VOL_SELECT_3P325V 0x02
#define BUS_VSYS_VOL_SELECT_3P9V 0x04
#define BUS_VSYS_VOL_SELECT_4P3V 0x06
#define BUS_POWER_PATH_MODE_ENA 0x01
#define BUS_PP_PRECHG_CURRENT_MASK 0x0E
#define BUS_POWER_PATH_PRECHG_ENA 0x01
/**
* struct res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct res_to_temp {
int temp;
int resist;
};
/**
* struct batres_vs_temp - defines one point in a temp vs battery internal
* resistance curve.
* @temp: battery pack temperature in Celcius
* @resist: battery internal reistance in mOhm
*/
struct batres_vs_temp {
int temp;
int resist;
};
/* Forward declaration */
struct ab8500_fg;
/**
* struct ab8500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
* @pcut_enable: Enable power cut feature in ab8505
* @pcut_max_time: Max time threshold
* @pcut_flag_time: Flagtime threshold
* @pcut_max_restart: Max number of restarts
* @pcut_debunce_time: Sets battery debounce time
*/
struct ab8500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
bool pcut_enable;
u8 pcut_max_time;
u8 pcut_flag_time;
u8 pcut_max_restart;
u8 pcut_debunce_time;
};
/**
* struct ab8500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct ab8500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct ab8500_bm_capacity_levels - ab8500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct ab8500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct ab8500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct ab8500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct ab8500_bm_data - ab8500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @capacity_scaling indicates whether capacity scaling is to be used
* @adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct ab8500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool no_maintenance;
bool capacity_scaling;
bool chg_unknown_bat;
bool enable_overshoot;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
const struct ab8500_maxim_parameters *maxi;
const struct ab8500_bm_capacity_levels *cap_levels;
const struct ab8500_bm_charger_parameters *chg_params;
const struct ab8500_fg_parameters *fg_params;
};
struct ab8500_btemp;
struct ab8500_gpadc;
struct ab8500_fg;
#ifdef CONFIG_AB8500_BM
extern struct abx500_bm_data ab8500_bm_data;
void ab8500_fg_reinit(void);
void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
struct ab8500_btemp *ab8500_btemp_get(void);
int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
int ab8500_btemp_get_temp(struct ab8500_btemp *btemp);
struct ab8500_fg *ab8500_fg_get(void);
int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res);
int ab8500_fg_inst_curr_started(struct ab8500_fg *di);
int ab8500_fg_inst_curr_done(struct ab8500_fg *di);
#else
static struct abx500_bm_data ab8500_bm_data;
#endif
#endif /* _AB8500_BM_H */

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include/linux/mfd/abx500/ab8500-codec.h Normal file
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/*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Ola Lilja <ola.o.lilja@stericsson.com>
* for ST-Ericsson.
*
* License terms:
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef AB8500_CORE_CODEC_H
#define AB8500_CORE_CODEC_H
/* Mic-types */
enum amic_type {
AMIC_TYPE_SINGLE_ENDED,
AMIC_TYPE_DIFFERENTIAL
};
/* Mic-biases */
enum amic_micbias {
AMIC_MICBIAS_VAMIC1,
AMIC_MICBIAS_VAMIC2,
AMIC_MICBIAS_UNKNOWN
};
/* Bias-voltage */
enum ear_cm_voltage {
EAR_CMV_0_95V,
EAR_CMV_1_10V,
EAR_CMV_1_27V,
EAR_CMV_1_58V,
EAR_CMV_UNKNOWN
};
/* Analog microphone settings */
struct amic_settings {
enum amic_type mic1_type;
enum amic_type mic2_type;
enum amic_micbias mic1a_micbias;
enum amic_micbias mic1b_micbias;
enum amic_micbias mic2_micbias;
};
/* Platform data structure for the audio-parts of the AB8500 */
struct ab8500_codec_platform_data {
struct amic_settings amics;
enum ear_cm_voltage ear_cmv;
};
#endif

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include/linux/mfd/abx500/ab8500-gpadc.h Normal file
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/*
* Copyright (C) 2010 ST-Ericsson SA
* Licensed under GPLv2.
*
* Author: Arun R Murthy <arun.murthy@stericsson.com>
* Author: Daniel Willerud <daniel.willerud@stericsson.com>
* Author: M'boumba Cedric Madianga <cedric.madianga@stericsson.com>
*/
#ifndef _AB8500_GPADC_H
#define _AB8500_GPADC_H
/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2
* and ADCHwSel[4:0] in GPADCCtrl3 ) */
#define BAT_CTRL 0x01
#define BTEMP_BALL 0x02
#define MAIN_CHARGER_V 0x03
#define ACC_DETECT1 0x04
#define ACC_DETECT2 0x05
#define ADC_AUX1 0x06
#define ADC_AUX2 0x07
#define MAIN_BAT_V 0x08
#define VBUS_V 0x09
#define MAIN_CHARGER_C 0x0A
#define USB_CHARGER_C 0x0B
#define BK_BAT_V 0x0C
#define DIE_TEMP 0x0D
#define USB_ID 0x0E
#define XTAL_TEMP 0x12
#define VBAT_TRUE_MEAS 0x13
#define BAT_CTRL_AND_IBAT 0x1C
#define VBAT_MEAS_AND_IBAT 0x1D
#define VBAT_TRUE_MEAS_AND_IBAT 0x1E
#define BAT_TEMP_AND_IBAT 0x1F
/* Virtual channel used only for ibat convertion to ampere
* Battery current conversion (ibat) cannot be requested as a single conversion
* but it is always in combination with other input requests
*/
#define IBAT_VIRTUAL_CHANNEL 0xFF
#define SAMPLE_1 1
#define SAMPLE_4 4
#define SAMPLE_8 8
#define SAMPLE_16 16
#define RISING_EDGE 0
#define FALLING_EDGE 1
/* Arbitrary ADC conversion type constants */
#define ADC_SW 0
#define ADC_HW 1
struct ab8500_gpadc;
struct ab8500_gpadc *ab8500_gpadc_get(char *name);
int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
static inline int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel)
{
return ab8500_gpadc_sw_hw_convert(gpadc, channel,
SAMPLE_16, 0, 0, ADC_SW);
}
int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type,
int *ibat);
int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
u8 channel, int ad_value);
void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h,
u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h);
#endif /* _AB8500_GPADC_H */

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/*
* Copyright ST-Ericsson 2010.
*
* Author: Bibek Basu <bibek.basu@stericsson.com>
* Licensed under GPLv2.
*/
#ifndef _AB8500_GPIO_H
#define _AB8500_GPIO_H
/*
* Platform data to register a block: only the initial gpio/irq number.
* Array sizes are large enough to contain all AB8500 and AB9540 GPIO
* registers.
*/
struct abx500_gpio_platform_data {
int gpio_base;
};
enum abx500_gpio_pull_updown {
ABX500_GPIO_PULL_DOWN = 0x0,
ABX500_GPIO_PULL_NONE = 0x1,
ABX500_GPIO_PULL_UP = 0x3,
};
enum abx500_gpio_vinsel {
ABX500_GPIO_VINSEL_VBAT = 0x0,
ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
};
#endif /* _AB8500_GPIO_H */

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include/linux/mfd/abx500/ab8500-sysctrl.h Normal file
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/*
* Copyright (C) ST-Ericsson SA 2010
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __AB8500_SYSCTRL_H
#define __AB8500_SYSCTRL_H
#include <linux/bitops.h>
#ifdef CONFIG_AB8500_CORE
int ab8500_sysctrl_read(u16 reg, u8 *value);
int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
void ab8500_restart(char mode, const char *cmd);
#else
static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
{
return 0;
}
static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
{
return 0;
}
#endif /* CONFIG_AB8500_CORE */
static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, bits);
}
static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, 0);
}
/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
struct ab8500_sysctrl_platform_data {
u8 initial_req_buf_config[8];
u16 (*reboot_reason_code)(const char *cmd);
};
/* Registers */
#define AB8500_TURNONSTATUS 0x100
#define AB8500_RESETSTATUS 0x101
#define AB8500_PONKEY1PRESSSTATUS 0x102
#define AB8500_SYSCLKREQSTATUS 0x142
#define AB8500_STW4500CTRL1 0x180
#define AB8500_STW4500CTRL2 0x181
#define AB8500_STW4500CTRL3 0x200
#define AB8500_MAINWDOGCTRL 0x201
#define AB8500_MAINWDOGTIMER 0x202
#define AB8500_LOWBAT 0x203
#define AB8500_BATTOK 0x204
#define AB8500_SYSCLKTIMER 0x205
#define AB8500_SMPSCLKCTRL 0x206
#define AB8500_SMPSCLKSEL1 0x207
#define AB8500_SMPSCLKSEL2 0x208
#define AB8500_SMPSCLKSEL3 0x209
#define AB8500_SYSULPCLKCONF 0x20A
#define AB8500_SYSULPCLKCTRL1 0x20B
#define AB8500_SYSCLKCTRL 0x20C
#define AB8500_SYSCLKREQ1VALID 0x20D
#define AB8500_SYSTEMCTRLSUP 0x20F
#define AB8500_SYSCLKREQ1RFCLKBUF 0x210
#define AB8500_SYSCLKREQ2RFCLKBUF 0x211
#define AB8500_SYSCLKREQ3RFCLKBUF 0x212
#define AB8500_SYSCLKREQ4RFCLKBUF 0x213
#define AB8500_SYSCLKREQ5RFCLKBUF 0x214
#define AB8500_SYSCLKREQ6RFCLKBUF 0x215
#define AB8500_SYSCLKREQ7RFCLKBUF 0x216
#define AB8500_SYSCLKREQ8RFCLKBUF 0x217
#define AB8500_DITHERCLKCTRL 0x220
#define AB8500_SWATCTRL 0x230
#define AB8500_HIQCLKCTRL 0x232
#define AB8500_VSIMSYSCLKCTRL 0x233
#define AB9540_SYSCLK12BUFCTRL 0x234
#define AB9540_SYSCLK12CONFCTRL 0x235
#define AB9540_SYSCLK12BUFCTRL2 0x236
#define AB9540_SYSCLK12BUF1VALID 0x237
#define AB9540_SYSCLK12BUF2VALID 0x238
#define AB9540_SYSCLK12BUF3VALID 0x239
#define AB9540_SYSCLK12BUF4VALID 0x23A
/* Bits */
#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
#define AB8500_STW4500CTRL1_SWOFF BIT(0)
#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
#define AB8500_STW4500CTRL3_THSDENA BIT(3)
#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
#define AB8500_LOWBAT_LOWBATENA BIT(0)
#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
#define AB8500_LOWBAT_LOWBAT_SHIFT 1
#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
#define AB8500_SWATCTRL_UPDATERF BIT(0)
#define AB8500_SWATCTRL_SWATENABLE BIT(1)
#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
#define AB8500_ENABLE_WD 0x1
#define AB8500_KICK_WD 0x2
#define AB8500_WD_RESTART_ON_EXPIRE 0x10
#endif /* __AB8500_SYSCTRL_H */

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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
*/
#ifndef MFD_AB8500_H
#define MFD_AB8500_H
#include <linux/atomic.h>
#include <linux/mutex.h>
#include <linux/irqdomain.h>
struct device;
/*
* AB IC versions
*
* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
* print of version string.
*/
enum ab8500_version {
AB8500_VERSION_AB8500 = 0x0,
AB8500_VERSION_AB8505 = 0x1,
AB8500_VERSION_AB9540 = 0x2,
AB8500_VERSION_AB8540 = 0x4,
AB8500_VERSION_UNDEFINED,
};
/* AB8500 CIDs*/
#define AB8500_CUTEARLY 0x00
#define AB8500_CUT1P0 0x10
#define AB8500_CUT1P1 0x11
#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */
#define AB8500_CUT2P0 0x20
#define AB8500_CUT3P0 0x30
#define AB8500_CUT3P3 0x33
/*
* AB8500 bank addresses
*/
#define AB8500_M_FSM_RANK 0x0
#define AB8500_SYS_CTRL1_BLOCK 0x1
#define AB8500_SYS_CTRL2_BLOCK 0x2
#define AB8500_REGU_CTRL1 0x3
#define AB8500_REGU_CTRL2 0x4
#define AB8500_USB 0x5
#define AB8500_TVOUT 0x6
#define AB8500_DBI 0x7
#define AB8500_ECI_AV_ACC 0x8
#define AB8500_RESERVED 0x9
#define AB8500_GPADC 0xA
#define AB8500_CHARGER 0xB
#define AB8500_GAS_GAUGE 0xC
#define AB8500_AUDIO 0xD
#define AB8500_INTERRUPT 0xE
#define AB8500_RTC 0xF
#define AB8500_MISC 0x10
#define AB8500_DEVELOPMENT 0x11
#define AB8500_DEBUG 0x12
#define AB8500_PROD_TEST 0x13
#define AB8500_STE_TEST 0x14
#define AB8500_OTP_EMUL 0x15
/*
* Interrupts
* Values used to index into array ab8500_irq_regoffset[] defined in
* drivers/mdf/ab8500-core.c
*/
/* Definitions for AB8500, AB9540 and AB8540 */
/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */
#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */
#define AB8500_INT_TEMP_WARM 3
#define AB8500_INT_PON_KEY2DB_F 4
#define AB8500_INT_PON_KEY2DB_R 5
#define AB8500_INT_PON_KEY1DB_F 6
#define AB8500_INT_PON_KEY1DB_R 7
/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
#define AB8500_INT_BATT_OVV 8
#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */
#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */
#define AB8500_INT_VBUS_DET_F 14
#define AB8500_INT_VBUS_DET_R 15
/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
#define AB8500_INT_VBUS_CH_DROP_END 16
#define AB8500_INT_RTC_60S 17
#define AB8500_INT_RTC_ALARM 18
#define AB8540_INT_BIF_INT 19
#define AB8500_INT_BAT_CTRL_INDB 20
#define AB8500_INT_CH_WD_EXP 21
#define AB8500_INT_VBUS_OVV 22
#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */
/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
#define AB8500_INT_CCN_CONV_ACC 24
#define AB8500_INT_INT_AUD 25
#define AB8500_INT_CCEOC 26
#define AB8500_INT_CC_INT_CALIB 27
#define AB8500_INT_LOW_BAT_F 28
#define AB8500_INT_LOW_BAT_R 29
#define AB8500_INT_BUP_CHG_NOT_OK 30
#define AB8500_INT_BUP_CHG_OK 31
/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */
#define AB8500_INT_ACC_DETECT_1DB_F 33
#define AB8500_INT_ACC_DETECT_1DB_R 34
#define AB8500_INT_ACC_DETECT_22DB_F 35
#define AB8500_INT_ACC_DETECT_22DB_R 36
#define AB8500_INT_ACC_DETECT_21DB_F 37
#define AB8500_INT_ACC_DETECT_21DB_R 38
#define AB8500_INT_GP_SW_ADC_CONV_END 39
/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO10R 44 /* not 8540 */
#define AB8500_INT_GPIO11R 45 /* not 8540 */
#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */
#define AB8500_INT_GPIO13R 47 /* not 8540 */
/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */
#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */
#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40R 54 /* not 8540 */
#define AB8500_INT_GPIO41R 55 /* not 8540 */
/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
#define AB8500_INT_GPIO10F 60
#define AB8500_INT_GPIO11F 61
#define AB8500_INT_GPIO12F 62 /* not 8505 */
#define AB8500_INT_GPIO13F 63
/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */
#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */
#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40F 70 /* not 8540 */
#define AB8500_INT_GPIO41F 71 /* not 8540 */
/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
#define AB8500_INT_ADP_SOURCE_ERROR 72
#define AB8500_INT_ADP_SINK_ERROR 73
#define AB8500_INT_ADP_PROBE_PLUG 74
#define AB8500_INT_ADP_PROBE_UNPLUG 75
#define AB8500_INT_ADP_SENSE_OFF 76
#define AB8500_INT_USB_PHY_POWER_ERR 78
#define AB8500_INT_USB_LINK_STATUS 79
/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
#define AB8500_INT_BTEMP_LOW 80
#define AB8500_INT_BTEMP_LOW_MEDIUM 81
#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
#define AB8500_INT_BTEMP_HIGH 83
/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
#define AB8500_INT_SRP_DETECT 88
#define AB8500_INT_USB_CHARGER_NOT_OKR 89
#define AB8500_INT_ID_WAKEUP_R 90
#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1R 92
#define AB8500_INT_ID_DET_R2R 93
#define AB8500_INT_ID_DET_R3R 94
#define AB8500_INT_ID_DET_R4R 95
/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */
#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */
#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */
#define AB8500_INT_CHSTOPBYSEC 103
/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
#define AB8500_INT_USB_CH_TH_PROT_F 104
#define AB8500_INT_USB_CH_TH_PROT_R 105
#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
#define AB8500_INT_CHCURLIMNOHSCHIRP 109
#define AB8500_INT_CHCURLIMHSCHIRP 110
#define AB8500_INT_XTAL32K_KO 111
/* Definitions for AB9540 / AB8505 */
/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
#define AB9540_INT_GPIO50R 113 /* not 8540 */
#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */
#define AB9540_INT_GPIO52R 115 /* not 8540 */
#define AB9540_INT_GPIO53R 116 /* not 8540 */
#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_R 118
/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
#define AB9540_INT_GPIO50F 121 /* not 8540 */
#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */
#define AB9540_INT_GPIO52F 123 /* not 8540 */
#define AB9540_INT_GPIO53F 124 /* not 8540 */
#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_F 126
/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
#define AB8505_INT_KEYSTUCK 128
#define AB8505_INT_IKR 129
#define AB8505_INT_IKP 130
#define AB8505_INT_KP 131
#define AB8505_INT_KEYDEGLITCH 132
#define AB8505_INT_MODPWRSTATUSF 134
#define AB8505_INT_MODPWRSTATUSR 135
/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
#define AB8500_INT_HOOK_DET_NEG_F 138
#define AB8500_INT_HOOK_DET_NEG_R 139
#define AB8500_INT_HOOK_DET_POS_F 140
#define AB8500_INT_HOOK_DET_POS_R 141
#define AB8500_INT_PLUG_DET_COMP_F 142
#define AB8500_INT_PLUG_DET_COMP_R 143
/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
#define AB8505_INT_COLL 144
#define AB8505_INT_RESERR 145
#define AB8505_INT_FRAERR 146
#define AB8505_INT_COMERR 147
#define AB8505_INT_SPDSET 148
#define AB8505_INT_DSENT 149
#define AB8505_INT_DREC 150
#define AB8505_INT_ACC_INT 151
/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
#define AB8505_INT_NOPINT 152
/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
#define AB8540_INT_IDPLUGDETCOMPF 160
#define AB8540_INT_IDPLUGDETCOMPR 161
#define AB8540_INT_FMDETCOMPLOF 162
#define AB8540_INT_FMDETCOMPLOR 163
#define AB8540_INT_FMDETCOMPHIF 164
#define AB8540_INT_FMDETCOMPHIR 165
#define AB8540_INT_ID5VDETCOMPF 166
#define AB8540_INT_ID5VDETCOMPR 167
/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
#define AB8540_INT_GPIO43F 168
#define AB8540_INT_GPIO43R 169
#define AB8540_INT_GPIO44F 170
#define AB8540_INT_GPIO44R 171
#define AB8540_INT_KEYPOSDETCOMPF 172
#define AB8540_INT_KEYPOSDETCOMPR 173
#define AB8540_INT_KEYNEGDETCOMPF 174
#define AB8540_INT_KEYNEGDETCOMPR 175
/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
#define AB8540_INT_GPIO1VBATF 176
#define AB8540_INT_GPIO1VBATR 177
#define AB8540_INT_GPIO2VBATF 178
#define AB8540_INT_GPIO2VBATR 179
#define AB8540_INT_GPIO3VBATF 180
#define AB8540_INT_GPIO3VBATR 181
#define AB8540_INT_GPIO4VBATF 182
#define AB8540_INT_GPIO4VBATR 183
/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
#define AB8540_INT_SYSCLKREQ2F 184
#define AB8540_INT_SYSCLKREQ2R 185
#define AB8540_INT_SYSCLKREQ3F 186
#define AB8540_INT_SYSCLKREQ3R 187
#define AB8540_INT_SYSCLKREQ4F 188
#define AB8540_INT_SYSCLKREQ4R 189
#define AB8540_INT_SYSCLKREQ5F 190
#define AB8540_INT_SYSCLKREQ5R 191
/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
#define AB8540_INT_PWMOUT1F 192
#define AB8540_INT_PWMOUT1R 193
#define AB8540_INT_PWMCTRL0F 194
#define AB8540_INT_PWMCTRL0R 195
#define AB8540_INT_PWMCTRL1F 196
#define AB8540_INT_PWMCTRL1R 197
#define AB8540_INT_SYSCLKREQ6F 198
#define AB8540_INT_SYSCLKREQ6R 199
/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
#define AB8540_INT_PWMEXTVIBRA1F 200
#define AB8540_INT_PWMEXTVIBRA1R 201
#define AB8540_INT_PWMEXTVIBRA2F 202
#define AB8540_INT_PWMEXTVIBRA2R 203
#define AB8540_INT_PWMOUT2F 204
#define AB8540_INT_PWMOUT2R 205
#define AB8540_INT_PWMOUT3F 206
#define AB8540_INT_PWMOUT3R 207
/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
#define AB8540_INT_ADDATA2F 208
#define AB8540_INT_ADDATA2R 209
#define AB8540_INT_DADATA2F 210
#define AB8540_INT_DADATA2R 211
#define AB8540_INT_FSYNC2F 212
#define AB8540_INT_FSYNC2R 213
#define AB8540_INT_BITCLK2F 214
#define AB8540_INT_BITCLK2R 215
/*
* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
* entire platform. This is a "compile time" constant so this must be set to
* the largest possible value that may be encountered with different AB SOCs.
* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
* which is larger.
*/
#define AB8500_NR_IRQS 112
#define AB8505_NR_IRQS 153
#define AB9540_NR_IRQS 153
#define AB8540_NR_IRQS 216
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS
#define AB8500_NUM_IRQ_REGS 14
#define AB9540_NUM_IRQ_REGS 20
#define AB8540_NUM_IRQ_REGS 27
/* Turn On Status Event */
#define AB8500_POR_ON_VBAT 0x01
#define AB8500_POW_KEY_1_ON 0x02
#define AB8500_POW_KEY_2_ON 0x04
#define AB8500_RTC_ALARM 0x08
#define AB8500_MAIN_CH_DET 0x10
#define AB8500_VBUS_DET 0x20
#define AB8500_USB_ID_DET 0x40
/**
* struct ab8500 - ab8500 internal structure
* @dev: parent device
* @lock: read/write operations lock
* @irq_lock: genirq bus lock
* @transfer_ongoing: 0 if no transfer ongoing
* @irq: irq line
* @irq_domain: irq domain
* @version: chip version id (e.g. ab8500 or ab9540)
* @chip_id: chip revision id
* @write: register write
* @write_masked: masked register write
* @read: register read
* @rx_buf: rx buf for SPI
* @tx_buf: tx buf for SPI
* @mask: cache of IRQ regs for bus lock
* @oldmask: cache of previous IRQ regs for bus lock
* @mask_size: Actual number of valid entries in mask[], oldmask[] and
* irq_reg_offset
* @irq_reg_offset: Array of offsets into IRQ registers
*/
struct ab8500 {
struct device *dev;
struct mutex lock;
struct mutex irq_lock;
atomic_t transfer_ongoing;
int irq_base;
int irq;
struct irq_domain *domain;
enum ab8500_version version;
u8 chip_id;
int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
int (*read)(struct ab8500 *ab8500, u16 addr);
unsigned long tx_buf[4];
unsigned long rx_buf[4];
u8 *mask;
u8 *oldmask;
int mask_size;
const int *irq_reg_offset;
int it_latchhier_num;
};
struct ab8500_regulator_platform_data;
struct ab8500_gpio_platform_data;
struct ab8500_codec_platform_data;
struct ab8500_sysctrl_platform_data;
/**
* struct ab8500_platform_data - AB8500 platform data
* @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
* @init: board-specific initialization after detection of ab8500
* @regulator: machine-specific constraints for regulators
*/
struct ab8500_platform_data {
int irq_base;
void (*init) (struct ab8500 *);
struct ab8500_regulator_platform_data *regulator;
struct abx500_gpio_platform_data *gpio;
struct ab8500_codec_platform_data *codec;
struct ab8500_sysctrl_platform_data *sysctrl;
};
extern int ab8500_init(struct ab8500 *ab8500,
enum ab8500_version version);
extern int ab8500_exit(struct ab8500 *ab8500);
extern int ab8500_suspend(struct ab8500 *ab8500);
static inline int is_ab8500(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8500;
}
static inline int is_ab8505(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8505;
}
static inline int is_ab9540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB9540;
}
static inline int is_ab8540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8540;
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
}
static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}
static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
static inline int is_ab8505_2p0(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
}
static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
static inline int is_ab9540_2p0(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
}
/*
* Be careful, the marketing name for this chip is 2.1
* but the value read from the chip is 3.0 (0x30)
*/
static inline int is_ab9540_3p0(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
}
static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
}
static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
}
static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
}
static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
}
static inline int is_ab8540_2p0(struct ab8500 *ab)
{
return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
}
static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
{
return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
}
static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
}
void ab8500_override_turn_on_stat(u8 mask, u8 set);
#ifdef CONFIG_AB8500_DEBUG
void ab8500_dump_all_banks(struct device *dev);
void ab8500_debug_register_interrupt(int line);
#else
static inline void ab8500_dump_all_banks(struct device *dev) {}
static inline void ab8500_debug_register_interrupt(int line) {}
#endif
#endif /* MFD_AB8500_H */

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/*
* Copyright (C) ST-Ericsson SA 2012
* Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _UX500_CHARGALG_H
#define _UX500_CHARGALG_H
#include <linux/power_supply.h>
#define psy_to_ux500_charger(x) container_of((x), \
struct ux500_charger, psy)
/* Forward declaration */
struct ux500_charger;
struct ux500_charger_ops {
int (*enable) (struct ux500_charger *, int, int, int);
int (*check_enable) (struct ux500_charger *, int, int);
int (*kick_wd) (struct ux500_charger *);
int (*update_curr) (struct ux500_charger *, int);
int (*pp_enable) (struct ux500_charger *, bool);
int (*pre_chg_enable) (struct ux500_charger *, bool);
};
/**
* struct ux500_charger - power supply ux500 charger sub class
* @psy power supply base class
* @ops ux500 charger operations
* @max_out_volt maximum output charger voltage in mV
* @max_out_curr maximum output charger current in mA
* @enabled indicates if this charger is used or not
* @external external charger unit (pm2xxx)
* @power_path USB power path support
*/
struct ux500_charger {
struct power_supply psy;
struct ux500_charger_ops ops;
int max_out_volt;
int max_out_curr;
int wdt_refresh;
bool enabled;
bool external;
bool power_path;
};
extern struct blocking_notifier_head charger_notifier_list;
#endif

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/*
* Definitions and platform data for Analog Devices
* ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
*
* Copyright 2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __LINUX_MFD_ADP5520_H
#define __LINUX_MFD_ADP5520_H
#define ID_ADP5520 5520
#define ID_ADP5501 5501
/*
* ADP5520/ADP5501 Register Map
*/
#define ADP5520_MODE_STATUS 0x00
#define ADP5520_INTERRUPT_ENABLE 0x01
#define ADP5520_BL_CONTROL 0x02
#define ADP5520_BL_TIME 0x03
#define ADP5520_BL_FADE 0x04
#define ADP5520_DAYLIGHT_MAX 0x05
#define ADP5520_DAYLIGHT_DIM 0x06
#define ADP5520_OFFICE_MAX 0x07
#define ADP5520_OFFICE_DIM 0x08
#define ADP5520_DARK_MAX 0x09
#define ADP5520_DARK_DIM 0x0A
#define ADP5520_BL_VALUE 0x0B
#define ADP5520_ALS_CMPR_CFG 0x0C
#define ADP5520_L2_TRIP 0x0D
#define ADP5520_L2_HYS 0x0E
#define ADP5520_L3_TRIP 0x0F
#define ADP5520_L3_HYS 0x10
#define ADP5520_LED_CONTROL 0x11
#define ADP5520_LED_TIME 0x12
#define ADP5520_LED_FADE 0x13
#define ADP5520_LED1_CURRENT 0x14
#define ADP5520_LED2_CURRENT 0x15
#define ADP5520_LED3_CURRENT 0x16
/*
* ADP5520 Register Map
*/
#define ADP5520_GPIO_CFG_1 0x17
#define ADP5520_GPIO_CFG_2 0x18
#define ADP5520_GPIO_IN 0x19
#define ADP5520_GPIO_OUT 0x1A
#define ADP5520_GPIO_INT_EN 0x1B
#define ADP5520_GPIO_INT_STAT 0x1C
#define ADP5520_GPIO_INT_LVL 0x1D
#define ADP5520_GPIO_DEBOUNCE 0x1E
#define ADP5520_GPIO_PULLUP 0x1F
#define ADP5520_KP_INT_STAT_1 0x20
#define ADP5520_KP_INT_STAT_2 0x21
#define ADP5520_KR_INT_STAT_1 0x22
#define ADP5520_KR_INT_STAT_2 0x23
#define ADP5520_KEY_STAT_1 0x24
#define ADP5520_KEY_STAT_2 0x25
/*
* MODE_STATUS bits
*/
#define ADP5520_nSTNBY (1 << 7)
#define ADP5520_BL_EN (1 << 6)
#define ADP5520_DIM_EN (1 << 5)
#define ADP5520_OVP_INT (1 << 4)
#define ADP5520_CMPR_INT (1 << 3)
#define ADP5520_GPI_INT (1 << 2)
#define ADP5520_KR_INT (1 << 1)
#define ADP5520_KP_INT (1 << 0)
/*
* INTERRUPT_ENABLE bits
*/
#define ADP5520_AUTO_LD_EN (1 << 4)
#define ADP5520_CMPR_IEN (1 << 3)
#define ADP5520_OVP_IEN (1 << 2)
#define ADP5520_KR_IEN (1 << 1)
#define ADP5520_KP_IEN (1 << 0)
/*
* BL_CONTROL bits
*/
#define ADP5520_BL_LVL ((x) << 5)
#define ADP5520_BL_LAW ((x) << 4)
#define ADP5520_BL_AUTO_ADJ (1 << 3)
#define ADP5520_OVP_EN (1 << 2)
#define ADP5520_FOVR (1 << 1)
#define ADP5520_KP_BL_EN (1 << 0)
/*
* ALS_CMPR_CFG bits
*/
#define ADP5520_L3_OUT (1 << 3)
#define ADP5520_L2_OUT (1 << 2)
#define ADP5520_L3_EN (1 << 1)
#define ADP5020_MAX_BRIGHTNESS 0x7F
#define FADE_VAL(in, out) ((0xF & (in)) | ((0xF & (out)) << 4))
#define BL_CTRL_VAL(law, auto) (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
#define ALS_CMPR_CFG_VAL(filt, l3_en) (((0x7 & filt) << 5) | l3_en)
/*
* LEDs subdevice bits and masks
*/
#define ADP5520_01_MAXLEDS 3
#define ADP5520_FLAG_LED_MASK 0x3
#define ADP5520_FLAG_OFFT_SHIFT 8
#define ADP5520_FLAG_OFFT_MASK 0x3
#define ADP5520_R3_MODE (1 << 5)
#define ADP5520_C3_MODE (1 << 4)
#define ADP5520_LED_LAW (1 << 3)
#define ADP5520_LED3_EN (1 << 2)
#define ADP5520_LED2_EN (1 << 1)
#define ADP5520_LED1_EN (1 << 0)
/*
* GPIO subdevice bits and masks
*/
#define ADP5520_MAXGPIOS 8
#define ADP5520_GPIO_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_GPIO_C2 (1 << 6)
#define ADP5520_GPIO_C1 (1 << 5)
#define ADP5520_GPIO_C0 (1 << 4)
#define ADP5520_GPIO_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_GPIO_R2 (1 << 2)
#define ADP5520_GPIO_R1 (1 << 1)
#define ADP5520_GPIO_R0 (1 << 0)
struct adp5520_gpio_platform_data {
unsigned gpio_start;
u8 gpio_en_mask;
u8 gpio_pullup_mask;
};
/*
* Keypad subdevice bits and masks
*/
#define ADP5520_MAXKEYS 16
#define ADP5520_COL_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_COL_C2 (1 << 6)
#define ADP5520_COL_C1 (1 << 5)
#define ADP5520_COL_C0 (1 << 4)
#define ADP5520_ROW_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_ROW_R2 (1 << 2)
#define ADP5520_ROW_R1 (1 << 1)
#define ADP5520_ROW_R0 (1 << 0)
#define ADP5520_KEY(row, col) (col + row * 4)
#define ADP5520_KEYMAPSIZE ADP5520_MAXKEYS
struct adp5520_keys_platform_data {
int rows_en_mask; /* Number of rows */
int cols_en_mask; /* Number of columns */
const unsigned short *keymap; /* Pointer to keymap */
unsigned short keymapsize; /* Keymap size */
unsigned repeat:1; /* Enable key repeat */
};
/*
* LEDs subdevice platform data
*/
#define FLAG_ID_ADP5520_LED1_ADP5501_LED0 1 /* ADP5520 PIN ILED */
#define FLAG_ID_ADP5520_LED2_ADP5501_LED1 2 /* ADP5520 PIN C3 */
#define FLAG_ID_ADP5520_LED3_ADP5501_LED2 3 /* ADP5520 PIN R3 */
#define ADP5520_LED_DIS_BLINK (0 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_600ms (1 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_800ms (2 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_ONT_200ms 0
#define ADP5520_LED_ONT_600ms 1
#define ADP5520_LED_ONT_800ms 2
#define ADP5520_LED_ONT_1200ms 3
struct adp5520_leds_platform_data {
int num_leds;
struct led_info *leds;
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 led_on_time;
};
/*
* Backlight subdevice platform data
*/
#define ADP5520_FADE_T_DIS 0 /* Fade Timer Disabled */
#define ADP5520_FADE_T_300ms 1 /* 0.3 Sec */
#define ADP5520_FADE_T_600ms 2
#define ADP5520_FADE_T_900ms 3
#define ADP5520_FADE_T_1200ms 4
#define ADP5520_FADE_T_1500ms 5
#define ADP5520_FADE_T_1800ms 6
#define ADP5520_FADE_T_2100ms 7
#define ADP5520_FADE_T_2400ms 8
#define ADP5520_FADE_T_2700ms 9
#define ADP5520_FADE_T_3000ms 10
#define ADP5520_FADE_T_3500ms 11
#define ADP5520_FADE_T_4000ms 12
#define ADP5520_FADE_T_4500ms 13
#define ADP5520_FADE_T_5000ms 14
#define ADP5520_FADE_T_5500ms 15 /* 5.5 Sec */
#define ADP5520_BL_LAW_LINEAR 0
#define ADP5520_BL_LAW_SQUARE 1
#define ADP5520_BL_LAW_CUBIC1 2
#define ADP5520_BL_LAW_CUBIC2 3
#define ADP5520_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
#define ADP5520_BL_AMBL_FILT_160ms 1
#define ADP5520_BL_AMBL_FILT_320ms 2
#define ADP5520_BL_AMBL_FILT_640ms 3
#define ADP5520_BL_AMBL_FILT_1280ms 4
#define ADP5520_BL_AMBL_FILT_2560ms 5
#define ADP5520_BL_AMBL_FILT_5120ms 6
#define ADP5520_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
/*
* Blacklight current 0..30mA
*/
#define ADP5520_BL_CUR_mA(I) ((I * 127) / 30)
/*
* L2 comparator current 0..1000uA
*/
#define ADP5520_L2_COMP_CURR_uA(I) ((I * 255) / 1000)
/*
* L3 comparator current 0..127uA
*/
#define ADP5520_L3_COMP_CURR_uA(I) ((I * 255) / 127)
struct adp5520_backlight_platform_data {
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 fade_led_law; /* fade-on/fade-off transfer characteristic */
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
u8 abml_filt; /* Light sensor filter time */
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
};
/*
* MFD chip platform data
*/
struct adp5520_platform_data {
struct adp5520_keys_platform_data *keys;
struct adp5520_gpio_platform_data *gpio;
struct adp5520_leds_platform_data *leds;
struct adp5520_backlight_platform_data *backlight;
};
/*
* MFD chip functions
*/
extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
extern int adp5520_write(struct device *dev, int reg, u8 val);
extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int adp5520_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
#endif /* __LINUX_MFD_ADP5520_H */

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/*
* Arizona MFD internals
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM_ARIZONA_CORE_H
#define _WM_ARIZONA_CORE_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/arizona/pdata.h>
#define ARIZONA_MAX_CORE_SUPPLIES 3
enum arizona_type {
WM5102 = 1,
WM5110 = 2,
};
#define ARIZONA_IRQ_GP1 0
#define ARIZONA_IRQ_GP2 1
#define ARIZONA_IRQ_GP3 2
#define ARIZONA_IRQ_GP4 3
#define ARIZONA_IRQ_GP5_FALL 4
#define ARIZONA_IRQ_GP5_RISE 5
#define ARIZONA_IRQ_JD_FALL 6
#define ARIZONA_IRQ_JD_RISE 7
#define ARIZONA_IRQ_DSP1_RAM_RDY 8
#define ARIZONA_IRQ_DSP2_RAM_RDY 9
#define ARIZONA_IRQ_DSP3_RAM_RDY 10
#define ARIZONA_IRQ_DSP4_RAM_RDY 11
#define ARIZONA_IRQ_DSP_IRQ1 12
#define ARIZONA_IRQ_DSP_IRQ2 13
#define ARIZONA_IRQ_DSP_IRQ3 14
#define ARIZONA_IRQ_DSP_IRQ4 15
#define ARIZONA_IRQ_DSP_IRQ5 16
#define ARIZONA_IRQ_DSP_IRQ6 17
#define ARIZONA_IRQ_DSP_IRQ7 18
#define ARIZONA_IRQ_DSP_IRQ8 19
#define ARIZONA_IRQ_SPK_SHUTDOWN_WARN 20
#define ARIZONA_IRQ_SPK_SHUTDOWN 21
#define ARIZONA_IRQ_MICDET 22
#define ARIZONA_IRQ_HPDET 23
#define ARIZONA_IRQ_WSEQ_DONE 24
#define ARIZONA_IRQ_DRC2_SIG_DET 25
#define ARIZONA_IRQ_DRC1_SIG_DET 26
#define ARIZONA_IRQ_ASRC2_LOCK 27
#define ARIZONA_IRQ_ASRC1_LOCK 28
#define ARIZONA_IRQ_UNDERCLOCKED 29
#define ARIZONA_IRQ_OVERCLOCKED 30
#define ARIZONA_IRQ_FLL2_LOCK 31
#define ARIZONA_IRQ_FLL1_LOCK 32
#define ARIZONA_IRQ_CLKGEN_ERR 33
#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 34
#define ARIZONA_IRQ_ASRC_CFG_ERR 35
#define ARIZONA_IRQ_AIF3_ERR 36
#define ARIZONA_IRQ_AIF2_ERR 37
#define ARIZONA_IRQ_AIF1_ERR 38
#define ARIZONA_IRQ_CTRLIF_ERR 39
#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 40
#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 41
#define ARIZONA_IRQ_SYSCLK_ENA_LOW 42
#define ARIZONA_IRQ_ISRC1_CFG_ERR 43
#define ARIZONA_IRQ_ISRC2_CFG_ERR 44
#define ARIZONA_IRQ_BOOT_DONE 45
#define ARIZONA_IRQ_DCS_DAC_DONE 46
#define ARIZONA_IRQ_DCS_HP_DONE 47
#define ARIZONA_IRQ_FLL2_CLOCK_OK 48
#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
#define ARIZONA_NUM_IRQ 52
struct snd_soc_dapm_context;
struct arizona {
struct regmap *regmap;
struct device *dev;
enum arizona_type type;
unsigned int rev;
int num_core_supplies;
struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
struct regulator *dcvdd;
struct arizona_pdata pdata;
int irq;
struct irq_domain *virq;
struct regmap_irq_chip_data *aod_irq_chip;
struct regmap_irq_chip_data *irq_chip;
bool hpdet_magic;
unsigned int hp_ena;
struct mutex clk_lock;
int clk32k_ref;
struct snd_soc_dapm_context *dapm;
};
int arizona_clk32k_enable(struct arizona *arizona);
int arizona_clk32k_disable(struct arizona *arizona);
int arizona_request_irq(struct arizona *arizona, int irq, char *name,
irq_handler_t handler, void *data);
void arizona_free_irq(struct arizona *arizona, int irq, void *data);
int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
int wm5102_patch(struct arizona *arizona);
int wm5110_patch(struct arizona *arizona);
#endif

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/*
* Platform data for Arizona devices
*
* Copyright 2012 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ARIZONA_PDATA_H
#define _ARIZONA_PDATA_H
#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
#define ARIZONA_MAX_GPIO 5
#define ARIZONA_32KZ_MCLK1 1
#define ARIZONA_32KZ_MCLK2 2
#define ARIZONA_32KZ_NONE 3
#define ARIZONA_MAX_INPUT 4
#define ARIZONA_DMIC_MICVDD 0
#define ARIZONA_DMIC_MICBIAS1 1
#define ARIZONA_DMIC_MICBIAS2 2
#define ARIZONA_DMIC_MICBIAS3 3
#define ARIZONA_MAX_MICBIAS 3
#define ARIZONA_INMODE_DIFF 0
#define ARIZONA_INMODE_SE 1
#define ARIZONA_INMODE_DMIC 2
#define ARIZONA_MAX_OUTPUT 6
#define ARIZONA_MAX_AIF 3
#define ARIZONA_HAP_ACT_ERM 0
#define ARIZONA_HAP_ACT_LRA 2
#define ARIZONA_MAX_PDM_SPK 2
struct regulator_init_data;
struct arizona_micbias {
int mV; /** Regulated voltage */
unsigned int ext_cap:1; /** External capacitor fitted */
unsigned int discharge:1; /** Actively discharge */
unsigned int fast_start:1; /** Enable aggressive startup ramp rate */
unsigned int bypass:1; /** Use bypass mode */
};
struct arizona_micd_config {
unsigned int src;
unsigned int bias;
bool gpio;
};
struct arizona_micd_range {
int max; /** Ohms */
int key; /** Key to report to input layer */
};
struct arizona_pdata {
int reset; /** GPIO controlling /RESET, if any */
int ldoena; /** GPIO controlling LODENA, if any */
/** Regulator configuration for MICVDD */
struct regulator_init_data *micvdd;
/** Regulator configuration for LDO1 */
struct regulator_init_data *ldo1;
/** If a direct 32kHz clock is provided on an MCLK specify it here */
int clk32k_src;
/** Mode for primary IRQ (defaults to active low) */
unsigned int irq_flags;
/* Base GPIO */
int gpio_base;
/** Pin state for GPIO pins */
int gpio_defaults[ARIZONA_MAX_GPIO];
/**
* Maximum number of channels clocks will be generated for,
* useful for systems where and I2S bus with multiple data
* lines is mastered.
*/
int max_channels_clocked[ARIZONA_MAX_AIF];
/** GPIO5 is used for jack detection */
bool jd_gpio5;
/** Internal pull on GPIO5 is disabled when used for jack detection */
bool jd_gpio5_nopull;
/** Use the headphone detect circuit to identify the accessory */
bool hpdet_acc_id;
/** Check for line output with HPDET method */
bool hpdet_acc_id_line;
/** GPIO used for mic isolation with HPDET */
int hpdet_id_gpio;
/** Extra debounce timeout used during initial mic detection (ms) */
int micd_detect_debounce;
/** GPIO for mic detection polarity */
int micd_pol_gpio;
/** Mic detect ramp rate */
int micd_bias_start_time;
/** Mic detect sample rate */
int micd_rate;
/** Mic detect debounce level */
int micd_dbtime;
/** Mic detect timeout (ms) */
int micd_timeout;
/** Force MICBIAS on for mic detect */
bool micd_force_micbias;
/** Mic detect level parameters */
const struct arizona_micd_range *micd_ranges;
int num_micd_ranges;
/** Headset polarity configurations */
struct arizona_micd_config *micd_configs;
int num_micd_configs;
/** Reference voltage for DMIC inputs */
int dmic_ref[ARIZONA_MAX_INPUT];
/** MICBIAS configurations */
struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
/** Mode of input structures */
int inmode[ARIZONA_MAX_INPUT];
/** Mode for outputs */
bool out_mono[ARIZONA_MAX_OUTPUT];
/** PDM speaker mute setting */
unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
/** PDM speaker format */
unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
/** Haptic actuator type */
unsigned int hap_act;
/** GPIO for primary IRQ (used for edge triggered emulation) */
int irq_gpio;
};
#endif

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include/linux/mfd/as3711.h Normal file
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/*
* AS3711 PMIC MFC driver header
*
* Copyright (C) 2012 Renesas Electronics Corporation
* Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the version 2 of the GNU General Public License as
* published by the Free Software Foundation
*/
#ifndef MFD_AS3711_H
#define MFD_AS3711_H
/*
* Client data
*/
/* Register addresses */
#define AS3711_SD_1_VOLTAGE 0 /* Digital Step-Down */
#define AS3711_SD_2_VOLTAGE 1
#define AS3711_SD_3_VOLTAGE 2
#define AS3711_SD_4_VOLTAGE 3
#define AS3711_LDO_1_VOLTAGE 4 /* Analog LDO */
#define AS3711_LDO_2_VOLTAGE 5
#define AS3711_LDO_3_VOLTAGE 6 /* Digital LDO */
#define AS3711_LDO_4_VOLTAGE 7
#define AS3711_LDO_5_VOLTAGE 8
#define AS3711_LDO_6_VOLTAGE 9
#define AS3711_LDO_7_VOLTAGE 0xa
#define AS3711_LDO_8_VOLTAGE 0xb
#define AS3711_SD_CONTROL 0x10
#define AS3711_GPIO_SIGNAL_OUT 0x20
#define AS3711_GPIO_SIGNAL_IN 0x21
#define AS3711_SD_CONTROL_1 0x30
#define AS3711_SD_CONTROL_2 0x31
#define AS3711_CURR_CONTROL 0x40
#define AS3711_CURR1_VALUE 0x43
#define AS3711_CURR2_VALUE 0x44
#define AS3711_CURR3_VALUE 0x45
#define AS3711_STEPUP_CONTROL_1 0x50
#define AS3711_STEPUP_CONTROL_2 0x51
#define AS3711_STEPUP_CONTROL_4 0x53
#define AS3711_STEPUP_CONTROL_5 0x54
#define AS3711_REG_STATUS 0x73
#define AS3711_INTERRUPT_STATUS_1 0x77
#define AS3711_INTERRUPT_STATUS_2 0x78
#define AS3711_INTERRUPT_STATUS_3 0x79
#define AS3711_CHARGER_STATUS_1 0x86
#define AS3711_CHARGER_STATUS_2 0x87
#define AS3711_ASIC_ID_1 0x90
#define AS3711_ASIC_ID_2 0x91
#define AS3711_MAX_REGS 0x92
/* Regulators */
enum {
AS3711_REGULATOR_SD_1,
AS3711_REGULATOR_SD_2,
AS3711_REGULATOR_SD_3,
AS3711_REGULATOR_SD_4,
AS3711_REGULATOR_LDO_1,
AS3711_REGULATOR_LDO_2,
AS3711_REGULATOR_LDO_3,
AS3711_REGULATOR_LDO_4,
AS3711_REGULATOR_LDO_5,
AS3711_REGULATOR_LDO_6,
AS3711_REGULATOR_LDO_7,
AS3711_REGULATOR_LDO_8,
AS3711_REGULATOR_MAX,
};
struct device;
struct regmap;
struct as3711 {
struct device *dev;
struct regmap *regmap;
};
#define AS3711_MAX_STEPDOWN 4
#define AS3711_MAX_STEPUP 2
#define AS3711_MAX_LDO 8
enum as3711_su2_feedback {
AS3711_SU2_VOLTAGE,
AS3711_SU2_CURR1,
AS3711_SU2_CURR2,
AS3711_SU2_CURR3,
AS3711_SU2_CURR_AUTO,
};
enum as3711_su2_fbprot {
AS3711_SU2_LX_SD4,
AS3711_SU2_GPIO2,
AS3711_SU2_GPIO3,
AS3711_SU2_GPIO4,
};
/*
* Platform data
*/
struct as3711_regulator_pdata {
struct regulator_init_data *init_data[AS3711_REGULATOR_MAX];
};
struct as3711_bl_pdata {
const char *su1_fb;
int su1_max_uA;
const char *su2_fb;
int su2_max_uA;
enum as3711_su2_feedback su2_feedback;
enum as3711_su2_fbprot su2_fbprot;
bool su2_auto_curr1;
bool su2_auto_curr2;
bool su2_auto_curr3;
};
struct as3711_platform_data {
struct as3711_regulator_pdata regulator;
struct as3711_bl_pdata backlight;
};
#endif

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include/linux/mfd/as3722.h Normal file
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/*
* as3722 definitions
*
* Copyright (C) 2013 ams
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
*
* Author: Florian Lobmaier <florian.lobmaier@ams.com>
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __LINUX_MFD_AS3722_H__
#define __LINUX_MFD_AS3722_H__
#include <linux/regmap.h>
/* AS3722 registers */
#define AS3722_SD0_VOLTAGE_REG 0x00
#define AS3722_SD1_VOLTAGE_REG 0x01
#define AS3722_SD2_VOLTAGE_REG 0x02
#define AS3722_SD3_VOLTAGE_REG 0x03
#define AS3722_SD4_VOLTAGE_REG 0x04
#define AS3722_SD5_VOLTAGE_REG 0x05
#define AS3722_SD6_VOLTAGE_REG 0x06
#define AS3722_GPIO0_CONTROL_REG 0x08
#define AS3722_GPIO1_CONTROL_REG 0x09
#define AS3722_GPIO2_CONTROL_REG 0x0A
#define AS3722_GPIO3_CONTROL_REG 0x0B
#define AS3722_GPIO4_CONTROL_REG 0x0C
#define AS3722_GPIO5_CONTROL_REG 0x0D
#define AS3722_GPIO6_CONTROL_REG 0x0E
#define AS3722_GPIO7_CONTROL_REG 0x0F
#define AS3722_LDO0_VOLTAGE_REG 0x10
#define AS3722_LDO1_VOLTAGE_REG 0x11
#define AS3722_LDO2_VOLTAGE_REG 0x12
#define AS3722_LDO3_VOLTAGE_REG 0x13
#define AS3722_LDO4_VOLTAGE_REG 0x14
#define AS3722_LDO5_VOLTAGE_REG 0x15
#define AS3722_LDO6_VOLTAGE_REG 0x16
#define AS3722_LDO7_VOLTAGE_REG 0x17
#define AS3722_LDO9_VOLTAGE_REG 0x19
#define AS3722_LDO10_VOLTAGE_REG 0x1A
#define AS3722_LDO11_VOLTAGE_REG 0x1B
#define AS3722_GPIO_DEB1_REG 0x1E
#define AS3722_GPIO_DEB2_REG 0x1F
#define AS3722_GPIO_SIGNAL_OUT_REG 0x20
#define AS3722_GPIO_SIGNAL_IN_REG 0x21
#define AS3722_REG_SEQU_MOD1_REG 0x22
#define AS3722_REG_SEQU_MOD2_REG 0x23
#define AS3722_REG_SEQU_MOD3_REG 0x24
#define AS3722_SD_PHSW_CTRL_REG 0x27
#define AS3722_SD_PHSW_STATUS 0x28
#define AS3722_SD0_CONTROL_REG 0x29
#define AS3722_SD1_CONTROL_REG 0x2A
#define AS3722_SDmph_CONTROL_REG 0x2B
#define AS3722_SD23_CONTROL_REG 0x2C
#define AS3722_SD4_CONTROL_REG 0x2D
#define AS3722_SD5_CONTROL_REG 0x2E
#define AS3722_SD6_CONTROL_REG 0x2F
#define AS3722_SD_DVM_REG 0x30
#define AS3722_RESET_REASON_REG 0x31
#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
#define AS3722_STARTUP_CONTROL_REG 0x33
#define AS3722_RESET_TIMER_REG 0x34
#define AS3722_REFERENCE_CONTROL_REG 0x35
#define AS3722_RESET_CONTROL_REG 0x36
#define AS3722_OVER_TEMP_CONTROL_REG 0x37
#define AS3722_WATCHDOG_CONTROL_REG 0x38
#define AS3722_REG_STANDBY_MOD1_REG 0x39
#define AS3722_REG_STANDBY_MOD2_REG 0x3A
#define AS3722_REG_STANDBY_MOD3_REG 0x3B
#define AS3722_ENABLE_CTRL1_REG 0x3C
#define AS3722_ENABLE_CTRL2_REG 0x3D
#define AS3722_ENABLE_CTRL3_REG 0x3E
#define AS3722_ENABLE_CTRL4_REG 0x3F
#define AS3722_ENABLE_CTRL5_REG 0x40
#define AS3722_PWM_CONTROL_L_REG 0x41
#define AS3722_PWM_CONTROL_H_REG 0x42
#define AS3722_WATCHDOG_TIMER_REG 0x46
#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
#define AS3722_IOVOLTAGE_REG 0x49
#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
#define AS3722_SD_CONTROL_REG 0x4D
#define AS3722_LDOCONTROL0_REG 0x4E
#define AS3722_LDOCONTROL1_REG 0x4F
#define AS3722_SD0_PROTECT_REG 0x50
#define AS3722_SD6_PROTECT_REG 0x51
#define AS3722_PWM_VCONTROL1_REG 0x52
#define AS3722_PWM_VCONTROL2_REG 0x53
#define AS3722_PWM_VCONTROL3_REG 0x54
#define AS3722_PWM_VCONTROL4_REG 0x55
#define AS3722_BB_CHARGER_REG 0x57
#define AS3722_CTRL_SEQU1_REG 0x58
#define AS3722_CTRL_SEQU2_REG 0x59
#define AS3722_OVCURRENT_REG 0x5A
#define AS3722_OVCURRENT_DEB_REG 0x5B
#define AS3722_SDLV_DEB_REG 0x5C
#define AS3722_OC_PG_CTRL_REG 0x5D
#define AS3722_OC_PG_CTRL2_REG 0x5E
#define AS3722_CTRL_STATUS 0x5F
#define AS3722_RTC_CONTROL_REG 0x60
#define AS3722_RTC_SECOND_REG 0x61
#define AS3722_RTC_MINUTE_REG 0x62
#define AS3722_RTC_HOUR_REG 0x63
#define AS3722_RTC_DAY_REG 0x64
#define AS3722_RTC_MONTH_REG 0x65
#define AS3722_RTC_YEAR_REG 0x66
#define AS3722_RTC_ALARM_SECOND_REG 0x67
#define AS3722_RTC_ALARM_MINUTE_REG 0x68
#define AS3722_RTC_ALARM_HOUR_REG 0x69
#define AS3722_RTC_ALARM_DAY_REG 0x6A
#define AS3722_RTC_ALARM_MONTH_REG 0x6B
#define AS3722_RTC_ALARM_YEAR_REG 0x6C
#define AS3722_SRAM_REG 0x6D
#define AS3722_RTC_ACCESS_REG 0x6F
#define AS3722_RTC_STATUS_REG 0x73
#define AS3722_INTERRUPT_MASK1_REG 0x74
#define AS3722_INTERRUPT_MASK2_REG 0x75
#define AS3722_INTERRUPT_MASK3_REG 0x76
#define AS3722_INTERRUPT_MASK4_REG 0x77
#define AS3722_INTERRUPT_STATUS1_REG 0x78
#define AS3722_INTERRUPT_STATUS2_REG 0x79
#define AS3722_INTERRUPT_STATUS3_REG 0x7A
#define AS3722_INTERRUPT_STATUS4_REG 0x7B
#define AS3722_TEMP_STATUS_REG 0x7D
#define AS3722_ADC0_CONTROL_REG 0x80
#define AS3722_ADC1_CONTROL_REG 0x81
#define AS3722_ADC0_MSB_RESULT_REG 0x82
#define AS3722_ADC0_LSB_RESULT_REG 0x83
#define AS3722_ADC1_MSB_RESULT_REG 0x84
#define AS3722_ADC1_LSB_RESULT_REG 0x85
#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
#define AS3722_ADC_CONFIGURATION_REG 0x8A
#define AS3722_ASIC_ID1_REG 0x90
#define AS3722_ASIC_ID2_REG 0x91
#define AS3722_LOCK_REG 0x9E
#define AS3722_FUSE7_REG 0xA7
#define AS3722_FUSE15_REG 0xAF
#define AS3722_STBY_REG0_CONTROL_REG 0xE0
#define AS3722_STBY_REG1_CONTROL_REG 0xE1
#define AS3722_STBY_REG2_CONTROL_REG 0xE2
#define AS3722_STBY_REG3_CONTROL_REG 0xE3
#define AS3722_STBY_REG4_CONTROL_REG 0xE4
#define AS3722_STBY_REG5_CONTROL_REG 0xE5
#define AS3722_STBY_REG6_CONTROL_REG 0xE6
#define AS3722_STBY_REG7_CONTROL_REG 0xE7
#define AS3722_STBY_REG8_CONTROL_REG 0xE8
#define AS3722_STBY_REG9_CONTROL_REG 0xE9
#define AS3722_STBY_REG0_VOLTAGE_REG 0xEA
#define AS3722_STBY_REG1_VOLTAGE_REG 0xEB
#define AS3722_STBY_REG2_VOLTAGE_REG 0xEC
#define AS3722_STBY_REG3_VOLTAGE_REG 0xED
#define AS3722_STBY_REG4_VOLTAGE_REG 0xEE
#define AS3722_STBY_REG5_VOLTAGE_REG 0xEF
#define AS3722_STBY_REG6_VOLTAGE_REG 0xF0
#define AS3722_STBY_REG7_VOLTAGE_REG 0xF1
#define AS3722_STBY_REG8_VOLTAGE_REG 0xF2
#define AS3722_STBY_REG9_VOLTAGE_REG 0xF3
#define AS3722_MAX_REGISTER 0xF4
#define AS3722_SD0_STBY_ON BIT(0)
#define AS3722_SD1_STBY_ON BIT(1)
#define AS3722_SD2_STBY_ON BIT(2)
#define AS3722_SD3_STBY_ON BIT(3)
#define AS3722_SD4_STBY_ON BIT(4)
#define AS3722_SD5_STBY_ON BIT(5)
#define AS3722_SD6_STBY_ON BIT(6)
#define AS3722_LDO0_STBY_ON BIT(0)
#define AS3722_LDO1_STBY_ON BIT(1)
#define AS3722_LDO2_STBY_ON BIT(2)
#define AS3722_LDO3_STBY_ON BIT(3)
#define AS3722_LDO4_STBY_ON BIT(4)
#define AS3722_LDO5_STBY_ON BIT(5)
#define AS3722_LDO6_STBY_ON BIT(6)
#define AS3722_LDO7_STBY_ON BIT(7)
#define AS3722_LDO9_STBY_ON BIT(0)
#define AS3722_LDO10_STBY_ON BIT(1)
#define AS3722_LDO11_STBY_ON BIT(2)
#define AS3722_SD0_EXT_ENABLE_MASK 0x03
#define AS3722_SD1_EXT_ENABLE_MASK 0x0C
#define AS3722_SD2_EXT_ENABLE_MASK 0x30
#define AS3722_SD3_EXT_ENABLE_MASK 0xC0
#define AS3722_SD4_EXT_ENABLE_MASK 0x03
#define AS3722_SD5_EXT_ENABLE_MASK 0x0C
#define AS3722_SD6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO0_EXT_ENABLE_MASK 0x03
#define AS3722_LDO1_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO2_EXT_ENABLE_MASK 0x30
#define AS3722_LDO3_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO4_EXT_ENABLE_MASK 0x03
#define AS3722_LDO5_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO7_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO9_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO10_EXT_ENABLE_MASK 0x30
#define AS3722_LDO11_EXT_ENABLE_MASK 0xC0
#define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03
#define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60
#define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05
#define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03
/* AS3722 register bits and bit masks */
#define AS3722_LDO_ILIMIT_MASK BIT(7)
#define AS3722_LDO_ILIMIT_BIT BIT(7)
#define AS3722_LDO0_VSEL_MASK 0x1F
#define AS3722_LDO0_VSEL_MIN 0x01
#define AS3722_LDO0_VSEL_MAX 0x12
#define AS3722_LDO0_NUM_VOLT 0x12
#define AS3722_LDO3_VSEL_MASK 0x3F
#define AS3722_LDO3_VSEL_MIN 0x01
#define AS3722_LDO3_VSEL_MAX 0x2D
#define AS3722_LDO3_NUM_VOLT 0x2D
#define AS3722_LDO_VSEL_MASK 0x7F
#define AS3722_LDO_VSEL_MIN 0x01
#define AS3722_LDO_VSEL_MAX 0x7F
#define AS3722_LDO_VSEL_DNU_MIN 0x25
#define AS3722_LDO_VSEL_DNU_MAX 0x3F
#define AS3722_LDO_NUM_VOLT 0x80
#define AS3722_LDO0_CTRL BIT(0)
#define AS3722_LDO1_CTRL BIT(1)
#define AS3722_LDO2_CTRL BIT(2)
#define AS3722_LDO3_CTRL BIT(3)
#define AS3722_LDO4_CTRL BIT(4)
#define AS3722_LDO5_CTRL BIT(5)
#define AS3722_LDO6_CTRL BIT(6)
#define AS3722_LDO7_CTRL BIT(7)
#define AS3722_LDO9_CTRL BIT(1)
#define AS3722_LDO10_CTRL BIT(2)
#define AS3722_LDO11_CTRL BIT(3)
#define AS3722_LDO3_MODE_MASK (3 << 6)
#define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6)
#define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0)
#define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1)
#define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2)
#define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3)
#define AS3722_SD_VSEL_MASK 0x7F
#define AS3722_SD0_VSEL_MIN 0x01
#define AS3722_SD0_VSEL_MAX 0x5A
#define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E
#define AS3722_SD2_VSEL_MIN 0x01
#define AS3722_SD2_VSEL_MAX 0x7F
#define AS3722_SDn_CTRL(n) BIT(n)
#define AS3722_SD0_MODE_FAST BIT(4)
#define AS3722_SD1_MODE_FAST BIT(4)
#define AS3722_SD2_MODE_FAST BIT(2)
#define AS3722_SD3_MODE_FAST BIT(6)
#define AS3722_SD4_MODE_FAST BIT(2)
#define AS3722_SD5_MODE_FAST BIT(2)
#define AS3722_SD6_MODE_FAST BIT(4)
#define AS3722_POWER_OFF BIT(1)
#define AS3722_INTERRUPT_MASK1_LID BIT(0)
#define AS3722_INTERRUPT_MASK1_ACOK BIT(1)
#define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2)
#define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3)
#define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4)
#define AS3722_INTERRUPT_MASK1_ONKEY BIT(5)
#define AS3722_INTERRUPT_MASK1_OVTMP BIT(6)
#define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
#define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0)
#define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1)
#define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2)
#define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3)
#define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4)
#define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5)
#define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6)
#define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
#define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0)
#define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1)
#define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2)
#define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3)
#define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4)
#define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5)
#define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6)
#define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5)
#define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6)
#define AS3722_INTERRUPT_MASK4_ADC BIT(7)
#define AS3722_ADC1_INTERVAL_TIME BIT(0)
#define AS3722_ADC1_INT_MODE_ON BIT(1)
#define AS3722_ADC_BUF_ON BIT(2)
#define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5)
#define AS3722_ADC1_INTEVAL_SCAN BIT(6)
#define AS3722_ADC1_INT_MASK BIT(7)
#define AS3722_ADC_MSB_VAL_MASK 0x7F
#define AS3722_ADC_LSB_VAL_MASK 0x07
#define AS3722_ADC0_CONV_START BIT(7)
#define AS3722_ADC0_CONV_NOTREADY BIT(7)
#define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F
#define AS3722_ADC1_CONV_START BIT(7)
#define AS3722_ADC1_CONV_NOTREADY BIT(7)
#define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F
/* GPIO modes */
#define AS3722_GPIO_MODE_MASK 0x07
#define AS3722_GPIO_MODE_INPUT 0x00
#define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02
#define AS3722_GPIO_MODE_ADC_IN 0x03
#define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04
#define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06
#define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07
#define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK)
#define AS3722_GPIO_INV BIT(7)
#define AS3722_GPIO_IOSF_MASK 0x78
#define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3)
#define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0)
#define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1)
#define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2)
#define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3)
#define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4)
#define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5)
#define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6)
#define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7)
#define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8)
#define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9)
#define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11)
#define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12)
#define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13)
#define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14)
#define AS3722_GPIOn_SIGNAL(n) BIT(n)
#define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n)
#define AS3722_I2C_PULL_UP BIT(4)
#define AS3722_INT_PULL_UP BIT(5)
#define AS3722_RTC_REP_WAKEUP_EN BIT(0)
#define AS3722_RTC_ALARM_WAKEUP_EN BIT(1)
#define AS3722_RTC_ON BIT(2)
#define AS3722_RTC_IRQMODE BIT(3)
#define AS3722_RTC_CLK32K_OUT_EN BIT(5)
#define AS3722_WATCHDOG_TIMER_MAX 0x7F
#define AS3722_WATCHDOG_ON BIT(0)
#define AS3722_WATCHDOG_SW_SIG BIT(0)
#define AS3722_EXT_CONTROL_ENABLE1 0x1
#define AS3722_EXT_CONTROL_ENABLE2 0x2
#define AS3722_EXT_CONTROL_ENABLE3 0x3
#define AS3722_ENABLE1_DEEPSLEEP BIT(5)
#define AS3722_RES_TIMER_VAL(n) ((n) & 0x3)
#define AS2722_RES_TIMER_0 AS3722_RES_TIMER_VAL(0)
#define AS3722_RES_TIMER_50 AS3722_RES_TIMER_VAL(1)
#define AS3722_RES_TIMER_100 AS3722_RES_TIMER_VAL(2)
#define AS3722_RES_TIMER_150 AS3722_RES_TIMER_VAL(3)
#define AS3722_OFF_DELAY_VAL(n) (((n) & 0x3) << 3)
#define AS3722_OFF_DELAY_0 AS3722_OFF_DELAY_VAL(0)
#define AS3722_OFF_DELAY_8 AS3722_OFF_DELAY_VAL(1)
#define AS3722_OFF_DELAY_16 AS3722_OFF_DELAY_VAL(2)
#define AS3722_OFF_DELAY_32 AS3722_OFF_DELAY_VAL(3)
#define AS3722_AUTO_OFF BIT(5)
#define AS3722_DEEPSLEEP_RESET_ENABLE BIT(6)
#define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4)
#define AS3722_FUSE15_NCELL_MASK 0x3
#define AS3722_FUSE15_SD0_LOW_VOLTAGE 0x2
#define AS3722_STBY_CONTROL_MAX_SLOT 9
#define AS3722_STBY_REGn_CONTROL_REG(n) (AS3722_STBY_REG0_CONTROL_REG + (n))
#define AS3722_STBY_REG_SELECT_MASK 0x1f
#define AS3722_STBY_REGn_VOLTAGE_REG(n) (AS3722_STBY_REG0_VOLTAGE_REG + (n))
/* Interrupt IDs */
enum as3722_irq {
AS3722_IRQ_LID,
AS3722_IRQ_ACOK,
AS3722_IRQ_ENABLE1,
AS3722_IRQ_OCCUR_ALARM_SD0,
AS3722_IRQ_ONKEY_LONG_PRESS,
AS3722_IRQ_ONKEY,
AS3722_IRQ_OVTMP,
AS3722_IRQ_LOWBAT,
AS3722_IRQ_SD0_LV,
AS3722_IRQ_SD1_LV,
AS3722_IRQ_SD2_LV,
AS3722_IRQ_PWM1_OV_PROT,
AS3722_IRQ_PWM2_OV_PROT,
AS3722_IRQ_ENABLE2,
AS3722_IRQ_SD6_LV,
AS3722_IRQ_RTC_REP,
AS3722_IRQ_RTC_ALARM,
AS3722_IRQ_GPIO1,
AS3722_IRQ_GPIO2,
AS3722_IRQ_GPIO3,
AS3722_IRQ_GPIO4,
AS3722_IRQ_GPIO5,
AS3722_IRQ_WATCHDOG,
AS3722_IRQ_ENABLE3,
AS3722_IRQ_TEMP_SD0_SHUTDOWN,
AS3722_IRQ_TEMP_SD1_SHUTDOWN,
AS3722_IRQ_TEMP_SD2_SHUTDOWN,
AS3722_IRQ_TEMP_SD0_ALARM,
AS3722_IRQ_TEMP_SD1_ALARM,
AS3722_IRQ_TEMP_SD6_ALARM,
AS3722_IRQ_OCCUR_ALARM_SD6,
AS3722_IRQ_ADC,
AS3722_IRQ_MAX,
};
struct as3722 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
unsigned long irq_flags;
bool en_intern_int_pullup;
bool en_intern_i2c_pullup;
struct regmap_irq_chip_data *irq_data;
};
static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)
{
return regmap_read(as3722->regmap, reg, dest);
}
static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value)
{
return regmap_write(as3722->regmap, reg, value);
}
static inline int as3722_block_read(struct as3722 *as3722, u32 reg,
int count, u8 *buf)
{
return regmap_bulk_read(as3722->regmap, reg, buf, count);
}
static inline int as3722_block_write(struct as3722 *as3722, u32 reg,
int count, u8 *data)
{
return regmap_bulk_write(as3722->regmap, reg, data, count);
}
static inline int as3722_update_bits(struct as3722 *as3722, u32 reg,
u32 mask, u8 val)
{
return regmap_update_bits(as3722->regmap, reg, mask, val);
}
static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq)
{
return regmap_irq_get_virq(as3722->irq_data, irq);
}
#endif /* __LINUX_MFD_AS3722_H__ */

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/*
* include/linux/mfd/asic3.h
*
* Compaq ASIC3 headers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright 2001 Compaq Computer Corporation.
* Copyright 2007-2008 OpenedHand Ltd.
*/
#ifndef __ASIC3_H__
#define __ASIC3_H__
#include <linux/types.h>
struct led_classdev;
struct asic3_led {
const char *name;
const char *default_trigger;
struct led_classdev *cdev;
};
struct asic3_platform_data {
u16 *gpio_config;
unsigned int gpio_config_num;
unsigned int irq_base;
unsigned int gpio_base;
unsigned int clock_rate;
struct asic3_led *leds;
};
#define ASIC3_NUM_GPIO_BANKS 4
#define ASIC3_GPIOS_PER_BANK 16
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
#define ASIC3_IRQ_LED0 64
#define ASIC3_IRQ_LED1 65
#define ASIC3_IRQ_LED2 66
#define ASIC3_IRQ_SPI 67
#define ASIC3_IRQ_SMBUS 68
#define ASIC3_IRQ_OWM 69
#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
#define ASIC3_GPIO_BANK_A 0
#define ASIC3_GPIO_BANK_B 1
#define ASIC3_GPIO_BANK_C 2
#define ASIC3_GPIO_BANK_D 3
#define ASIC3_GPIO(bank, gpio) \
((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
/* All offsets below are specified with this address bus shift */
#define ASIC3_DEFAULT_ADDR_SHIFT 2
#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
#define ASIC3_GPIO_OFFSET(base, reg) \
(ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
#define ASIC3_GPIO_A_BASE 0x0000
#define ASIC3_GPIO_B_BASE 0x0100
#define ASIC3_GPIO_C_BASE 0x0200
#define ASIC3_GPIO_D_BASE 0x0300
#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
(ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
* R/W bit 1: autosleep
* 0: disable gposlpout in normal mode,
* enable gposlpout in sleep mode.
*/
#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
/*
* ASIC3 GPIO config
*
* Bits 0..6 gpio number
* Bits 7..13 Alternate function
* Bit 14 Direction
* Bit 15 Initial value
*
*/
#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
| (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
| (((init) & 0x1) << 15))
#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
/*
* Alternate functions
*/
#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0)
#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
#define ASIC3_SPI_Base 0x0400
#define ASIC3_SPI_Control 0x0000
#define ASIC3_SPI_TxData 0x0004
#define ASIC3_SPI_RxData 0x0008
#define ASIC3_SPI_Int 0x000c
#define ASIC3_SPI_Status 0x0010
#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
#define ASIC3_PWM_0_Base 0x0500
#define ASIC3_PWM_1_Base 0x0600
#define ASIC3_PWM_TimeBase 0x0000
#define ASIC3_PWM_PeriodTime 0x0004
#define ASIC3_PWM_DutyTime 0x0008
#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
#define ASIC3_NUM_LEDS 3
#define ASIC3_LED_0_Base 0x0700
#define ASIC3_LED_1_Base 0x0800
#define ASIC3_LED_2_Base 0x0900
#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
/* LED TimeBase bits - match ASIC2 */
#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
/* Note: max = 5 on hx4700 */
/* 0: maximum time base */
/* 1: maximum time base / 2 */
/* n: maximum time base / 2^n */
#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
#define ASIC3_CLOCK_BASE 0x0A00
#define ASIC3_CLOCK_CDEX 0x00
#define ASIC3_CLOCK_SEL 0x04
#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
#define CLOCK_CDEX_SOURCE0 (1 << 0)
#define CLOCK_CDEX_SOURCE1 (1 << 1)
#define CLOCK_CDEX_SPI (1 << 2)
#define CLOCK_CDEX_OWM (1 << 3)
#define CLOCK_CDEX_PWM0 (1 << 4)
#define CLOCK_CDEX_PWM1 (1 << 5)
#define CLOCK_CDEX_LED0 (1 << 6)
#define CLOCK_CDEX_LED1 (1 << 7)
#define CLOCK_CDEX_LED2 (1 << 8)
/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
#define CLOCK_CDEX_SMBUS (1 << 11)
#define CLOCK_CDEX_CONTROL_CX (1 << 12)
#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
/* R/W: INT clock source control (32.768 kHz) */
#define CLOCK_SEL_CX (1 << 2)
#define ASIC3_INTR_BASE 0x0B00
#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
#define ASIC3_INTMASK_MASK0 (1 << 2)
#define ASIC3_INTMASK_MASK1 (1 << 3)
#define ASIC3_INTMASK_MASK2 (1 << 4)
#define ASIC3_INTMASK_MASK3 (1 << 5)
#define ASIC3_INTMASK_MASK4 (1 << 6)
#define ASIC3_INTMASK_MASK5 (1 << 7)
#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
#define ASIC3_INTR_LED0 (1 << 4)
#define ASIC3_INTR_LED1 (1 << 5)
#define ASIC3_INTR_LED2 (1 << 6)
#define ASIC3_INTR_SPI (1 << 7)
#define ASIC3_INTR_SMBUS (1 << 8)
#define ASIC3_INTR_OWM (1 << 9)
#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
/* Basic control of the SD ASIC */
#define ASIC3_SDHWCTRL_BASE 0x0E00
#define ASIC3_SDHWCTRL_SDCONF 0x00
#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
/* SD card write protection: 0=high */
#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
/* SD card power supply ctrl 1=enable */
#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
#define ASIC3_EXTCF_BASE 0x1100
#define ASIC3_EXTCF_SELECT 0x00
#define ASIC3_EXTCF_RESET 0x04
#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
/*********************************************
* The Onewire interface (DS1WM) is handled
* by the ds1wm driver.
*
*********************************************/
#define ASIC3_OWM_BASE 0xC00
/*****************************************************************************
* The SD configuration registers are at a completely different location
* in memory. They are divided into three sets of registers:
*
* SD_CONFIG Core configuration register
* SD_CTRL Control registers for SD operations
* SDIO_CTRL Control registers for SDIO operations
*
*****************************************************************************/
#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
#define ASIC3_SD_CTRL_BASE 0x1000
#define ASIC3_SDIO_CTRL_BASE 0x1200
#define ASIC3_MAP_SIZE_32BIT 0x2000
#define ASIC3_MAP_SIZE_16BIT 0x1000
/* Functions needed by leds-asic3 */
struct asic3;
extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
#endif /* __ASIC3_H__ */

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/*
* drivers/mfd/mfd-core.h
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_CORE_H
#define MFD_CORE_H
#include <linux/platform_device.h>
struct irq_domain;
/*
* This struct describes the MFD part ("cell").
* After registration the copy of this structure will become the platform data
* of the resulting platform_device
*/
struct mfd_cell {
const char *name;
int id;
/* refcounting for multiple drivers to use a single cell */
atomic_t *usage_count;
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
/* platform data passed to the sub devices drivers */
void *platform_data;
size_t pdata_size;
/*
* Device Tree compatible string
* See: Documentation/devicetree/usage-model.txt Chapter 2.2 for details
*/
const char *of_compatible;
/*
* These resources can be specified relative to the parent device.
* For accessing hardware you should use resources from the platform dev
*/
int num_resources;
const struct resource *resources;
/* don't check for resource conflicts */
bool ignore_resource_conflicts;
/*
* Disable runtime PM callbacks for this subdevice - see
* pm_runtime_no_callbacks().
*/
bool pm_runtime_no_callbacks;
};
/*
* Convenience functions for clients using shared cells. Refcounting
* happens automatically, with the cell's enable/disable callbacks
* being called only when a device is first being enabled or no other
* clients are making use of it.
*/
extern int mfd_cell_enable(struct platform_device *pdev);
extern int mfd_cell_disable(struct platform_device *pdev);
/*
* "Clone" multiple platform devices for a single cell. This is to be used
* for devices that have multiple users of a cell. For example, if an mfd
* driver wants the cell "foo" to be used by a GPIO driver, an MTD driver,
* and a platform driver, the following bit of code would be use after first
* calling mfd_add_devices():
*
* const char *fclones[] = { "foo-gpio", "foo-mtd" };
* err = mfd_clone_cells("foo", fclones, ARRAY_SIZE(fclones));
*
* Each driver (MTD, GPIO, and platform driver) would then register
* platform_drivers for "foo-mtd", "foo-gpio", and "foo", respectively.
* The cell's .enable/.disable hooks should be used to deal with hardware
* resource contention.
*/
extern int mfd_clone_cell(const char *cell, const char **clones,
size_t n_clones);
/*
* Given a platform device that's been created by mfd_add_devices(), fetch
* the mfd_cell that created it.
*/
static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
{
return pdev->mfd_cell;
}
extern int mfd_add_devices(struct device *parent, int id,
struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *irq_domain);
extern void mfd_remove_devices(struct device *parent);
#endif

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/*
* ChromeOS EC multi-function device
*
* Copyright (C) 2012 Google, Inc
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_MFD_CROS_EC_H
#define __LINUX_MFD_CROS_EC_H
#include <linux/power_supply.h>
#include <linux/mfd/cros_ec_commands.h>
#include <linux/mfd/cros_ec_dev.h>
#include <linux/mutex.h>
/*
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
*/
enum {
EC_MSG_TX_HEADER_BYTES = 3,
EC_MSG_TX_TRAILER_BYTES = 1,
EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES +
EC_MSG_TX_TRAILER_BYTES,
EC_MSG_RX_PROTO_BYTES = 3,
/* Max length of messages */
EC_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE +
EC_MSG_TX_PROTO_BYTES,
};
/**
* struct cros_ec_device - Information about a ChromeOS EC device
*
* @ec_name: name of EC device (e.g. 'chromeos-ec')
* @phys_name: name of physical comms layer (e.g. 'i2c-4')
* @dev: Device pointer for physical comms device
* @vdev: Device pointer for virtual comms device
* @was_wake_device: true if this device was set to wake the system from
* sleep at the last suspend
* @cmd_read_mem: direct read of the EC memory-mapped region, if supported
* @offset is within EC_LPC_ADDR_MEMMAP region.
* @bytes: number of bytes to read. zero means "read a string" (including
* the trailing '\0'). At most only EC_MEMMAP_SIZE bytes can be read.
* Caller must ensure that the buffer is large enough for the result when
* reading a string.
*
* @priv: Private data
* @irq: Interrupt to use
* @din: input buffer (for data from EC)
* @dout: output buffer (for data to EC)
* \note
* These two buffers will always be dword-aligned and include enough
* space for up to 7 word-alignment bytes also, so we can ensure that
* the body of the message is always dword-aligned (64-bit).
* We use this alignment to keep ARM and x86 happy. Probably word
* alignment would be OK, there might be a small performance advantage
* to using dword.
* @din_size: size of din buffer to allocate (zero to use static din)
* @dout_size: size of dout buffer to allocate (zero to use static dout)
* @parent: pointer to parent device (e.g. i2c or spi device)
* @wake_enabled: true if this device can wake the system from sleep
* @lock: one transaction at a time
* @cmd_xfer: send command to EC and get response
* Returns the number of bytes received if the communication succeeded, but
* that doesn't mean the EC was happy with the command. The caller
* should check msg.result for the EC's result code.
*/
struct cros_ec_device {
/* These are used by other drivers that want to talk to the EC */
const char *ec_name;
const char *phys_name;
struct device *dev;
struct device *vdev;
bool was_wake_device;
struct class *cros_class;
int (*cmd_readmem)(struct cros_ec_device *ec, unsigned int offset,
unsigned int bytes, void *dest);
int (*cmd_read_u32)(struct cros_ec_device *ec, unsigned int offset,
u32 *dest);
int (*cmd_read_u16)(struct cros_ec_device *ec, unsigned int offset,
u16 *dest);
int (*cmd_read_u8)(struct cros_ec_device *ec, unsigned int offset,
u8 *dest);
/* These are used to implement the platform-specific interface */
void *priv;
int irq;
uint8_t *din;
uint8_t *dout;
int din_size;
int dout_size;
struct device *parent;
bool wake_enabled;
struct mutex lock;
int (*cmd_xfer)(struct cros_ec_device *ec,
struct cros_ec_command *msg);
struct power_supply *charger;
};
/**
* cros_ec_suspend - Handle a suspend operation for the ChromeOS EC device
*
* This can be called by drivers to handle a suspend event.
*
* ec_dev: Device to suspend
* @return 0 if ok, -ve on error
*/
int cros_ec_suspend(struct cros_ec_device *ec_dev);
/**
* cros_ec_resume - Handle a resume operation for the ChromeOS EC device
*
* This can be called by drivers to handle a resume event.
*
* @ec_dev: Device to resume
* @return 0 if ok, -ve on error
*/
int cros_ec_resume(struct cros_ec_device *ec_dev);
/**
* cros_ec_prepare_tx - Prepare an outgoing message in the output buffer
*
* This is intended to be used by all ChromeOS EC drivers, but at present
* only SPI uses it. Once LPC uses the same protocol it can start using it.
* I2C could use it now, with a refactor of the existing code.
*
* @ec_dev: Device to register
* @msg: Message to write
*/
int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
/**
* cros_ec_cmd_xfer - Send a command to the ChromeOS EC
*
* Call this to send a command to the ChromeOS EC. This should be used
* instead of calling the EC's cmd_xfer() callback directly.
*
* @ec_dev: EC device
* @msg: Message to write
*/
int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
/**
* cros_ec_remove - Remove a ChromeOS EC
*
* Call this to deregister a ChromeOS EC, then clean up any private data.
*
* @ec_dev: Device to register
* @return 0 if ok, -ve on error
*/
int cros_ec_remove(struct cros_ec_device *ec_dev);
/**
* cros_ec_register - Register a new ChromeOS EC, using the provided info
*
* Before calling this, allocate a pointer to a new device and then fill
* in all the fields up to the --private-- marker.
*
* @ec_dev: Device to register
* @return 0 if ok, -ve on error
*/
int cros_ec_register(struct cros_ec_device *ec_dev);
#endif /* __LINUX_MFD_CROS_EC_H */

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/*
* cros_ec_dev - expose the Chrome OS Embedded Controller to userspace
*
* Copyright (C) 2013 The Chromium OS Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _CROS_EC_DEV_H_
#define _CROS_EC_DEV_H_
#include <linux/ioctl.h>
#include <linux/types.h>
#define CROS_EC_DEV_NAME "cros_ec"
#define CROS_EC_DEV_VERSION "1.0.0"
/*
* @version: Command version number (often 0)
* @command: Command to send (EC_CMD_...)
* @outdata: Outgoing data to EC
* @outsize: Outgoing length in bytes
* @indata: Where to put the incoming data from EC
* @insize: Max number of bytes to accept from EC
* @result: EC's response to the command (separate from communication failure)
* ioctl returns the number of bytes returned from the EC, negative on error.
*/
struct cros_ec_command {
uint32_t version;
uint32_t command;
uint8_t *outdata;
uint32_t outsize;
uint8_t *indata;
uint32_t insize;
uint32_t result;
};
/*
* @offset: within EC_LPC_ADDR_MEMMAP region
* @bytes: number of bytes to read. zero means "read a string" (including '\0')
* (at most only EC_MEMMAP_SIZE bytes can be read)
* @buffer: where to store the result
* ioctl returns the number of bytes read, negative on error
*/
struct cros_ec_readmem {
uint32_t offset;
uint32_t bytes;
char *buffer;
};
#define CROS_EC_DEV_IOC ':'
#define CROS_EC_DEV_IOCXCMD _IOWR(':', 0, struct cros_ec_command)
#define CROS_EC_DEV_IOCRDMEM _IOWR(':', 1, struct cros_ec_readmem)
#endif /* _CROS_EC_DEV_H_ */

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#ifndef __LINUX_PMIC_DA903X_H
#define __LINUX_PMIC_DA903X_H
/* Unified sub device IDs for DA9030/DA9034/DA9035 */
enum {
DA9030_ID_LED_1,
DA9030_ID_LED_2,
DA9030_ID_LED_3,
DA9030_ID_LED_4,
DA9030_ID_LED_PC,
DA9030_ID_VIBRA,
DA9030_ID_WLED,
DA9030_ID_BUCK1,
DA9030_ID_BUCK2,
DA9030_ID_LDO1,
DA9030_ID_LDO2,
DA9030_ID_LDO3,
DA9030_ID_LDO4,
DA9030_ID_LDO5,
DA9030_ID_LDO6,
DA9030_ID_LDO7,
DA9030_ID_LDO8,
DA9030_ID_LDO9,
DA9030_ID_LDO10,
DA9030_ID_LDO11,
DA9030_ID_LDO12,
DA9030_ID_LDO13,
DA9030_ID_LDO14,
DA9030_ID_LDO15,
DA9030_ID_LDO16,
DA9030_ID_LDO17,
DA9030_ID_LDO18,
DA9030_ID_LDO19,
DA9030_ID_LDO_INT, /* LDO Internal */
DA9030_ID_BAT, /* battery charger */
DA9034_ID_LED_1,
DA9034_ID_LED_2,
DA9034_ID_VIBRA,
DA9034_ID_WLED,
DA9034_ID_TOUCH,
DA9034_ID_BUCK1,
DA9034_ID_BUCK2,
DA9034_ID_LDO1,
DA9034_ID_LDO2,
DA9034_ID_LDO3,
DA9034_ID_LDO4,
DA9034_ID_LDO5,
DA9034_ID_LDO6,
DA9034_ID_LDO7,
DA9034_ID_LDO8,
DA9034_ID_LDO9,
DA9034_ID_LDO10,
DA9034_ID_LDO11,
DA9034_ID_LDO12,
DA9034_ID_LDO13,
DA9034_ID_LDO14,
DA9034_ID_LDO15,
DA9035_ID_BUCK3,
};
/*
* DA9030/DA9034 LEDs sub-devices uses generic "struct led_info"
* as the platform_data
*/
/* DA9030 flags for "struct led_info"
*/
#define DA9030_LED_RATE_ON (0 << 5)
#define DA9030_LED_RATE_052S (1 << 5)
#define DA9030_LED_DUTY_1_16 (0 << 3)
#define DA9030_LED_DUTY_1_8 (1 << 3)
#define DA9030_LED_DUTY_1_4 (2 << 3)
#define DA9030_LED_DUTY_1_2 (3 << 3)
#define DA9030_VIBRA_MODE_1P3V (0 << 1)
#define DA9030_VIBRA_MODE_2P7V (1 << 1)
#define DA9030_VIBRA_FREQ_1HZ (0 << 2)
#define DA9030_VIBRA_FREQ_2HZ (1 << 2)
#define DA9030_VIBRA_FREQ_4HZ (2 << 2)
#define DA9030_VIBRA_FREQ_8HZ (3 << 2)
#define DA9030_VIBRA_DUTY_ON (0 << 4)
#define DA9030_VIBRA_DUTY_75P (1 << 4)
#define DA9030_VIBRA_DUTY_50P (2 << 4)
#define DA9030_VIBRA_DUTY_25P (3 << 4)
/* DA9034 flags for "struct led_info" */
#define DA9034_LED_RAMP (1 << 7)
/* DA9034 touch screen platform data */
struct da9034_touch_pdata {
int interval_ms; /* sampling interval while pen down */
int x_inverted;
int y_inverted;
};
struct da9034_backlight_pdata {
int output_current; /* output current of WLED, from 0-31 (in mA) */
};
/* DA9030 battery charger data */
struct power_supply_info;
struct da9030_battery_info {
/* battery parameters */
struct power_supply_info *battery_info;
/* current and voltage to use for battery charging */
unsigned int charge_milliamp;
unsigned int charge_millivolt;
/* voltage thresholds (in millivolts) */
int vbat_low;
int vbat_crit;
int vbat_charge_start;
int vbat_charge_stop;
int vbat_charge_restart;
/* battery nominal minimal and maximal voltages in millivolts */
int vcharge_min;
int vcharge_max;
/* Temperature thresholds. These are DA9030 register values
"as is" and should be measured for each battery type */
int tbat_low;
int tbat_high;
int tbat_restart;
/* battery monitor interval (seconds) */
unsigned int batmon_interval;
/* platform callbacks for battery low and critical events */
void (*battery_low)(void);
void (*battery_critical)(void);
};
struct da903x_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct da903x_platform_data {
int num_subdevs;
struct da903x_subdev_info *subdevs;
};
/* bit definitions for DA9030 events */
#define DA9030_EVENT_ONKEY (1 << 0)
#define DA9030_EVENT_PWREN (1 << 1)
#define DA9030_EVENT_EXTON (1 << 2)
#define DA9030_EVENT_CHDET (1 << 3)
#define DA9030_EVENT_TBAT (1 << 4)
#define DA9030_EVENT_VBATMON (1 << 5)
#define DA9030_EVENT_VBATMON_TXON (1 << 6)
#define DA9030_EVENT_CHIOVER (1 << 7)
#define DA9030_EVENT_TCTO (1 << 8)
#define DA9030_EVENT_CCTO (1 << 9)
#define DA9030_EVENT_ADC_READY (1 << 10)
#define DA9030_EVENT_VBUS_4P4 (1 << 11)
#define DA9030_EVENT_VBUS_4P0 (1 << 12)
#define DA9030_EVENT_SESS_VALID (1 << 13)
#define DA9030_EVENT_SRP_DETECT (1 << 14)
#define DA9030_EVENT_WATCHDOG (1 << 15)
#define DA9030_EVENT_LDO15 (1 << 16)
#define DA9030_EVENT_LDO16 (1 << 17)
#define DA9030_EVENT_LDO17 (1 << 18)
#define DA9030_EVENT_LDO18 (1 << 19)
#define DA9030_EVENT_LDO19 (1 << 20)
#define DA9030_EVENT_BUCK2 (1 << 21)
/* bit definitions for DA9034 events */
#define DA9034_EVENT_ONKEY (1 << 0)
#define DA9034_EVENT_EXTON (1 << 2)
#define DA9034_EVENT_CHDET (1 << 3)
#define DA9034_EVENT_TBAT (1 << 4)
#define DA9034_EVENT_VBATMON (1 << 5)
#define DA9034_EVENT_REV_IOVER (1 << 6)
#define DA9034_EVENT_CH_IOVER (1 << 7)
#define DA9034_EVENT_CH_TCTO (1 << 8)
#define DA9034_EVENT_CH_CCTO (1 << 9)
#define DA9034_EVENT_USB_DEV (1 << 10)
#define DA9034_EVENT_OTGCP_IOVER (1 << 11)
#define DA9034_EVENT_VBUS_4P55 (1 << 12)
#define DA9034_EVENT_VBUS_3P8 (1 << 13)
#define DA9034_EVENT_SESS_1P8 (1 << 14)
#define DA9034_EVENT_SRP_READY (1 << 15)
#define DA9034_EVENT_ADC_MAN (1 << 16)
#define DA9034_EVENT_ADC_AUTO4 (1 << 17)
#define DA9034_EVENT_ADC_AUTO5 (1 << 18)
#define DA9034_EVENT_ADC_AUTO6 (1 << 19)
#define DA9034_EVENT_PEN_DOWN (1 << 20)
#define DA9034_EVENT_TSI_READY (1 << 21)
#define DA9034_EVENT_UART_TX (1 << 22)
#define DA9034_EVENT_UART_RX (1 << 23)
#define DA9034_EVENT_HEADSET (1 << 25)
#define DA9034_EVENT_HOOKSWITCH (1 << 26)
#define DA9034_EVENT_WATCHDOG (1 << 27)
extern int da903x_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int da903x_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
/* Status Query Interface */
#define DA9030_STATUS_ONKEY (1 << 0)
#define DA9030_STATUS_PWREN1 (1 << 1)
#define DA9030_STATUS_EXTON (1 << 2)
#define DA9030_STATUS_CHDET (1 << 3)
#define DA9030_STATUS_TBAT (1 << 4)
#define DA9030_STATUS_VBATMON (1 << 5)
#define DA9030_STATUS_VBATMON_TXON (1 << 6)
#define DA9030_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_ONKEY (1 << 0)
#define DA9034_STATUS_EXTON (1 << 2)
#define DA9034_STATUS_CHDET (1 << 3)
#define DA9034_STATUS_TBAT (1 << 4)
#define DA9034_STATUS_VBATMON (1 << 5)
#define DA9034_STATUS_PEN_DOWN (1 << 6)
#define DA9034_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_USB_DEV (1 << 8)
#define DA9034_STATUS_HEADSET (1 << 9)
#define DA9034_STATUS_HOOKSWITCH (1 << 10)
#define DA9034_STATUS_REMCON (1 << 11)
#define DA9034_STATUS_VBUS_VALID_4P55 (1 << 12)
#define DA9034_STATUS_VBUS_VALID_3P8 (1 << 13)
#define DA9034_STATUS_SESS_VALID_1P8 (1 << 14)
#define DA9034_STATUS_SRP_READY (1 << 15)
extern int da903x_query_status(struct device *dev, unsigned int status);
/* NOTE: the functions below are not intended for use outside
* of the DA903x sub-device drivers
*/
extern int da903x_write(struct device *dev, int reg, uint8_t val);
extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_read(struct device *dev, int reg, uint8_t *val);
extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
#endif /* __LINUX_PMIC_DA903X_H */

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/*
* da9052 declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MFD_DA9052_DA9052_H
#define __MFD_DA9052_DA9052_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/list.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9052/reg.h>
/* Common - HWMON Channel Definations */
#define DA9052_ADC_VDDOUT 0
#define DA9052_ADC_ICH 1
#define DA9052_ADC_TBAT 2
#define DA9052_ADC_VBAT 3
#define DA9052_ADC_IN4 4
#define DA9052_ADC_IN5 5
#define DA9052_ADC_IN6 6
#define DA9052_ADC_TSI 7
#define DA9052_ADC_TJUNC 8
#define DA9052_ADC_VBBAT 9
#define DA9052_IRQ_DCIN 0
#define DA9052_IRQ_VBUS 1
#define DA9052_IRQ_DCINREM 2
#define DA9052_IRQ_VBUSREM 3
#define DA9052_IRQ_VDDLOW 4
#define DA9052_IRQ_ALARM 5
#define DA9052_IRQ_SEQRDY 6
#define DA9052_IRQ_COMP1V2 7
#define DA9052_IRQ_NONKEY 8
#define DA9052_IRQ_IDFLOAT 9
#define DA9052_IRQ_IDGND 10
#define DA9052_IRQ_CHGEND 11
#define DA9052_IRQ_TBAT 12
#define DA9052_IRQ_ADC_EOM 13
#define DA9052_IRQ_PENDOWN 14
#define DA9052_IRQ_TSIREADY 15
#define DA9052_IRQ_GPI0 16
#define DA9052_IRQ_GPI1 17
#define DA9052_IRQ_GPI2 18
#define DA9052_IRQ_GPI3 19
#define DA9052_IRQ_GPI4 20
#define DA9052_IRQ_GPI5 21
#define DA9052_IRQ_GPI6 22
#define DA9052_IRQ_GPI7 23
#define DA9052_IRQ_GPI8 24
#define DA9052_IRQ_GPI9 25
#define DA9052_IRQ_GPI10 26
#define DA9052_IRQ_GPI11 27
#define DA9052_IRQ_GPI12 28
#define DA9052_IRQ_GPI13 29
#define DA9052_IRQ_GPI14 30
#define DA9052_IRQ_GPI15 31
enum da9052_chip_id {
DA9052,
DA9053_AA,
DA9053_BA,
DA9053_BB,
};
struct da9052_pdata;
struct da9052 {
struct device *dev;
struct regmap *regmap;
struct mutex auxadc_lock;
struct completion done;
int irq_base;
struct regmap_irq_chip_data *irq_data;
u8 chip_id;
int chip_irq;
/* SOC I/O transfer related fixes for DA9052/53 */
int (*fix_io) (struct da9052 *da9052, unsigned char reg);
};
/* ADC API */
int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
int da9052_adc_read_temp(struct da9052 *da9052);
/* Device I/O API */
static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9052->regmap, reg, &val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return val;
}
static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
unsigned char val)
{
int ret;
ret = regmap_write(da9052->regmap, reg, val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret;
ret = regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret;
ret = regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
int ret;
ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
if (ret < 0)
return ret;
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
if (ret < 0)
return ret;
}
return ret;
}
int da9052_device_init(struct da9052 *da9052, u8 chip_id);
void da9052_device_exit(struct da9052 *da9052);
extern struct regmap_config da9052_regmap_config;
int da9052_irq_init(struct da9052 *da9052);
int da9052_irq_exit(struct da9052 *da9052);
int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
irq_handler_t handler, void *data);
void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
int da9052_enable_irq(struct da9052 *da9052, int irq);
int da9052_disable_irq(struct da9052 *da9052, int irq);
int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
#endif /* __MFD_DA9052_DA9052_H */

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/*
* Platform data declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MFD_DA9052_PDATA_H__
#define __MFD_DA9052_PDATA_H__
#define DA9052_MAX_REGULATORS 14
struct da9052;
struct da9052_pdata {
struct led_platform_data *pled;
int (*init) (struct da9052 *da9052);
int irq_base;
int gpio_base;
int use_for_apm;
struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
};
#endif

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include/linux/mfd/da9052/reg.h Normal file
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/*
* Register declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __LINUX_MFD_DA9052_REG_H
#define __LINUX_MFD_DA9052_REG_H
/* PAGE REGISTERS */
#define DA9052_PAGE0_CON_REG 0
#define DA9052_PAGE1_CON_REG 128
/* STATUS REGISTERS */
#define DA9052_STATUS_A_REG 1
#define DA9052_STATUS_B_REG 2
#define DA9052_STATUS_C_REG 3
#define DA9052_STATUS_D_REG 4
/* PARK REGISTER */
#define DA9052_PARK_REGISTER DA9052_STATUS_D_REG
/* EVENT REGISTERS */
#define DA9052_EVENT_A_REG 5
#define DA9052_EVENT_B_REG 6
#define DA9052_EVENT_C_REG 7
#define DA9052_EVENT_D_REG 8
#define DA9052_FAULTLOG_REG 9
/* IRQ REGISTERS */
#define DA9052_IRQ_MASK_A_REG 10
#define DA9052_IRQ_MASK_B_REG 11
#define DA9052_IRQ_MASK_C_REG 12
#define DA9052_IRQ_MASK_D_REG 13
/* CONTROL REGISTERS */
#define DA9052_CONTROL_A_REG 14
#define DA9052_CONTROL_B_REG 15
#define DA9052_CONTROL_C_REG 16
#define DA9052_CONTROL_D_REG 17
#define DA9052_PDDIS_REG 18
#define DA9052_INTERFACE_REG 19
#define DA9052_RESET_REG 20
/* GPIO REGISTERS */
#define DA9052_GPIO_0_1_REG 21
#define DA9052_GPIO_2_3_REG 22
#define DA9052_GPIO_4_5_REG 23
#define DA9052_GPIO_6_7_REG 24
#define DA9052_GPIO_14_15_REG 28
/* POWER SEQUENCER CONTROL REGISTERS */
#define DA9052_ID_0_1_REG 29
#define DA9052_ID_2_3_REG 30
#define DA9052_ID_4_5_REG 31
#define DA9052_ID_6_7_REG 32
#define DA9052_ID_8_9_REG 33
#define DA9052_ID_10_11_REG 34
#define DA9052_ID_12_13_REG 35
#define DA9052_ID_14_15_REG 36
#define DA9052_ID_16_17_REG 37
#define DA9052_ID_18_19_REG 38
#define DA9052_ID_20_21_REG 39
#define DA9052_SEQ_STATUS_REG 40
#define DA9052_SEQ_A_REG 41
#define DA9052_SEQ_B_REG 42
#define DA9052_SEQ_TIMER_REG 43
/* LDO AND BUCK REGISTERS */
#define DA9052_BUCKA_REG 44
#define DA9052_BUCKB_REG 45
#define DA9052_BUCKCORE_REG 46
#define DA9052_BUCKPRO_REG 47
#define DA9052_BUCKMEM_REG 48
#define DA9052_BUCKPERI_REG 49
#define DA9052_LDO1_REG 50
#define DA9052_LDO2_REG 51
#define DA9052_LDO3_REG 52
#define DA9052_LDO4_REG 53
#define DA9052_LDO5_REG 54
#define DA9052_LDO6_REG 55
#define DA9052_LDO7_REG 56
#define DA9052_LDO8_REG 57
#define DA9052_LDO9_REG 58
#define DA9052_LDO10_REG 59
#define DA9052_SUPPLY_REG 60
#define DA9052_PULLDOWN_REG 61
#define DA9052_CHGBUCK_REG 62
#define DA9052_WAITCONT_REG 63
#define DA9052_ISET_REG 64
#define DA9052_BATCHG_REG 65
/* BATTERY CONTROL REGISTRS */
#define DA9052_CHG_CONT_REG 66
#define DA9052_INPUT_CONT_REG 67
#define DA9052_CHG_TIME_REG 68
#define DA9052_BBAT_CONT_REG 69
/* LED CONTROL REGISTERS */
#define DA9052_BOOST_REG 70
#define DA9052_LED_CONT_REG 71
#define DA9052_LEDMIN123_REG 72
#define DA9052_LED1_CONF_REG 73
#define DA9052_LED2_CONF_REG 74
#define DA9052_LED3_CONF_REG 75
#define DA9052_LED1CONT_REG 76
#define DA9052_LED2CONT_REG 77
#define DA9052_LED3CONT_REG 78
#define DA9052_LED_CONT_4_REG 79
#define DA9052_LED_CONT_5_REG 80
/* ADC CONTROL REGISTERS */
#define DA9052_ADC_MAN_REG 81
#define DA9052_ADC_CONT_REG 82
#define DA9052_ADC_RES_L_REG 83
#define DA9052_ADC_RES_H_REG 84
#define DA9052_VDD_RES_REG 85
#define DA9052_VDD_MON_REG 86
#define DA9052_ICHG_AV_REG 87
#define DA9052_ICHG_THD_REG 88
#define DA9052_ICHG_END_REG 89
#define DA9052_TBAT_RES_REG 90
#define DA9052_TBAT_HIGHP_REG 91
#define DA9052_TBAT_HIGHN_REG 92
#define DA9052_TBAT_LOW_REG 93
#define DA9052_T_OFFSET_REG 94
#define DA9052_ADCIN4_RES_REG 95
#define DA9052_AUTO4_HIGH_REG 96
#define DA9052_AUTO4_LOW_REG 97
#define DA9052_ADCIN5_RES_REG 98
#define DA9052_AUTO5_HIGH_REG 99
#define DA9052_AUTO5_LOW_REG 100
#define DA9052_ADCIN6_RES_REG 101
#define DA9052_AUTO6_HIGH_REG 102
#define DA9052_AUTO6_LOW_REG 103
#define DA9052_TJUNC_RES_REG 104
/* TSI CONTROL REGISTERS */
#define DA9052_TSI_CONT_A_REG 105
#define DA9052_TSI_CONT_B_REG 106
#define DA9052_TSI_X_MSB_REG 107
#define DA9052_TSI_Y_MSB_REG 108
#define DA9052_TSI_LSB_REG 109
#define DA9052_TSI_Z_MSB_REG 110
/* RTC COUNT REGISTERS */
#define DA9052_COUNT_S_REG 111
#define DA9052_COUNT_MI_REG 112
#define DA9052_COUNT_H_REG 113
#define DA9052_COUNT_D_REG 114
#define DA9052_COUNT_MO_REG 115
#define DA9052_COUNT_Y_REG 116
/* RTC CONTROL REGISTERS */
#define DA9052_ALARM_MI_REG 117
#define DA9052_ALARM_H_REG 118
#define DA9052_ALARM_D_REG 119
#define DA9052_ALARM_MO_REG 120
#define DA9052_ALARM_Y_REG 121
#define DA9052_SECOND_A_REG 122
#define DA9052_SECOND_B_REG 123
#define DA9052_SECOND_C_REG 124
#define DA9052_SECOND_D_REG 125
/* PAGE CONFIGURATION BIT */
#define DA9052_PAGE_CONF 0X80
/* STATUS REGISTER A BITS */
#define DA9052_STATUSA_VDATDET 0X80
#define DA9052_STATUSA_VBUSSEL 0X40
#define DA9052_STATUSA_DCINSEL 0X20
#define DA9052_STATUSA_VBUSDET 0X10
#define DA9052_STATUSA_DCINDET 0X08
#define DA9052_STATUSA_IDGND 0X04
#define DA9052_STATUSA_IDFLOAT 0X02
#define DA9052_STATUSA_NONKEY 0X01
/* STATUS REGISTER B BITS */
#define DA9052_STATUSB_COMPDET 0X80
#define DA9052_STATUSB_SEQUENCING 0X40
#define DA9052_STATUSB_GPFB2 0X20
#define DA9052_STATUSB_CHGTO 0X10
#define DA9052_STATUSB_CHGEND 0X08
#define DA9052_STATUSB_CHGLIM 0X04
#define DA9052_STATUSB_CHGPRE 0X02
#define DA9052_STATUSB_CHGATT 0X01
/* STATUS REGISTER C BITS */
#define DA9052_STATUSC_GPI7 0X80
#define DA9052_STATUSC_GPI6 0X40
#define DA9052_STATUSC_GPI5 0X20
#define DA9052_STATUSC_GPI4 0X10
#define DA9052_STATUSC_GPI3 0X08
#define DA9052_STATUSC_GPI2 0X04
#define DA9052_STATUSC_GPI1 0X02
#define DA9052_STATUSC_GPI0 0X01
/* STATUS REGISTER D BITS */
#define DA9052_STATUSD_GPI15 0X80
#define DA9052_STATUSD_GPI14 0X40
#define DA9052_STATUSD_GPI13 0X20
#define DA9052_STATUSD_GPI12 0X10
#define DA9052_STATUSD_GPI11 0X08
#define DA9052_STATUSD_GPI10 0X04
#define DA9052_STATUSD_GPI9 0X02
#define DA9052_STATUSD_GPI8 0X01
/* EVENT REGISTER A BITS */
#define DA9052_EVENTA_ECOMP1V2 0X80
#define DA9052_EVENTA_ESEQRDY 0X40
#define DA9052_EVENTA_EALRAM 0X20
#define DA9052_EVENTA_EVDDLOW 0X10
#define DA9052_EVENTA_EVBUSREM 0X08
#define DA9052_EVENTA_EDCINREM 0X04
#define DA9052_EVENTA_EVBUSDET 0X02
#define DA9052_EVENTA_EDCINDET 0X01
/* EVENT REGISTER B BITS */
#define DA9052_EVENTB_ETSIREADY 0X80
#define DA9052_EVENTB_EPENDOWN 0X40
#define DA9052_EVENTB_EADCEOM 0X20
#define DA9052_EVENTB_ETBAT 0X10
#define DA9052_EVENTB_ECHGEND 0X08
#define DA9052_EVENTB_EIDGND 0X04
#define DA9052_EVENTB_EIDFLOAT 0X02
#define DA9052_EVENTB_ENONKEY 0X01
/* EVENT REGISTER C BITS */
#define DA9052_EVENTC_EGPI7 0X80
#define DA9052_EVENTC_EGPI6 0X40
#define DA9052_EVENTC_EGPI5 0X20
#define DA9052_EVENTC_EGPI4 0X10
#define DA9052_EVENTC_EGPI3 0X08
#define DA9052_EVENTC_EGPI2 0X04
#define DA9052_EVENTC_EGPI1 0X02
#define DA9052_EVENTC_EGPI0 0X01
/* EVENT REGISTER D BITS */
#define DA9052_EVENTD_EGPI15 0X80
#define DA9052_EVENTD_EGPI14 0X40
#define DA9052_EVENTD_EGPI13 0X20
#define DA9052_EVENTD_EGPI12 0X10
#define DA9052_EVENTD_EGPI11 0X08
#define DA9052_EVENTD_EGPI10 0X04
#define DA9052_EVENTD_EGPI9 0X02
#define DA9052_EVENTD_EGPI8 0X01
/* IRQ MASK REGISTERS BITS */
#define DA9052_M_NONKEY 0X0100
/* TSI EVENT REGISTERS BITS */
#define DA9052_E_PEN_DOWN 0X4000
#define DA9052_E_TSI_READY 0X8000
/* FAULT LOG REGISTER BITS */
#define DA9052_FAULTLOG_WAITSET 0X80
#define DA9052_FAULTLOG_NSDSET 0X40
#define DA9052_FAULTLOG_KEYSHUT 0X20
#define DA9052_FAULTLOG_TEMPOVER 0X08
#define DA9052_FAULTLOG_VDDSTART 0X04
#define DA9052_FAULTLOG_VDDFAULT 0X02
#define DA9052_FAULTLOG_TWDERROR 0X01
/* CONTROL REGISTER A BITS */
#define DA9052_CONTROLA_GPIV 0X80
#define DA9052_CONTROLA_PMOTYPE 0X20
#define DA9052_CONTROLA_PMOV 0X10
#define DA9052_CONTROLA_PMIV 0X08
#define DA9052_CONTROLA_PMIFV 0X08
#define DA9052_CONTROLA_PWR1EN 0X04
#define DA9052_CONTROLA_PWREN 0X02
#define DA9052_CONTROLA_SYSEN 0X01
/* CONTROL REGISTER B BITS */
#define DA9052_CONTROLB_SHUTDOWN 0X80
#define DA9052_CONTROLB_DEEPSLEEP 0X40
#define DA9052_CONTROL_B_WRITEMODE 0X20
#define DA9052_CONTROLB_BBATEN 0X10
#define DA9052_CONTROLB_OTPREADEN 0X08
#define DA9052_CONTROLB_AUTOBOOT 0X04
#define DA9052_CONTROLB_ACTDIODE 0X02
#define DA9052_CONTROLB_BUCKMERGE 0X01
/* CONTROL REGISTER C BITS */
#define DA9052_CONTROLC_BLINKDUR 0X80
#define DA9052_CONTROLC_BLINKFRQ 0X60
#define DA9052_CONTROLC_DEBOUNCING 0X1C
#define DA9052_CONTROLC_PMFB2PIN 0X02
#define DA9052_CONTROLC_PMFB1PIN 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_CONTROLD_WATCHDOG 0X80
#define DA9052_CONTROLD_ACCDETEN 0X40
#define DA9052_CONTROLD_GPI1415SD 0X20
#define DA9052_CONTROLD_NONKEYSD 0X10
#define DA9052_CONTROLD_KEEPACTEN 0X08
#define DA9052_CONTROLD_TWDSCALE 0X07
/* POWER DOWN DISABLE REGISTER BITS */
#define DA9052_PDDIS_PMCONTPD 0X80
#define DA9052_PDDIS_OUT32KPD 0X40
#define DA9052_PDDIS_CHGBBATPD 0X20
#define DA9052_PDDIS_CHGPD 0X10
#define DA9052_PDDIS_HS2WIREPD 0X08
#define DA9052_PDDIS_PMIFPD 0X04
#define DA9052_PDDIS_GPADCPD 0X02
#define DA9052_PDDIS_GPIOPD 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_INTERFACE_IFBASEADDR 0XE0
#define DA9052_INTERFACE_NCSPOL 0X10
#define DA9052_INTERFACE_RWPOL 0X08
#define DA9052_INTERFACE_CPHA 0X04
#define DA9052_INTERFACE_CPOL 0X02
#define DA9052_INTERFACE_IFTYPE 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_RESET_RESETEVENT 0XC0
#define DA9052_RESET_RESETTIMER 0X3F
/* GPIO REGISTERS */
/* GPIO CONTROL REGISTER BITS */
#define DA9052_GPIO_EVEN_PORT_PIN 0X03
#define DA9052_GPIO_EVEN_PORT_TYPE 0X04
#define DA9052_GPIO_EVEN_PORT_MODE 0X08
#define DA9052_GPIO_ODD_PORT_PIN 0X30
#define DA9052_GPIO_ODD_PORT_TYPE 0X40
#define DA9052_GPIO_ODD_PORT_MODE 0X80
/*POWER SEQUENCER REGISTER BITS */
/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
#define DA9052_ID01_LDO1STEP 0XF0
#define DA9052_ID01_SYSPRE 0X04
#define DA9052_ID01_DEFSUPPLY 0X02
#define DA9052_ID01_NRESMODE 0X01
/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
#define DA9052_ID23_LDO3STEP 0XF0
#define DA9052_ID23_LDO2STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
#define DA9052_ID45_LDO5STEP 0XF0
#define DA9052_ID45_LDO4STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
#define DA9052_ID67_LDO7STEP 0XF0
#define DA9052_ID67_LDO6STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
#define DA9052_ID89_LDO9STEP 0XF0
#define DA9052_ID89_LDO8STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
#define DA9052_ID1011_PDDISSTEP 0XF0
#define DA9052_ID1011_LDO10STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
#define DA9052_ID1213_VMEMSWSTEP 0XF0
#define DA9052_ID1213_VPERISWSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
#define DA9052_ID1415_BUCKPROSTEP 0XF0
#define DA9052_ID1415_BUCKCORESTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
#define DA9052_ID1617_BUCKPERISTEP 0XF0
#define DA9052_ID1617_BUCKMEMSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
#define DA9052_ID1819_GPRISE2STEP 0XF0
#define DA9052_ID1819_GPRISE1STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
#define DA9052_ID2021_GPFALL2STEP 0XF0
#define DA9052_ID2021_GPFALL1STEP 0X0F
/* POWER SEQ STATUS REGISTER BITS */
#define DA9052_SEQSTATUS_SEQPOINTER 0XF0
#define DA9052_SEQSTATUS_WAITSTEP 0X0F
/* POWER SEQ A REGISTER BITS */
#define DA9052_SEQA_POWEREND 0XF0
#define DA9052_SEQA_SYSTEMEND 0X0F
/* POWER SEQ B REGISTER BITS */
#define DA9052_SEQB_PARTDOWN 0XF0
#define DA9052_SEQB_MAXCOUNT 0X0F
/* POWER SEQ TIMER REGISTER BITS */
#define DA9052_SEQTIMER_SEQDUMMY 0XF0
#define DA9052_SEQTIMER_SEQTIME 0X0F
/*POWER SUPPLY CONTROL REGISTER BITS */
/* BUCK REGISTER A BITS */
#define DA9052_BUCKA_BPROILIM 0XC0
#define DA9052_BUCKA_BPROMODE 0X30
#define DA9052_BUCKA_BCOREILIM 0X0C
#define DA9052_BUCKA_BCOREMODE 0X03
/* BUCK REGISTER B BITS */
#define DA9052_BUCKB_BERIILIM 0XC0
#define DA9052_BUCKB_BPERIMODE 0X30
#define DA9052_BUCKB_BMEMILIM 0X0C
#define DA9052_BUCKB_BMEMMODE 0X03
/* BUCKCORE REGISTER BITS */
#define DA9052_BUCKCORE_BCORECONF 0X80
#define DA9052_BUCKCORE_BCOREEN 0X40
#define DA9052_BUCKCORE_VBCORE 0X3F
/* BUCKPRO REGISTER BITS */
#define DA9052_BUCKPRO_BPROCONF 0X80
#define DA9052_BUCKPRO_BPROEN 0X40
#define DA9052_BUCKPRO_VBPRO 0X3F
/* BUCKMEM REGISTER BITS */
#define DA9052_BUCKMEM_BMEMCONF 0X80
#define DA9052_BUCKMEM_BMEMEN 0X40
#define DA9052_BUCKMEM_VBMEM 0X3F
/* BUCKPERI REGISTER BITS */
#define DA9052_BUCKPERI_BPERICONF 0X80
#define DA9052_BUCKPERI_BPERIEN 0X40
#define DA9052_BUCKPERI_BPERIHS 0X20
#define DA9052_BUCKPERI_VBPERI 0X1F
/* LDO1 REGISTER BITS */
#define DA9052_LDO1_LDO1CONF 0X80
#define DA9052_LDO1_LDO1EN 0X40
#define DA9052_LDO1_VLDO1 0X1F
/* LDO2 REGISTER BITS */
#define DA9052_LDO2_LDO2CONF 0X80
#define DA9052_LDO2_LDO2EN 0X40
#define DA9052_LDO2_VLDO2 0X3F
/* LDO3 REGISTER BITS */
#define DA9052_LDO3_LDO3CONF 0X80
#define DA9052_LDO3_LDO3EN 0X40
#define DA9052_LDO3_VLDO3 0X3F
/* LDO4 REGISTER BITS */
#define DA9052_LDO4_LDO4CONF 0X80
#define DA9052_LDO4_LDO4EN 0X40
#define DA9052_LDO4_VLDO4 0X3F
/* LDO5 REGISTER BITS */
#define DA9052_LDO5_LDO5CONF 0X80
#define DA9052_LDO5_LDO5EN 0X40
#define DA9052_LDO5_VLDO5 0X3F
/* LDO6 REGISTER BITS */
#define DA9052_LDO6_LDO6CONF 0X80
#define DA9052_LDO6_LDO6EN 0X40
#define DA9052_LDO6_VLDO6 0X3F
/* LDO7 REGISTER BITS */
#define DA9052_LDO7_LDO7CONF 0X80
#define DA9052_LDO7_LDO7EN 0X40
#define DA9052_LDO7_VLDO7 0X3F
/* LDO8 REGISTER BITS */
#define DA9052_LDO8_LDO8CONF 0X80
#define DA9052_LDO8_LDO8EN 0X40
#define DA9052_LDO8_VLDO8 0X3F
/* LDO9 REGISTER BITS */
#define DA9052_LDO9_LDO9CONF 0X80
#define DA9052_LDO9_LDO9EN 0X40
#define DA9052_LDO9_VLDO9 0X3F
/* LDO10 REGISTER BITS */
#define DA9052_LDO10_LDO10CONF 0X80
#define DA9052_LDO10_LDO10EN 0X40
#define DA9052_LDO10_VLDO10 0X3F
/* SUPPLY REGISTER BITS */
#define DA9052_SUPPLY_VLOCK 0X80
#define DA9052_SUPPLY_VMEMSWEN 0X40
#define DA9052_SUPPLY_VPERISWEN 0X20
#define DA9052_SUPPLY_VLDO3GO 0X10
#define DA9052_SUPPLY_VLDO2GO 0X08
#define DA9052_SUPPLY_VBMEMGO 0X04
#define DA9052_SUPPLY_VBPROGO 0X02
#define DA9052_SUPPLY_VBCOREGO 0X01
/* PULLDOWN REGISTER BITS */
#define DA9052_PULLDOWN_LDO5PDDIS 0X20
#define DA9052_PULLDOWN_LDO2PDDIS 0X10
#define DA9052_PULLDOWN_LDO1PDDIS 0X08
#define DA9052_PULLDOWN_MEMPDDIS 0X04
#define DA9052_PULLDOWN_PROPDDIS 0X02
#define DA9052_PULLDOWN_COREPDDIS 0X01
/* BAT CHARGER REGISTER BITS */
/* CHARGER BUCK REGISTER BITS */
#define DA9052_CHGBUCK_CHGTEMP 0X80
#define DA9052_CHGBUCK_CHGUSBILIM 0X40
#define DA9052_CHGBUCK_CHGBUCKLP 0X20
#define DA9052_CHGBUCK_CHGBUCKEN 0X10
#define DA9052_CHGBUCK_ISETBUCK 0X0F
/* WAIT COUNTER REGISTER BITS */
#define DA9052_WAITCONT_WAITDIR 0X80
#define DA9052_WAITCONT_RTCCLOCK 0X40
#define DA9052_WAITCONT_WAITMODE 0X20
#define DA9052_WAITCONT_EN32KOUT 0X10
#define DA9052_WAITCONT_DELAYTIME 0X0F
/* ISET CONTROL REGISTER BITS */
#define DA9052_ISET_ISETDCIN 0XF0
#define DA9052_ISET_ISETVBUS 0X0F
/* BATTERY CHARGER CONTROL REGISTER BITS */
#define DA9052_BATCHG_ICHGPRE 0XC0
#define DA9052_BATCHG_ICHGBAT 0X3F
/* CHARGER COUNTER REGISTER BITS */
#define DA9052_CHG_CONT_VCHG_BAT 0XF8
#define DA9052_CHG_CONT_TCTR 0X07
/* INPUT CONTROL REGISTER BITS */
#define DA9052_INPUT_CONT_TCTR_MODE 0X80
#define DA9052_INPUT_CONT_VBUS_SUSP 0X10
#define DA9052_INPUT_CONT_DCIN_SUSP 0X08
/* CHARGING TIME REGISTER BITS */
#define DA9052_CHGTIME_CHGTIME 0XFF
/* BACKUP BATTERY CONTROL REGISTER BITS */
#define DA9052_BBATCONT_BCHARGERISET 0XF0
#define DA9052_BBATCONT_BCHARGERVSET 0X0F
/* LED REGISTERS BITS */
/* LED BOOST REGISTER BITS */
#define DA9052_BOOST_EBFAULT 0X80
#define DA9052_BOOST_MBFAULT 0X40
#define DA9052_BOOST_BOOSTFRQ 0X20
#define DA9052_BOOST_BOOSTILIM 0X10
#define DA9052_BOOST_LED3INEN 0X08
#define DA9052_BOOST_LED2INEN 0X04
#define DA9052_BOOST_LED1INEN 0X02
#define DA9052_BOOST_BOOSTEN 0X01
/* LED CONTROL REGISTER BITS */
#define DA9052_LEDCONT_SELLEDMODE 0X80
#define DA9052_LEDCONT_LED3ICONT 0X40
#define DA9052_LEDCONT_LED3RAMP 0X20
#define DA9052_LEDCONT_LED3EN 0X10
#define DA9052_LEDCONT_LED2RAMP 0X08
#define DA9052_LEDCONT_LED2EN 0X04
#define DA9052_LEDCONT_LED1RAMP 0X02
#define DA9052_LEDCONT_LED1EN 0X01
/* LEDMIN123 REGISTER BIT */
#define DA9052_LEDMIN123_LEDMINCURRENT 0XFF
/* LED1CONF REGISTER BIT */
#define DA9052_LED1CONF_LED1CURRENT 0XFF
/* LED2CONF REGISTER BIT */
#define DA9052_LED2CONF_LED2CURRENT 0XFF
/* LED3CONF REGISTER BIT */
#define DA9052_LED3CONF_LED3CURRENT 0XFF
/* LED COUNT REGISTER BIT */
#define DA9052_LED_CONT_DIM 0X80
/* ADC MAN REGISTERS BITS */
#define DA9052_ADC_MAN_MAN_CONV 0X10
#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00
#define DA9052_ADC_MAN_MUXSEL_ICH 0X01
#define DA9052_ADC_MAN_MUXSEL_TBAT 0X02
#define DA9052_ADC_MAN_MUXSEL_VBAT 0X03
#define DA9052_ADC_MAN_MUXSEL_AD4 0X04
#define DA9052_ADC_MAN_MUXSEL_AD5 0X05
#define DA9052_ADC_MAN_MUXSEL_AD6 0X06
#define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09
/* ADC CONTROL REGSISTERS BITS */
#define DA9052_ADCCONT_COMP1V2EN 0X80
#define DA9052_ADCCONT_ADCMODE 0X40
#define DA9052_ADCCONT_TBATISRCEN 0X20
#define DA9052_ADCCONT_AD4ISRCEN 0X10
#define DA9052_ADCCONT_AUTOAD6EN 0X08
#define DA9052_ADCCONT_AUTOAD5EN 0X04
#define DA9052_ADCCONT_AUTOAD4EN 0X02
#define DA9052_ADCCONT_AUTOVDDEN 0X01
/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
#define DA9052_ADC_RES_LSB 0X03
/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
#define DA9052_ADCRESH_ADCRESMSB 0XFF
/* VDD RES REGSISTER BIT*/
#define DA9052_VDDRES_VDDOUTRES 0XFF
/* VDD MON REGSISTER BIT */
#define DA9052_VDDMON_VDDOUTMON 0XFF
/* ICHG_AV REGSISTER BIT */
#define DA9052_ICHGAV_ICHGAV 0XFF
/* ICHG_THD REGSISTER BIT */
#define DA9052_ICHGTHD_ICHGTHD 0XFF
/* ICHG_END REGSISTER BIT */
#define DA9052_ICHGEND_ICHGEND 0XFF
/* TBAT_RES REGSISTER BIT */
#define DA9052_TBATRES_TBATRES 0XFF
/* TBAT_HIGHP REGSISTER BIT */
#define DA9052_TBATHIGHP_TBATHIGHP 0XFF
/* TBAT_HIGHN REGSISTER BIT */
#define DA9052_TBATHIGHN_TBATHIGHN 0XFF
/* TBAT_LOW REGSISTER BIT */
#define DA9052_TBATLOW_TBATLOW 0XFF
/* T_OFFSET REGSISTER BIT */
#define DA9052_TOFFSET_TOFFSET 0XFF
/* ADCIN4_RES REGSISTER BIT */
#define DA9052_ADCIN4RES_ADCIN4RES 0XFF
/* ADCIN4_HIGH REGSISTER BIT */
#define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF
/* ADCIN4_LOW REGSISTER BIT */
#define DA9052_AUTO4LOW_AUTO4LOW 0XFF
/* ADCIN5_RES REGSISTER BIT */
#define DA9052_ADCIN5RES_ADCIN5RES 0XFF
/* ADCIN5_HIGH REGSISTER BIT */
#define DA9052_AUTO5HIGH_AUTOHIGH 0XFF
/* ADCIN5_LOW REGSISTER BIT */
#define DA9052_AUTO5LOW_AUTO5LOW 0XFF
/* ADCIN6_RES REGSISTER BIT */
#define DA9052_ADCIN6RES_ADCIN6RES 0XFF
/* ADCIN6_HIGH REGSISTER BIT */
#define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF
/* ADCIN6_LOW REGSISTER BIT */
#define DA9052_AUTO6LOW_AUTO6LOW 0XFF
/* TJUNC_RES REGSISTER BIT*/
#define DA9052_TJUNCRES_TJUNCRES 0XFF
/* TSI REGISTER */
/* TSI CONTROL REGISTER A BITS */
#define DA9052_TSICONTA_TSIDELAY 0XC0
#define DA9052_TSICONTA_TSISKIP 0X38
#define DA9052_TSICONTA_TSIMODE 0X04
#define DA9052_TSICONTA_PENDETEN 0X02
#define DA9052_TSICONTA_AUTOTSIEN 0X01
/* TSI CONTROL REGISTER B BITS */
#define DA9052_TSICONTB_ADCREF 0X80
#define DA9052_TSICONTB_TSIMAN 0X40
#define DA9052_TSICONTB_TSIMUX 0X30
#define DA9052_TSICONTB_TSISEL3 0X08
#define DA9052_TSICONTB_TSISEL2 0X04
#define DA9052_TSICONTB_TSISEL1 0X02
#define DA9052_TSICONTB_TSISEL0 0X01
/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIXMSB_TSIXM 0XFF
/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIYMSB_TSIYM 0XFF
/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
#define DA9052_TSILSB_PENDOWN 0X40
#define DA9052_TSILSB_TSIZL 0X30
#define DA9052_TSILSB_TSIYL 0X0C
#define DA9052_TSILSB_TSIXL 0X03
/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
#define DA9052_TSIZMSB_TSIZM 0XFF
/* RTC REGISTER */
/* RTC TIMER SECONDS REGISTER BITS */
#define DA9052_COUNTS_MONITOR 0X40
#define DA9052_RTC_SEC 0X3F
/* RTC TIMER MINUTES REGISTER BIT */
#define DA9052_RTC_MIN 0X3F
/* RTC TIMER HOUR REGISTER BIT */
#define DA9052_RTC_HOUR 0X1F
/* RTC TIMER DAYS REGISTER BIT */
#define DA9052_RTC_DAY 0X1F
/* RTC TIMER MONTHS REGISTER BIT */
#define DA9052_RTC_MONTH 0X0F
/* RTC TIMER YEARS REGISTER BIT */
#define DA9052_RTC_YEAR 0X3F
/* RTC ALARM MINUTES REGISTER BITS */
#define DA9052_ALARMM_I_TICK_TYPE 0X80
#define DA9052_ALARMMI_ALARMTYPE 0X40
/* RTC ALARM YEARS REGISTER BITS */
#define DA9052_ALARM_Y_TICK_ON 0X80
#define DA9052_ALARM_Y_ALARM_ON 0X40
/* RTC SECONDS REGISTER A BITS */
#define DA9052_SECONDA_SECONDSA 0XFF
/* RTC SECONDS REGISTER B BITS */
#define DA9052_SECONDB_SECONDSB 0XFF
/* RTC SECONDS REGISTER C BITS */
#define DA9052_SECONDC_SECONDSC 0XFF
/* RTC SECONDS REGISTER D BITS */
#define DA9052_SECONDD_SECONDSD 0XFF
#endif
/* __LINUX_MFD_DA9052_REG_H */

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/*
* da9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __DA9055_CORE_H
#define __DA9055_CORE_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
/*
* PMIC IRQ
*/
#define DA9055_IRQ_ALARM 0x01
#define DA9055_IRQ_TICK 0x02
#define DA9055_IRQ_NONKEY 0x00
#define DA9055_IRQ_REGULATOR 0x0B
#define DA9055_IRQ_HWMON 0x03
struct da9055_pdata;
struct da9055 {
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
struct device *dev;
struct i2c_client *i2c_client;
int irq_base;
int chip_irq;
};
/* Device I/O */
static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9055->regmap, reg, &val);
if (ret < 0)
return ret;
return val;
}
static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
unsigned char val)
{
return regmap_write(da9055->regmap, reg, val);
}
static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
}
/* Generic Device API */
int da9055_device_init(struct da9055 *da9055);
void da9055_device_exit(struct da9055 *da9055);
extern struct regmap_config da9055_regmap_config;
#endif /* __DA9055_CORE_H */

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/* Copyright (C) 2012 Dialog Semiconductor Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __DA9055_PDATA_H
#define __DA9055_PDATA_H
#define DA9055_MAX_REGULATORS 8
struct da9055;
enum gpio_select {
NO_GPIO = 0,
GPIO_1,
GPIO_2
};
struct da9055_pdata {
int (*init) (struct da9055 *da9055);
int irq_base;
int gpio_base;
struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
/* Enable RTC in RESET Mode */
bool reset_enable;
/*
* GPI muxed pin to control
* regulator state A/B, 0 if not available.
*/
int *gpio_ren;
/*
* GPI muxed pin to control
* regulator set, 0 if not available.
*/
int *gpio_rsel;
/*
* Regulator mode control bits value (GPI offset) that
* that controls the regulator state, 0 if not available.
*/
enum gpio_select *reg_ren;
/*
* Regulator mode control bits value (GPI offset) that
* controls the regulator set A/B, 0 if not available.
*/
enum gpio_select *reg_rsel;
/* GPIOs to enable regulator, 0 if not available */
int *ena_gpio;
};
#endif /* __DA9055_PDATA_H */

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/*
* DA9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __DA9055_REG_H
#define __DA9055_REG_H
/*
* PMIC registers
*/
/* PAGE0 */
#define DA9055_REG_PAGE_CON 0x00
/* System Control and Event Registers */
#define DA9055_REG_STATUS_A 0x01
#define DA9055_REG_STATUS_B 0x02
#define DA9055_REG_FAULT_LOG 0x03
#define DA9055_REG_EVENT_A 0x04
#define DA9055_REG_EVENT_B 0x05
#define DA9055_REG_EVENT_C 0x06
#define DA9055_REG_IRQ_MASK_A 0x07
#define DA9055_REG_IRQ_MASK_B 0x08
#define DA9055_REG_IRQ_MASK_C 0x09
#define DA9055_REG_CONTROL_A 0x0A
#define DA9055_REG_CONTROL_B 0x0B
#define DA9055_REG_CONTROL_C 0x0C
#define DA9055_REG_CONTROL_D 0x0D
#define DA9055_REG_CONTROL_E 0x0E
#define DA9055_REG_PD_DIS 0x0F
/* GPIO Control Registers */
#define DA9055_REG_GPIO0_1 0x10
#define DA9055_REG_GPIO2 0x11
#define DA9055_REG_GPIO_MODE0_2 0x12
/* Regulator Control Registers */
#define DA9055_REG_BCORE_CONT 0x13
#define DA9055_REG_BMEM_CONT 0x14
#define DA9055_REG_LDO1_CONT 0x15
#define DA9055_REG_LDO2_CONT 0x16
#define DA9055_REG_LDO3_CONT 0x17
#define DA9055_REG_LDO4_CONT 0x18
#define DA9055_REG_LDO5_CONT 0x19
#define DA9055_REG_LDO6_CONT 0x1A
/* GP-ADC Control Registers */
#define DA9055_REG_ADC_MAN 0x1B
#define DA9055_REG_ADC_CONT 0x1C
#define DA9055_REG_VSYS_MON 0x1D
#define DA9055_REG_ADC_RES_L 0x1E
#define DA9055_REG_ADC_RES_H 0x1F
#define DA9055_REG_VSYS_RES 0x20
#define DA9055_REG_ADCIN1_RES 0x21
#define DA9055_REG_ADCIN2_RES 0x22
#define DA9055_REG_ADCIN3_RES 0x23
/* Sequencer Control Registers */
#define DA9055_REG_EN_32K 0x35
/* Regulator Setting Registers */
#define DA9055_REG_BUCK_LIM 0x37
#define DA9055_REG_BCORE_MODE 0x38
#define DA9055_REG_VBCORE_A 0x39
#define DA9055_REG_VBMEM_A 0x3A
#define DA9055_REG_VLDO1_A 0x3B
#define DA9055_REG_VLDO2_A 0x3C
#define DA9055_REG_VLDO3_A 0x3D
#define DA9055_REG_VLDO4_A 0x3E
#define DA9055_REG_VLDO5_A 0x3F
#define DA9055_REG_VLDO6_A 0x40
#define DA9055_REG_VBCORE_B 0x41
#define DA9055_REG_VBMEM_B 0x42
#define DA9055_REG_VLDO1_B 0x43
#define DA9055_REG_VLDO2_B 0x44
#define DA9055_REG_VLDO3_B 0x45
#define DA9055_REG_VLDO4_B 0x46
#define DA9055_REG_VLDO5_B 0x47
#define DA9055_REG_VLDO6_B 0x48
/* GP-ADC Threshold Registers */
#define DA9055_REG_AUTO1_HIGH 0x49
#define DA9055_REG_AUTO1_LOW 0x4A
#define DA9055_REG_AUTO2_HIGH 0x4B
#define DA9055_REG_AUTO2_LOW 0x4C
#define DA9055_REG_AUTO3_HIGH 0x4D
#define DA9055_REG_AUTO3_LOW 0x4E
/* OTP */
#define DA9055_REG_OPT_COUNT 0x50
#define DA9055_REG_OPT_ADDR 0x51
#define DA9055_REG_OPT_DATA 0x52
/* RTC Calendar and Alarm Registers */
#define DA9055_REG_COUNT_S 0x53
#define DA9055_REG_COUNT_MI 0x54
#define DA9055_REG_COUNT_H 0x55
#define DA9055_REG_COUNT_D 0x56
#define DA9055_REG_COUNT_MO 0x57
#define DA9055_REG_COUNT_Y 0x58
#define DA9055_REG_ALARM_MI 0x59
#define DA9055_REG_ALARM_H 0x5A
#define DA9055_REG_ALARM_D 0x5B
#define DA9055_REG_ALARM_MO 0x5C
#define DA9055_REG_ALARM_Y 0x5D
#define DA9055_REG_SECOND_A 0x5E
#define DA9055_REG_SECOND_B 0x5F
#define DA9055_REG_SECOND_C 0x60
#define DA9055_REG_SECOND_D 0x61
/* Customer Trim and Configuration */
#define DA9055_REG_T_OFFSET 0x63
#define DA9055_REG_INTERFACE 0x64
#define DA9055_REG_CONFIG_A 0x65
#define DA9055_REG_CONFIG_B 0x66
#define DA9055_REG_CONFIG_C 0x67
#define DA9055_REG_CONFIG_D 0x68
#define DA9055_REG_CONFIG_E 0x69
#define DA9055_REG_TRIM_CLDR 0x6F
/* General Purpose Registers */
#define DA9055_REG_GP_ID_0 0x70
#define DA9055_REG_GP_ID_1 0x71
#define DA9055_REG_GP_ID_2 0x72
#define DA9055_REG_GP_ID_3 0x73
#define DA9055_REG_GP_ID_4 0x74
#define DA9055_REG_GP_ID_5 0x75
#define DA9055_REG_GP_ID_6 0x76
#define DA9055_REG_GP_ID_7 0x77
#define DA9055_REG_GP_ID_8 0x78
#define DA9055_REG_GP_ID_9 0x79
#define DA9055_REG_GP_ID_10 0x7A
#define DA9055_REG_GP_ID_11 0x7B
#define DA9055_REG_GP_ID_12 0x7C
#define DA9055_REG_GP_ID_13 0x7D
#define DA9055_REG_GP_ID_14 0x7E
#define DA9055_REG_GP_ID_15 0x7F
#define DA9055_REG_GP_ID_16 0x80
#define DA9055_REG_GP_ID_17 0x81
#define DA9055_REG_GP_ID_18 0x82
#define DA9055_REG_GP_ID_19 0x83
#define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19
/*
* PMIC registers bits
*/
/* DA9055_REG_PAGE_CON (addr=0x00) */
#define DA9055_PAGE_WRITE_MODE (0<<6)
#define DA9055_REPEAT_WRITE_MODE (1<<6)
/* DA9055_REG_STATUS_A (addr=0x01) */
#define DA9055_NOKEY_STS 0x01
#define DA9055_WAKE_STS 0x02
#define DA9055_DVC_BUSY_STS 0x04
#define DA9055_COMP1V2_STS 0x08
#define DA9055_NJIG_STS 0x10
#define DA9055_LDO5_LIM_STS 0x20
#define DA9055_LDO6_LIM_STS 0x40
/* DA9055_REG_STATUS_B (addr=0x02) */
#define DA9055_GPI0_STS 0x01
#define DA9055_GPI1_STS 0x02
#define DA9055_GPI2_STS 0x04
/* DA9055_REG_FAULT_LOG (addr=0x03) */
#define DA9055_TWD_ERROR_FLG 0x01
#define DA9055_POR_FLG 0x02
#define DA9055_VDD_FAULT_FLG 0x04
#define DA9055_VDD_START_FLG 0x08
#define DA9055_TEMP_CRIT_FLG 0x10
#define DA9055_KEY_RESET_FLG 0x20
#define DA9055_WAIT_SHUT_FLG 0x80
/* DA9055_REG_EVENT_A (addr=0x04) */
#define DA9055_NOKEY_EINT 0x01
#define DA9055_ALARM_EINT 0x02
#define DA9055_TICK_EINT 0x04
#define DA9055_ADC_RDY_EINT 0x08
#define DA9055_SEQ_RDY_EINT 0x10
#define DA9055_EVENTS_B_EINT 0x20
#define DA9055_EVENTS_C_EINT 0x40
/* DA9055_REG_EVENT_B (addr=0x05) */
#define DA9055_E_WAKE_EINT 0x01
#define DA9055_E_TEMP_EINT 0x02
#define DA9055_E_COMP1V2_EINT 0x04
#define DA9055_E_LDO_LIM_EINT 0x08
#define DA9055_E_NJIG_EINT 0x20
#define DA9055_E_VDD_MON_EINT 0x40
#define DA9055_E_VDD_WARN_EINT 0x80
/* DA9055_REG_EVENT_C (addr=0x06) */
#define DA9055_E_GPI0_EINT 0x01
#define DA9055_E_GPI1_EINT 0x02
#define DA9055_E_GPI2_EINT 0x04
/* DA9055_REG_IRQ_MASK_A (addr=0x07) */
#define DA9055_M_NONKEY_EINT 0x01
#define DA9055_M_ALARM_EINT 0x02
#define DA9055_M_TICK_EINT 0x04
#define DA9055_M_ADC_RDY_EINT 0x08
#define DA9055_M_SEQ_RDY_EINT 0x10
/* DA9055_REG_IRQ_MASK_B (addr=0x08) */
#define DA9055_M_WAKE_EINT 0x01
#define DA9055_M_TEMP_EINT 0x02
#define DA9055_M_COMP_1V2_EINT 0x04
#define DA9055_M_LDO_LIM_EINT 0x08
#define DA9055_M_NJIG_EINT 0x20
#define DA9055_M_VDD_MON_EINT 0x40
#define DA9055_M_VDD_WARN_EINT 0x80
/* DA9055_REG_IRQ_MASK_C (addr=0x09) */
#define DA9055_M_GPI0_EINT 0x01
#define DA9055_M_GPI1_EINT 0x02
#define DA9055_M_GPI2_EINT 0x04
/* DA9055_REG_CONTROL_A (addr=0xA) */
#define DA9055_DEBOUNCING_SHIFT 0x00
#define DA9055_DEBOUNCING_MASK 0x07
#define DA9055_NRES_MODE_SHIFT 0x03
#define DA9055_NRES_MODE_MASK 0x08
#define DA9055_SLEW_RATE_SHIFT 0x04
#define DA9055_SLEW_RATE_MASK 0x30
#define DA9055_NOKEY_LOCK_SHIFT 0x06
#define DA9055_NOKEY_LOCK_MASK 0x40
/* DA9055_REG_CONTROL_B (addr=0xB) */
#define DA9055_RTC_MODE_PD 0x01
#define DA9055_RTC_MODE_SD_SHIFT 0x01
#define DA9055_RTC_MODE_SD 0x02
#define DA9055_RTC_EN 0x04
#define DA9055_ECO_MODE_SHIFT 0x03
#define DA9055_ECO_MODE_MASK 0x08
#define DA9055_TWDSCALE_SHIFT 4
#define DA9055_TWDSCALE_MASK 0x70
#define DA9055_V_LOCK_SHIFT 0x07
#define DA9055_V_LOCK_MASK 0x80
/* DA9055_REG_CONTROL_C (addr=0xC) */
#define DA9055_SYSTEM_EN_SHIFT 0x00
#define DA9055_SYSTEM_EN_MASK 0x01
#define DA9055_POWERN_EN_SHIFT 0x01
#define DA9055_POWERN_EN_MASK 0x02
#define DA9055_POWER1_EN_SHIFT 0x02
#define DA9055_POWER1_EN_MASK 0x04
/* DA9055_REG_CONTROL_D (addr=0xD) */
#define DA9055_STANDBY_SHIFT 0x02
#define DA9055_STANDBY_MASK 0x08
#define DA9055_AUTO_BOOT_SHIFT 0x03
#define DA9055_AUTO_BOOT_MASK 0x04
/* DA9055_REG_CONTROL_E (addr=0xE) */
#define DA9055_WATCHDOG_SHIFT 0x00
#define DA9055_WATCHDOG_MASK 0x01
#define DA9055_SHUTDOWN_SHIFT 0x01
#define DA9055_SHUTDOWN_MASK 0x02
#define DA9055_WAKE_UP_SHIFT 0x02
#define DA9055_WAKE_UP_MASK 0x04
/* DA9055_REG_GPIO (addr=0x10/0x11) */
#define DA9055_GPIO0_PIN_SHIFT 0x00
#define DA9055_GPIO0_PIN_MASK 0x03
#define DA9055_GPIO0_TYPE_SHIFT 0x02
#define DA9055_GPIO0_TYPE_MASK 0x04
#define DA9055_GPIO0_WEN_SHIFT 0x03
#define DA9055_GPIO0_WEN_MASK 0x08
#define DA9055_GPIO1_PIN_SHIFT 0x04
#define DA9055_GPIO1_PIN_MASK 0x30
#define DA9055_GPIO1_TYPE_SHIFT 0x06
#define DA9055_GPIO1_TYPE_MASK 0x40
#define DA9055_GPIO1_WEN_SHIFT 0x07
#define DA9055_GPIO1_WEN_MASK 0x80
#define DA9055_GPIO2_PIN_SHIFT 0x00
#define DA9055_GPIO2_PIN_MASK 0x30
#define DA9055_GPIO2_TYPE_SHIFT 0x02
#define DA9055_GPIO2_TYPE_MASK 0x04
#define DA9055_GPIO2_WEN_SHIFT 0x03
#define DA9055_GPIO2_WEN_MASK 0x08
/* DA9055_REG_GPIO_MODE (addr=0x12) */
#define DA9055_GPIO0_MODE_SHIFT 0x00
#define DA9055_GPIO0_MODE_MASK 0x01
#define DA9055_GPIO1_MODE_SHIFT 0x01
#define DA9055_GPIO1_MODE_MASK 0x02
#define DA9055_GPIO2_MODE_SHIFT 0x02
#define DA9055_GPIO2_MODE_MASK 0x04
/* DA9055_REG_BCORE_CONT (addr=0x13) */
#define DA9055_BCORE_EN_SHIFT 0x00
#define DA9055_BCORE_EN_MASK 0x01
#define DA9055_BCORE_GPI_SHIFT 0x01
#define DA9055_BCORE_GPI_MASK 0x02
#define DA9055_BCORE_PD_DIS_SHIFT 0x03
#define DA9055_BCORE_PD_DIS_MASK 0x04
#define DA9055_VBCORE_SEL_SHIFT 0x04
#define DA9055_SEL_REG_A 0x0
#define DA9055_SEL_REG_B 0x10
#define DA9055_VBCORE_SEL_MASK 0x10
#define DA9055_V_GPI_MASK 0x60
#define DA9055_V_GPI_SHIFT 0x05
#define DA9055_E_GPI_MASK 0x06
#define DA9055_E_GPI_SHIFT 0x01
#define DA9055_VBCORE_GPI_SHIFT 0x05
#define DA9055_VBCORE_GPI_MASK 0x60
#define DA9055_BCORE_CONF_SHIFT 0x07
#define DA9055_BCORE_CONF_MASK 0x80
/* DA9055_REG_BMEM_CONT (addr=0x14) */
#define DA9055_BMEM_EN_SHIFT 0x00
#define DA9055_BMEM_EN_MASK 0x01
#define DA9055_BMEM_GPI_SHIFT 0x01
#define DA9055_BMEM_GPI_MASK 0x06
#define DA9055_BMEM_PD_DIS_SHIFT 0x03
#define DA9055_BMEM_PD_DIS_MASK 0x08
#define DA9055_VBMEM_SEL_SHIT 0x04
#define DA9055_VBMEM_SEL_VBMEM_A (0<<4)
#define DA9055_VBMEM_SEL_VBMEM_B (1<<4)
#define DA9055_VBMEM_SEL_MASK 0x10
#define DA9055_VBMEM_GPI_SHIFT 0x05
#define DA9055_VBMEM_GPI_MASK 0x60
#define DA9055_BMEM_CONF_SHIFT 0x07
#define DA9055_BMEM_CONF_MASK 0x80
/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
#define DA9055_LDO_EN_SHIFT 0x00
#define DA9055_LDO_EN_MASK 0x01
#define DA9055_LDO_GPI_SHIFT 0x01
#define DA9055_LDO_GPI_MASK 0x06
#define DA9055_LDO_PD_DIS_SHIFT 0x03
#define DA9055_LDO_PD_DIS_MASK 0x08
#define DA9055_VLDO_SEL_SHIFT 0x04
#define DA9055_VLDO_SEL_MASK 0x10
#define DA9055_VLDO_SEL_VLDO_A 0x00
#define DA9055_VLDO_SEL_VLDO_B 0x01
#define DA9055_VLDO_GPI_SHIFT 0x05
#define DA9055_VLDO_GPI_MASK 0x60
#define DA9055_LDO_CONF_SHIFT 0x07
#define DA9055_LDO_CONF_MASK 0x80
#define DA9055_REGUALTOR_SET_A 0x00
#define DA9055_REGUALTOR_SET_B 0x10
/* DA9055_REG_ADC_MAN (addr=0x1B) */
#define DA9055_ADC_MUX_SHIFT 0
#define DA9055_ADC_MUX_MASK 0xF
#define DA9055_ADC_MUX_VSYS 0x0
#define DA9055_ADC_MUX_ADCIN1 0x01
#define DA9055_ADC_MUX_ADCIN2 0x02
#define DA9055_ADC_MUX_ADCIN3 0x03
#define DA9055_ADC_MUX_T_SENSE 0x04
#define DA9055_ADC_MAN_SHIFT 0x04
#define DA9055_ADC_MAN_CONV 0x10
#define DA9055_ADC_LSB_MASK 0X03
#define DA9055_ADC_MODE_MASK 0x20
#define DA9055_ADC_MODE_SHIFT 5
#define DA9055_ADC_MODE_1MS (1<<5)
#define DA9055_COMP1V2_EN_SHIFT 7
/* DA9055_REG_ADC_CONT (addr=0x1C) */
#define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0
#define DA9055_ADC_AUTO_AD1_EN_SHIFT 1
#define DA9055_ADC_AUTO_AD2_EN_SHIFT 2
#define DA9055_ADC_AUTO_AD3_EN_SHIFT 3
#define DA9055_ADC_ISRC_EN_SHIFT 4
#define DA9055_ADC_ADCIN1_DEB_SHIFT 5
#define DA9055_ADC_ADCIN2_DEB_SHIFT 6
#define DA9055_ADC_ADCIN3_DEB_SHIFT 7
#define DA9055_AD1_ISRC_MASK 0x10
#define DA9055_AD1_ISRC_SHIFT 4
/* DA9055_REG_VSYS_MON (addr=0x1D) */
#define DA9055_VSYS_VAL_SHIFT 0
#define DA9055_VSYS_VAL_MASK 0xFF
#define DA9055_VSYS_VAL_BASE 0x00
#define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK
#define DA9055_VSYS_VOLT_BASE 2500
#define DA9055_VSYS_VOLT_INC 10
#define DA9055_VSYS_STEPS 255
#define DA9055_VSYS_VOLT_MIN 2500
/* DA9044_REG_XXX_RES (addr=0x20-0x23) */
#define DA9055_ADC_VAL_SHIFT 0
#define DA9055_ADC_VAL_MASK 0xFF
#define DA9055_ADC_VAL_BASE 0x00
#define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK
#define DA9055_ADC_VOLT_BASE 0
#define DA9055_ADC_VSYS_VOLT_BASE 2500
#define DA9055_ADC_VOLT_INC 10
#define DA9055_ADC_VSYS_VOLT_INC 12
#define DA9055_ADC_STEPS 255
/* DA9055_REG_EN_32K (addr=0x35)*/
#define DA9055_STARTUP_TIME_MASK 0x07
#define DA9055_STARTUP_TIME_0S 0x0
#define DA9055_STARTUP_TIME_0_52S 0x1
#define DA9055_STARTUP_TIME_1S 0x2
#define DA9055_CRYSTAL_EN 0x08
#define DA9055_DELAY_MODE_EN 0x10
#define DA9055_OUT_CLCK_GATED 0x20
#define DA9055_RTC_CLOCK_GATED 0x40
#define DA9055_EN_32KOUT_BUF 0x80
/* DA9055_REG_RESET (addr=0x36) */
/* Timer up to 31.744 ms */
#define DA9055_RESET_TIMER_VAL_SHIFT 0
#define DA9055_RESET_LOW_VAL_MASK 0x3F
#define DA9055_RESET_LOW_VAL_BASE 0
#define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK
#define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */
#define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */
#define DA9055_RESET_US_LOW_STEP 30
/* Timer up to 1048.576ms */
#define DA9055_RESET_HIGH_VAL_MASK 0x3F
#define DA9055_RESET_HIGH_VAL_BASE 0
#define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK
#define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */
#define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */
#define DA9055_RESET_US_HIGH_STEP 31
/* DA9055_REG_BUCK_ILIM (addr=0x37)*/
#define DA9055_BMEM_ILIM_SHIFT 0
#define DA9055_ILIM_MASK 0x3
#define DA9055_ILIM_500MA 0x0
#define DA9055_ILIM_600MA 0x1
#define DA9055_ILIM_700MA 0x2
#define DA9055_ILIM_800MA 0x3
#define DA9055_BCORE_ILIM_SHIFT 2
/* DA9055_REG_BCORE_MODE (addr=0x38) */
#define DA9055_BMEM_MODE_SHIFT 0
#define DA9055_MODE_MASK 0x3
#define DA9055_MODE_AB 0x0
#define DA9055_MODE_SLEEP 0x1
#define DA9055_MODE_SYNCHRO 0x2
#define DA9055_MODE_AUTO 0x3
#define DA9055_BCORE_MODE_SHIFT 2
/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
#define DA9055_VBCORE_VAL_SHIFT 0
#define DA9055_VBCORE_VAL_MASK 0x3F
#define DA9055_VBCORE_VAL_BASE 0x09
#define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK
#define DA9055_VBCORE_VOLT_BASE 750
#define DA9055_VBCORE_VOLT_INC 25
#define DA9055_VBCORE_STEPS 53
#define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE
#define DA9055_BCORE_SL_SYNCHRO (0<<7)
#define DA9055_BCORE_SL_SLEEP (1<<7)
/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
#define DA9055_VBMEM_VAL_SHIFT 0
#define DA9055_VBMEM_VAL_MASK 0x3F
#define DA9055_VBMEM_VAL_BASE 0x00
#define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK
#define DA9055_VBMEM_VOLT_BASE 925
#define DA9055_VBMEM_VOLT_INC 25
#define DA9055_VBMEM_STEPS 63
#define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE
#define DA9055_BCMEM_SL_SYNCHRO (0<<7)
#define DA9055_BCMEM_SL_SLEEP (1<<7)
/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
#define DA9055_VLDO_VAL_SHIFT 0
#define DA9055_VLDO_VAL_MASK 0x3F
#define DA9055_VLDO6_VAL_MASK 0x7F
#define DA9055_VLDO_VAL_BASE 0x02
#define DA9055_VLDO2_VAL_BASE 0x03
#define DA9055_VLDO6_VAL_BASE 0x00
#define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK
#define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK
#define DA9055_VLDO_VOLT_BASE 900
#define DA9055_VLDO_VOLT_INC 50
#define DA9055_VLDO6_VOLT_INC 20
#define DA9055_VLDO_STEPS 48
#define DA9055_VLDO5_STEPS 37
#define DA9055_VLDO6_STEPS 120
#define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE
#define DA9055_LDO_MODE_SHIFT 7
#define DA9055_LDO_SL_NORMAL 0
#define DA9055_LDO_SL_SLEEP 1
/* DA9055_REG_OTP_CONT (addr=0x50) */
#define DA9055_OTP_TIM_NORMAL (0<<0)
#define DA9055_OTP_TIM_MARGINAL (1<<0)
#define DA9055_OTP_GP_RD_SHIFT 1
#define DA9055_OTP_APPS_RD_SHIFT 2
#define DA9055_PC_DONE_SHIFT 3
#define DA9055_OTP_GP_LOCK_SHIFT 4
#define DA9055_OTP_APPS_LOCK_SHIFT 5
#define DA9055_OTP_CONF_LOCK_SHIFT 6
#define DA9055_OTP_WRITE_DIS_SHIFT 7
/* DA9055_REG_COUNT_S (addr=0x53) */
#define DA9055_RTC_SEC 0x3F
#define DA9055_RTC_MONITOR_EN 0x40
#define DA9055_RTC_READ 0x80
/* DA9055_REG_COUNT_MI (addr=0x54) */
#define DA9055_RTC_MIN 0x3F
/* DA9055_REG_COUNT_H (addr=0x55) */
#define DA9055_RTC_HOUR 0x1F
/* DA9055_REG_COUNT_D (addr=0x56) */
#define DA9055_RTC_DAY 0x1F
/* DA9055_REG_COUNT_MO (addr=0x57) */
#define DA9055_RTC_MONTH 0x0F
/* DA9055_REG_COUNT_Y (addr=0x58) */
#define DA9055_RTC_YEAR 0x3F
#define DA9055_RTC_YEAR_BASE 2000
/* DA9055_REG_ALARM_MI (addr=0x59) */
#define DA9055_RTC_ALM_MIN 0x3F
#define DA9055_ALARM_STATUS_SHIFT 6
#define DA9055_ALARM_STATUS_MASK 0x3
#define DA9055_ALARM_STATUS_NO_ALARM 0x0
#define DA9055_ALARM_STATUS_TICK 0x1
#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
#define DA9055_ALARM_STATUS_BOTH 0x3
/* DA9055_REG_ALARM_H (addr=0x5A) */
#define DA9055_RTC_ALM_HOUR 0x1F
/* DA9055_REG_ALARM_D (addr=0x5B) */
#define DA9055_RTC_ALM_DAY 0x1F
/* DA9055_REG_ALARM_MO (addr=0x5C) */
#define DA9055_RTC_ALM_MONTH 0x0F
#define DA9055_RTC_TICK_WAKE_MASK 0x20
#define DA9055_RTC_TICK_WAKE_SHIFT 5
#define DA9055_RTC_TICK_TYPE 0x10
#define DA9055_RTC_TICK_TYPE_SHIFT 0x4
#define DA9055_RTC_TICK_SEC 0x0
#define DA9055_RTC_TICK_MIN 0x1
#define DA9055_ALARAM_TICK_WAKE 0x20
/* DA9055_REG_ALARM_Y (addr=0x5D) */
#define DA9055_RTC_TICK_EN 0x80
#define DA9055_RTC_ALM_EN 0x40
#define DA9055_RTC_TICK_ALM_MASK 0xC0
#define DA9055_RTC_ALM_YEAR 0x3F
/* DA9055_REG_TRIM_CLDR (addr=0x62) */
#define DA9055_TRIM_32K_SHIFT 0
#define DA9055_TRIM_32K_MASK 0x7F
#define DA9055_TRIM_DECREMENT (1<<7)
#define DA9055_TRIM_INCREMENT (0<<7)
#define DA9055_TRIM_VAL_BASE 0x0
#define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */
#define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */
#define DA9055_TRIM_STEPS 127
/* DA9055_REG_CONFIG_A (addr=0x65) */
#define DA9055_PM_I_V_VDDCORE (0<<0)
#define DA9055_PM_I_V_VDD_IO (1<<0)
#define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1)
#define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1)
#define DA9055_PM_O_TYPE_PUSH_PULL (0<<2)
#define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2)
#define DA9055_IRQ_TYPE_ACT_LOW (0<<3)
#define DA9055_IRQ_TYPE_ACT_HIGH (1<<3)
#define DA9055_NIRQ_MODE_IMM (0<<4)
#define DA9055_NIRQ_MODE_ACTIVE (1<<4)
#define DA9055_GPI_V_VDDCORE (0<<5)
#define DA9055_GPI_V_VDD_IO (1<<5)
#define DA9055_PM_IF_V_VDDCORE (0<<6)
#define DA9055_PM_IF_V_VDD_IO (1<<6)
/* DA9055_REG_CONFIG_B (addr=0x66) */
#define DA9055_VDD_FAULT_VAL_SHIFT 0
#define DA9055_VDD_FAULT_VAL_MASK 0xF
#define DA9055_VDD_FAULT_VAL_BASE 0x0
#define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK
#define DA9055_VDD_FAULT_VOLT_BASE 2500
#define DA9055_VDD_FAULT_VOLT_INC 50
#define DA9055_VDD_FAULT_STEPS 15
#define DA9055_VDD_HYST_VAL_SHIFT 4
#define DA9055_VDD_HYST_VAL_MASK 0x7
#define DA9055_VDD_HYST_VAL_BASE 0x0
#define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK
#define DA9055_VDD_HYST_VOLT_BASE 100
#define DA9055_VDD_HYST_VOLT_INC 50
#define DA9055_VDD_HYST_STEPS 7
#define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE
#define DA9055_VDD_FAULT_EN_SHIFT 7
/* DA9055_REG_CONFIG_C (addr=0x67) */
#define DA9055_BCORE_CLK_INV_SHIFT 0
#define DA9055_BMEM_CLK_INV_SHIFT 1
#define DA9055_NFAULT_CONF_SHIFT 2
#define DA9055_LDO_SD_SHIFT 4
#define DA9055_LDO5_BYP_SHIFT 6
#define DA9055_LDO6_BYP_SHIFT 7
/* DA9055_REG_CONFIG_D (addr=0x68) */
#define DA9055_NONKEY_PIN_SHIFT 0
#define DA9055_NONKEY_PIN_MASK 0x3
#define DA9055_NONKEY_PIN_PORT_MODE 0x0
#define DA9055_NONKEY_PIN_KEY_MODE 0x1
#define DA9055_NONKEY_PIN_MULTI_FUNC 0x2
#define DA9055_NONKEY_PIN_DEDICT 0x3
#define DA9055_NONKEY_SD_SHIFT 2
#define DA9055_KEY_DELAY_SHIFT 3
#define DA9055_KEY_DELAY_MASK 0x3
#define DA9055_KEY_DELAY_4S 0x0
#define DA9055_KEY_DELAY_6S 0x1
#define DA9055_KEY_DELAY_8S 0x2
#define DA9055_KEY_DELAY_10S 0x3
/* DA9055_REG_CONFIG_E (addr=0x69) */
#define DA9055_GPIO_PUPD_PULL_UP 0x0
#define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1
#define DA9055_GPIO0_PUPD_SHIFT 0
#define DA9055_GPIO1_PUPD_SHIFT 1
#define DA9055_GPIO2_PUPD_SHIFT 2
#define DA9055_UVOV_DELAY_SHIFT 4
#define DA9055_UVOV_DELAY_MASK 0x3
#define DA9055_RESET_DURATION_SHIFT 6
#define DA9055_RESET_DURATION_MASK 0x3
#define DA9055_RESET_DURATION_0MS 0x0
#define DA9055_RESET_DURATION_100MS 0x1
#define DA9055_RESET_DURATION_500MS 0x2
#define DA9055_RESET_DURATION_1000MS 0x3
/* DA9055_REG_MON_REG_1 (addr=0x6A) */
#define DA9055_MON_THRES_SHIFT 0
#define DA9055_MON_THRES_MASK 0x3
#define DA9055_MON_RES_SHIFT 2
#define DA9055_MON_DEB_SHIFT 3
#define DA9055_MON_MODE_SHIFT 4
#define DA9055_MON_MODE_MASK 0x3
#define DA9055_START_MAX_SHIFT 6
#define DA9055_START_MAX_MASK 0x3
/* DA9055_REG_MON_REG_2 (addr=0x6B) */
#define DA9055_LDO1_MON_EN_SHIFT 0
#define DA9055_LDO2_MON_EN_SHIFT 1
#define DA9055_LDO3_MON_EN_SHIFT 2
#define DA9055_LDO4_MON_EN_SHIFT 3
#define DA9055_LDO5_MON_EN_SHIFT 4
#define DA9055_LDO6_MON_EN_SHIFT 5
#define DA9055_BCORE_MON_EN_SHIFT 6
#define DA9055_BMEM_MON_EN_SHIFT 7
/* DA9055_REG_CONFIG_F (addr=0x6C) */
#define DA9055_LDO1_DEF_SHIFT 0
#define DA9055_LDO2_DEF_SHIFT 1
#define DA9055_LDO3_DEF_SHIFT 2
#define DA9055_LDO4_DEF_SHIFT 3
#define DA9055_LDO5_DEF_SHIFT 4
#define DA9055_LDO6_DEF_SHIFT 5
#define DA9055_BCORE_DEF_SHIFT 6
#define DA9055_BMEM_DEF_SHIFT 7
/* DA9055_REG_MON_REG_4 (addr=0x6D) */
#define DA9055_MON_A8_IDX_SHIFT 0
#define DA9055_MON_A89_IDX_MASK 0x3
#define DA9055_MON_A89_IDX_NONE 0x0
#define DA9055_MON_A89_IDX_BUCKCORE 0x1
#define DA9055_MON_A89_IDX_LDO3 0x2
#define DA9055_MON_A9_IDX_SHIFT 5
/* DA9055_REG_MON_REG_5 (addr=0x6E) */
#define DA9055_MON_A10_IDX_SHIFT 0
#define DA9055_MON_A10_IDX_MASK 0x3
#define DA9055_MON_A10_IDX_NONE 0x0
#define DA9055_MON_A10_IDX_LDO1 0x1
#define DA9055_MON_A10_IDX_LDO2 0x2
#define DA9055_MON_A10_IDX_LDO5 0x3
#define DA9055_MON_A10_IDX_LDO6 0x4
#endif /* __DA9055_REG_H */

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include/linux/mfd/davinci_voicecodec.h Normal file
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/*
* DaVinci Voice Codec Core Interface for TI platforms
*
* Copyright (C) 2010 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
#define __LINUX_MFD_DAVINIC_VOICECODEC_H_
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <mach/edma.h>
/*
* Register values.
*/
#define DAVINCI_VC_PID 0x00
#define DAVINCI_VC_CTRL 0x04
#define DAVINCI_VC_INTEN 0x08
#define DAVINCI_VC_INTSTATUS 0x0c
#define DAVINCI_VC_INTCLR 0x10
#define DAVINCI_VC_EMUL_CTRL 0x14
#define DAVINCI_VC_RFIFO 0x20
#define DAVINCI_VC_WFIFO 0x24
#define DAVINCI_VC_FIFOSTAT 0x28
#define DAVINCI_VC_TST_CTRL 0x2C
#define DAVINCI_VC_REG05 0x94
#define DAVINCI_VC_REG09 0xA4
#define DAVINCI_VC_REG12 0xB0
/* DAVINCI_VC_CTRL bit fields */
#define DAVINCI_VC_CTRL_MASK 0x5500
#define DAVINCI_VC_CTRL_RSTADC BIT(0)
#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
/* DAVINCI_VC_INT bit fields */
#define DAVINCI_VC_INT_MASK 0x3F
#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
/* DAVINCI_VC_REG05 bit fields */
#define DAVINCI_VC_REG05_PGA_GAIN 0x07
/* DAVINCI_VC_REG09 bit fields */
#define DAVINCI_VC_REG09_MUTE 0x40
#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
/* DAVINCI_VC_REG12 bit fields */
#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
#define DAVINCI_VC_CELLS 2
enum davinci_vc_cells {
DAVINCI_VC_VCIF_CELL,
DAVINCI_VC_CQ93VC_CELL,
};
struct davinci_vcif {
struct platform_device *pdev;
u32 dma_tx_channel;
u32 dma_rx_channel;
dma_addr_t dma_tx_addr;
dma_addr_t dma_rx_addr;
};
struct cq93vc {
struct platform_device *pdev;
struct snd_soc_codec *codec;
u32 sysclk;
};
struct davinci_vc;
struct davinci_vc {
/* Device data */
struct device *dev;
struct platform_device *pdev;
struct clk *clk;
/* Memory resources */
void __iomem *base;
resource_size_t pbase;
size_t base_size;
/* MFD cells */
struct mfd_cell cells[DAVINCI_VC_CELLS];
/* Client devices */
struct davinci_vcif davinci_vcif;
struct cq93vc cq93vc;
};
#endif

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include/linux/mfd/db8500-prcmu.h Normal file
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/*
* Copyright (C) STMicroelectronics 2009
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* PRCMU f/w APIs
*/
#ifndef __MFD_DB8500_PRCMU_H
#define __MFD_DB8500_PRCMU_H
#include <linux/interrupt.h>
#include <linux/bitops.h>
/*
* Registers
*/
#define DB8500_PRCM_LINE_VALUE 0x170
#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
#define DB8500_PRCM_DSI_SW_RESET 0x324
#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
/**
* enum state - ON/OFF state definition
* @OFF: State is ON
* @ON: State is OFF
*
*/
enum state {
OFF = 0x0,
ON = 0x1,
};
/**
* enum ret_state - general purpose On/Off/Retention states
*
*/
enum ret_state {
OFFST = 0,
ONST = 1,
RETST = 2
};
/**
* enum clk_arm - ARM Cortex A9 clock schemes
* @A9_OFF:
* @A9_BOOT:
* @A9_OPPT1:
* @A9_OPPT2:
* @A9_EXTCLK:
*/
enum clk_arm {
A9_OFF,
A9_BOOT,
A9_OPPT1,
A9_OPPT2,
A9_EXTCLK
};
/**
* enum clk_gen - GEN#0/GEN#1 clock schemes
* @GEN_OFF:
* @GEN_BOOT:
* @GEN_OPPT1:
*/
enum clk_gen {
GEN_OFF,
GEN_BOOT,
GEN_OPPT1,
};
/* some information between arm and xp70 */
/**
* enum romcode_write - Romcode message written by A9 AND read by XP70
* @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
* @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
* romcode. The xp70 will go into self-reset
*/
enum romcode_write {
RDY_2_DS = 0x09,
RDY_2_XP70_RST = 0x10
};
/**
* enum romcode_read - Romcode message written by XP70 and read by A9
* @INIT: Init value when romcode field is not used
* @FS_2_DS: Value set when power state is going from ApExecute to
* ApDeepSleep
* @END_DS: Value set when ApDeepSleep power state is reached coming from
* ApExecute state
* @DS_TO_FS: Value set when power state is going from ApDeepSleep to
* ApExecute
* @END_FS: Value set when ApExecute power state is reached coming from
* ApDeepSleep state
* @SWR: Value set when power state is going to ApReset
* @END_SWR: Value set when the xp70 finished executing ApReset actions and
* waits for romcode acknowledgment to go to self-reset
*/
enum romcode_read {
INIT = 0x00,
FS_2_DS = 0x0A,
END_DS = 0x0B,
DS_TO_FS = 0x0C,
END_FS = 0x0D,
SWR = 0x0E,
END_SWR = 0x0F
};
/**
* enum ap_pwrst - current power states defined in PRCMU firmware
* @NO_PWRST: Current power state init
* @AP_BOOT: Current power state is apBoot
* @AP_EXECUTE: Current power state is apExecute
* @AP_DEEP_SLEEP: Current power state is apDeepSleep
* @AP_SLEEP: Current power state is apSleep
* @AP_IDLE: Current power state is apIdle
* @AP_RESET: Current power state is apReset
*/
enum ap_pwrst {
NO_PWRST = 0x00,
AP_BOOT = 0x01,
AP_EXECUTE = 0x02,
AP_DEEP_SLEEP = 0x03,
AP_SLEEP = 0x04,
AP_IDLE = 0x05,
AP_RESET = 0x06
};
/**
* enum ap_pwrst_trans - Transition states defined in PRCMU firmware
* @NO_TRANSITION: No power state transition
* @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
* @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
* @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
* @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
* ApDeepSleep
* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
*/
enum ap_pwrst_trans {
PRCMU_AP_NO_CHANGE = 0x00,
APEXECUTE_TO_APSLEEP = 0x01,
APIDLE_TO_APSLEEP = 0x02, /* To be removed */
PRCMU_AP_SLEEP = 0x01,
APBOOT_TO_APEXECUTE = 0x03,
APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
PRCMU_AP_DEEP_SLEEP = 0x04,
APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
PRCMU_AP_IDLE = 0x05,
PRCMU_AP_DEEP_IDLE = 0x07,
};
/**
* enum hw_acc_state - State definition for hardware accelerator
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
* @HW_OFF: The hardware accelerator must be switched off
* @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
* internal RAM in retention
* @HW_ON: The hwa hardware accelerator hwa must be switched on
*
* NOTE! Deprecated, to be removed when all users switched over to use the
* regulator API.
*/
enum hw_acc_state {
HW_NO_CHANGE = 0x00,
HW_OFF = 0x01,
HW_OFF_RAMRET = 0x02,
HW_ON = 0x04
};
/**
* enum mbox_2_arm_stat - Status messages definition for mbox_arm
* @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
* completed
* @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
* completed
* @SLEEPOK: The apExecute to apSleep state transition has been completed
* @IDLEOK: The apExecute to apIdle state transition has been completed
* @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
* @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
* @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
* @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
* going
* @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
* going
* @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
* been completed
* @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
* @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
* @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
* completed
* @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
* @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
* @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
* completed
* @INIT_STATUS: Status init
*/
enum ap_pwrsttr_status {
BOOT_TO_EXECUTEOK = 0xFF,
DEEPSLEEPOK = 0xFE,
SLEEPOK = 0xFD,
IDLEOK = 0xFC,
SOFTRESETOK = 0xFB,
SOFTRESETGO = 0xFA,
BOOT_TO_EXECUTE = 0xF9,
EXECUTE_TO_DEEPSLEEP = 0xF8,
DEEPSLEEP_TO_EXECUTE = 0xF7,
DEEPSLEEP_TO_EXECUTEOK = 0xF6,
EXECUTE_TO_SLEEP = 0xF5,
SLEEP_TO_EXECUTE = 0xF4,
SLEEP_TO_EXECUTEOK = 0xF3,
EXECUTE_TO_IDLE = 0xF2,
IDLE_TO_EXECUTE = 0xF1,
IDLE_TO_EXECUTEOK = 0xF0,
RDYTODS_RETURNTOEXE = 0xEF,
NORDYTODS_RETURNTOEXE = 0xEE,
EXETOSLEEP_RETURNTOEXE = 0xED,
EXETOIDLE_RETURNTOEXE = 0xEC,
INIT_STATUS = 0xEB,
/*error messages */
INITERROR = 0x00,
PLLARMLOCKP_ER = 0x01,
PLLDDRLOCKP_ER = 0x02,
PLLSOCLOCKP_ER = 0x03,
PLLSOCK1LOCKP_ER = 0x04,
ARMWFI_ER = 0x05,
SYSCLKOK_ER = 0x06,
I2C_NACK_DATA_ER = 0x07,
BOOT_ER = 0x08,
I2C_STATUS_ALWAYS_1 = 0x0A,
I2C_NACK_REG_ADDR_ER = 0x0B,
I2C_NACK_DATA0123_ER = 0x1B,
I2C_NACK_ADDR_ER = 0x1F,
CURAPPWRSTISNOT_BOOT = 0x20,
CURAPPWRSTISNOT_EXECUTE = 0x21,
CURAPPWRSTISNOT_SLEEPMODE = 0x22,
CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
FIFO4500WUISNOT_WUPEVENT = 0x24,
PLL32KLOCKP_ER = 0x29,
DDRDEEPSLEEPOK_ER = 0x2A,
ROMCODEREADY_ER = 0x50,
WUPBEFOREDS = 0x51,
DDRCONFIG_ER = 0x52,
WUPBEFORESLEEP = 0x53,
WUPBEFOREIDLE = 0x54
}; /* earlier called as mbox_2_arm_stat */
/**
* enum dvfs_stat - DVFS status messages definition
* @DVFS_GO: A state transition DVFS is on going
* @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
* @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
* @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
* @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
* NOCHGCLK
* @DVFS_INITSTATUS: Value init
*/
enum dvfs_stat {
DVFS_GO = 0xFF,
DVFS_ARM100OPPOK = 0xFE,
DVFS_ARM50OPPOK = 0xFD,
DVFS_ARMEXTCLKOK = 0xFC,
DVFS_NOCHGTCLKOK = 0xFB,
DVFS_INITSTATUS = 0x00
};
/**
* enum sva_mmdsp_stat - SVA MMDSP status messages
* @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
* @SVA_MMDSP_INIT: Status init
*/
enum sva_mmdsp_stat {
SVA_MMDSP_GO = 0xFF,
SVA_MMDSP_INIT = 0x00
};
/**
* enum sia_mmdsp_stat - SIA MMDSP status messages
* @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
* @SIA_MMDSP_INIT: Status init
*/
enum sia_mmdsp_stat {
SIA_MMDSP_GO = 0xFF,
SIA_MMDSP_INIT = 0x00
};
/**
* enum mbox_to_arm_err - Error messages definition
* @INIT_ERR: Init value
* @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
* @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
* @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
* @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
* @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
* @SYSCLKOK_ERR: The SYSCLK is not available in the given time
* @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
* @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
* @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
* through I2C has not been correctly executed in the given time
* @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
* through I2C has not been correctly executed in the given time
* @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
* I2C has not been correctly executed in the given time
* @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
* has not been correctly executed in the given time
* @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
* not been correctly executed in the given time
* @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
* not been correctly executed in the given time
* @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
* through I2C has not been correctly executed in the given time
* @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
* ApBoot to ApExecute but the power current state is not Apboot
* @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
* transition from ApExecute to others power state but the
* power current state is not ApExecute
* @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
* but the power current state is not ApDeepSleep/ApSleep/ApIdle
* @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
* but the power current state is not correct
* @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
* been correctly executed in the given time
* @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
* been correctly executed in the given time
* @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
* been correctly executed in the given time
* @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
* been correctly executed in the given time
* @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
* been correctly executed in the given time
*/
enum mbox_to_arm_err {
INIT_ERR = 0x00,
PLLARMLOCKP_ERR = 0x01,
PLLDDRLOCKP_ERR = 0x02,
PLLSOC0LOCKP_ERR = 0x03,
PLLSOC1LOCKP_ERR = 0x04,
ARMWFI_ERR = 0x05,
SYSCLKOK_ERR = 0x06,
BOOT_ERR = 0x07,
ROMCODESAVECONTEXT = 0x08,
VARMHIGHSPEEDVALTO_ERR = 0x10,
VARMHIGHSPEEDACCESS_ERR = 0x11,
VARMLOWSPEEDVALTO_ERR = 0x12,
VARMLOWSPEEDACCESS_ERR = 0x13,
VARMRETENTIONVALTO_ERR = 0x14,
VARMRETENTIONACCESS_ERR = 0x15,
VAPEHIGHSPEEDVALTO_ERR = 0x16,
VSAFEHPVALTO_ERR = 0x17,
VMODSEL1VALTO_ERR = 0x18,
VMODSEL2VALTO_ERR = 0x19,
VARMOFFACCESS_ERR = 0x1A,
VAPEOFFACCESS_ERR = 0x1B,
VARMRETACCES_ERR = 0x1C,
CURAPPWRSTISNOTBOOT = 0x20,
CURAPPWRSTISNOTEXECUTE = 0x21,
CURAPPWRSTISNOTSLEEPMODE = 0x22,
CURAPPWRSTISNOTCORRECTDBG = 0x23,
ARMREGU1VALTO_ERR = 0x24,
ARMREGU2VALTO_ERR = 0x25,
VAPEREGUVALTO_ERR = 0x26,
VSMPS3REGUVALTO_ERR = 0x27,
VMODREGUVALTO_ERR = 0x28
};
enum hw_acc {
SVAMMDSP = 0,
SVAPIPE = 1,
SIAMMDSP = 2,
SIAPIPE = 3,
SGA = 4,
B2R2MCDE = 5,
ESRAM12 = 6,
ESRAM34 = 7,
};
enum cs_pwrmgt {
PWRDNCS0 = 0,
WKUPCS0 = 1,
PWRDNCS1 = 2,
WKUPCS1 = 3
};
/* Defs related to autonomous power management */
/**
* enum sia_sva_pwr_policy - Power policy
* @NO_CHGT: No change
* @DSPOFF_HWPOFF:
* @DSPOFFRAMRET_HWPOFF:
* @DSPCLKOFF_HWPOFF:
* @DSPCLKOFF_HWPCLKOFF:
*
*/
enum sia_sva_pwr_policy {
NO_CHGT = 0x0,
DSPOFF_HWPOFF = 0x1,
DSPOFFRAMRET_HWPOFF = 0x2,
DSPCLKOFF_HWPOFF = 0x3,
DSPCLKOFF_HWPCLKOFF = 0x4,
};
/**
* enum auto_enable - Auto Power enable
* @AUTO_OFF:
* @AUTO_ON:
*
*/
enum auto_enable {
AUTO_OFF = 0x0,
AUTO_ON = 0x1,
};
/* End of file previously known as prcmu-fw-defs_v1.h */
/**
* enum prcmu_power_status - results from set_power_state
* @PRCMU_SLEEP_OK: Sleep went ok
* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
* @PRCMU_IDLE_OK: Idle went ok
* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
*
*/
enum prcmu_power_status {
PRCMU_SLEEP_OK = 0xf3,
PRCMU_DEEP_SLEEP_OK = 0xf6,
PRCMU_IDLE_OK = 0xf0,
PRCMU_DEEPIDLE_OK = 0xe3,
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
PRCMU_ARMPENDINGIT_ER = 0x93,
};
/*
* Definitions for autonomous power management configuration.
*/
#define PRCMU_AUTO_PM_OFF 0
#define PRCMU_AUTO_PM_ON 1
#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
enum prcmu_auto_pm_policy {
PRCMU_AUTO_PM_POLICY_NO_CHANGE,
PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
};
/**
* struct prcmu_auto_pm_config - Autonomous power management configuration.
* @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
* @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
*/
struct prcmu_auto_pm_config {
u8 sia_auto_pm_enable;
u8 sia_power_on;
u8 sia_policy;
u8 sva_auto_pm_enable;
u8 sva_power_on;
u8 sva_policy;
};
#ifdef CONFIG_MFD_DB8500_PRCMU
void db8500_prcmu_early_init(u32 phy_base, u32 size);
int prcmu_set_rc_a2p(enum romcode_write);
enum romcode_read prcmu_get_rc_p2a(void);
enum ap_pwrst prcmu_get_xp70_current_state(void);
bool prcmu_has_arm_maxopp(void);
struct prcmu_fw_version *prcmu_get_fw_version(void);
int prcmu_release_usb_wakeup_state(void);
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle);
bool prcmu_is_auto_pm_enabled(void);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
int prcmu_set_clock_divider(u8 clock, u8 divider);
int db8500_prcmu_config_hotdog(u8 threshold);
int db8500_prcmu_config_hotmon(u8 low, u8 high);
int db8500_prcmu_start_temp_sense(u16 cycles32k);
int db8500_prcmu_stop_temp_sense(void);
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void db8500_prcmu_modem_reset(void);
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int db8500_prcmu_enable_a9wdog(u8 id);
int db8500_prcmu_disable_a9wdog(u8 id);
int db8500_prcmu_kick_a9wdog(u8 id);
int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
int db8500_prcmu_set_display_clocks(void);
int db8500_prcmu_disable_dsipll(void);
int db8500_prcmu_enable_dsipll(void);
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
u16 db8500_prcmu_get_reset_code(void);
bool db8500_prcmu_is_ac_wake_requested(void);
int db8500_prcmu_set_arm_opp(u8 opp);
int db8500_prcmu_get_arm_opp(void);
int db8500_prcmu_set_ape_opp(u8 opp);
int db8500_prcmu_get_ape_opp(void);
int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
int db8500_prcmu_set_ddr_opp(u8 opp);
int db8500_prcmu_get_ddr_opp(void);
u32 db8500_prcmu_read(unsigned int reg);
void db8500_prcmu_write(unsigned int reg, u32 value);
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
#else /* !CONFIG_MFD_DB8500_PRCMU */
static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
static inline int prcmu_set_rc_a2p(enum romcode_write code)
{
return 0;
}
static inline enum romcode_read prcmu_get_rc_p2a(void)
{
return INIT;
}
static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
{
return AP_EXECUTE;
}
static inline bool prcmu_has_arm_maxopp(void)
{
return false;
}
static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
{
return NULL;
}
static inline int db8500_prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
{
return 0;
}
static inline int prcmu_release_usb_wakeup_state(void)
{
return 0;
}
static inline int db8500_prcmu_set_ddr_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle)
{
}
static inline bool prcmu_is_auto_pm_enabled(void)
{
return false;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
{
return 0;
}
static inline int db8500_prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int db8500_prcmu_stop_temp_sense(void)
{
return 0;
}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_ac_wake_req(void)
{
return 0;
}
static inline void prcmu_ac_sleep_req(void) {}
static inline void db8500_prcmu_modem_reset(void) {}
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline u8 db8500_prcmu_get_power_state_result(void)
{
return 0;
}
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline int db8500_prcmu_set_display_clocks(void)
{
return 0;
}
static inline int db8500_prcmu_disable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_enable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
static inline u16 db8500_prcmu_get_reset_code(void)
{
return 0;
}
static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return 0;
}
static inline int db8500_prcmu_enable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_disable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_kick_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
{
return 0;
}
static inline bool db8500_prcmu_is_ac_wake_requested(void)
{
return 0;
}
static inline int db8500_prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_arm_opp(void)
{
return 0;
}
static inline u32 db8500_prcmu_read(unsigned int reg)
{
return 0;
}
static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
u32 value) {}
#endif /* !CONFIG_MFD_DB8500_PRCMU */
#endif /* __MFD_DB8500_PRCMU_H */

722
include/linux/mfd/dbx500-prcmu.h Normal file
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/*
* Copyright (C) ST Ericsson SA 2011
*
* License Terms: GNU General Public License v2
*
* STE Ux500 PRCMU API
*/
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>
/* Offset for the firmware version within the TCPM */
#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
PRCMU_WAKEUP_INDEX_RTC,
PRCMU_WAKEUP_INDEX_RTT0,
PRCMU_WAKEUP_INDEX_RTT1,
PRCMU_WAKEUP_INDEX_HSI0,
PRCMU_WAKEUP_INDEX_HSI1,
PRCMU_WAKEUP_INDEX_USB,
PRCMU_WAKEUP_INDEX_ABB,
PRCMU_WAKEUP_INDEX_ABB_FIFO,
PRCMU_WAKEUP_INDEX_ARM,
PRCMU_WAKEUP_INDEX_CD_IRQ,
NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
/* EPOD (power domain) IDs */
/*
* DB8500 EPODs
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
* - EPOD_ID_SGA: power domain for SGA
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
* - NUM_EPOD_ID: number of power domains
*
* TODO: These should be prefixed.
*/
#define EPOD_ID_SVAMMDSP 0
#define EPOD_ID_SVAPIPE 1
#define EPOD_ID_SIAMMDSP 2
#define EPOD_ID_SIAPIPE 3
#define EPOD_ID_SGA 4
#define EPOD_ID_B2R2_MCDE 5
#define EPOD_ID_ESRAM12 6
#define EPOD_ID_ESRAM34 7
#define NUM_EPOD_ID 8
/*
* state definition for EPOD (power domain)
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
* - EPOD_STATE_OFF: The EPOD is switched off
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
* retention
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
* - EPOD_STATE_ON: Same as above, but with clock enabled
*/
#define EPOD_STATE_NO_CHANGE 0x00
#define EPOD_STATE_OFF 0x01
#define EPOD_STATE_RAMRET 0x02
#define EPOD_STATE_ON_CLK_OFF 0x03
#define EPOD_STATE_ON 0x04
/*
* CLKOUT sources
*/
#define PRCMU_CLKSRC_CLK38M 0x00
#define PRCMU_CLKSRC_ACLK 0x01
#define PRCMU_CLKSRC_SYSCLK 0x02
#define PRCMU_CLKSRC_LCDCLK 0x03
#define PRCMU_CLKSRC_SDMMCCLK 0x04
#define PRCMU_CLKSRC_TVCLK 0x05
#define PRCMU_CLKSRC_TIMCLK 0x06
#define PRCMU_CLKSRC_CLK009 0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
#define PRCMU_CLKSRC_I2CCLK 0x41
#define PRCMU_CLKSRC_MSP02CLK 0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
#define PRCMU_CLKSRC_HSIRXCLK 0x44
#define PRCMU_CLKSRC_HSITXCLK 0x45
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
#define PRCMU_CLKSRC_HDMICLK 0x47
/*
* Clock identifiers.
*/
enum prcmu_clock {
PRCMU_SGACLK,
PRCMU_UARTCLK,
PRCMU_MSP02CLK,
PRCMU_MSP1CLK,
PRCMU_I2CCLK,
PRCMU_SDMMCCLK,
PRCMU_SPARE1CLK,
PRCMU_SLIMCLK,
PRCMU_PER1CLK,
PRCMU_PER2CLK,
PRCMU_PER3CLK,
PRCMU_PER5CLK,
PRCMU_PER6CLK,
PRCMU_PER7CLK,
PRCMU_LCDCLK,
PRCMU_BMLCLK,
PRCMU_HSITXCLK,
PRCMU_HSIRXCLK,
PRCMU_HDMICLK,
PRCMU_APEATCLK,
PRCMU_APETRACECLK,
PRCMU_MCDECLK,
PRCMU_IPI2CCLK,
PRCMU_DSIALTCLK,
PRCMU_DMACLK,
PRCMU_B2R2CLK,
PRCMU_TVCLK,
PRCMU_SSPCLK,
PRCMU_RNGCLK,
PRCMU_UICCCLK,
PRCMU_PWMCLK,
PRCMU_IRDACLK,
PRCMU_IRRCCLK,
PRCMU_SIACLK,
PRCMU_SVACLK,
PRCMU_ACLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
PRCMU_TIMCLK,
PRCMU_PLLSOC0,
PRCMU_PLLSOC1,
PRCMU_ARMSS,
PRCMU_PLLDDR,
PRCMU_PLLDSI,
PRCMU_DSI0CLK,
PRCMU_DSI1CLK,
PRCMU_DSI0ESCCLK,
PRCMU_DSI1ESCCLK,
PRCMU_DSI2ESCCLK,
};
/**
* enum prcmu_wdog_id - PRCMU watchdog IDs
* @PRCMU_WDOG_ALL: use all timers
* @PRCMU_WDOG_CPU1: use first CPU timer only
* @PRCMU_WDOG_CPU2: use second CPU timer conly
*/
enum prcmu_wdog_id {
PRCMU_WDOG_ALL = 0x00,
PRCMU_WDOG_CPU1 = 0x01,
PRCMU_WDOG_CPU2 = 0x02,
};
/**
* enum ape_opp - APE OPP states definition
* @APE_OPP_INIT:
* @APE_NO_CHANGE: The APE operating point is unchanged
* @APE_100_OPP: The new APE operating point is ape100opp
* @APE_50_OPP: 50%
* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
*/
enum ape_opp {
APE_OPP_INIT = 0x00,
APE_NO_CHANGE = 0x01,
APE_100_OPP = 0x02,
APE_50_OPP = 0x03,
APE_50_PARTLY_25_OPP = 0xFF,
};
/**
* enum arm_opp - ARM OPP states definition
* @ARM_OPP_INIT:
* @ARM_NO_CHANGE: The ARM operating point is unchanged
* @ARM_100_OPP: The new ARM operating point is arm100opp
* @ARM_50_OPP: The new ARM operating point is arm50opp
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
* @ARM_EXTCLK: The new ARM operating point is armExtClk
*/
enum arm_opp {
ARM_OPP_INIT = 0x00,
ARM_NO_CHANGE = 0x01,
ARM_100_OPP = 0x02,
ARM_50_OPP = 0x03,
ARM_MAX_OPP = 0x04,
ARM_MAX_FREQ100OPP = 0x05,
ARM_EXTCLK = 0x07
};
/**
* enum ddr_opp - DDR OPP states definition
* @DDR_100_OPP: The new DDR operating point is ddr100opp
* @DDR_50_OPP: The new DDR operating point is ddr50opp
* @DDR_25_OPP: The new DDR operating point is ddr25opp
*/
enum ddr_opp {
DDR_100_OPP = 0x00,
DDR_50_OPP = 0x01,
DDR_25_OPP = 0x02,
};
/*
* Definitions for controlling ESRAM0 in deep sleep.
*/
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
/**
* enum ddr_pwrst - DDR power states definition
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
* @DDR_PWR_STATE_ON:
* @DDR_PWR_STATE_OFFLOWLAT:
* @DDR_PWR_STATE_OFFHIGHLAT:
*/
enum ddr_pwrst {
DDR_PWR_STATE_UNCHANGED = 0x00,
DDR_PWR_STATE_ON = 0x01,
DDR_PWR_STATE_OFFLOWLAT = 0x02,
DDR_PWR_STATE_OFFHIGHLAT = 0x03
};
#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
struct prcmu_pdata
{
bool enable_set_ddr_opp;
bool enable_ape_opp_100_voltage;
struct ab8500_platform_data *ab_platdata;
int ab_irq;
int irq_base;
u32 version_offset;
u32 legacy_offset;
u32 adt_offset;
};
#define PRCMU_FW_PROJECT_U8500 2
#define PRCMU_FW_PROJECT_U8400 3
#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBB 5
#define PRCMU_FW_PROJECT_U8500_C1 6
#define PRCMU_FW_PROJECT_U8500_C2 7
#define PRCMU_FW_PROJECT_U8500_C3 8
#define PRCMU_FW_PROJECT_U8500_C4 9
#define PRCMU_FW_PROJECT_U9500_MBL 10
#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
#define PRCMU_FW_PROJECT_U8520 13
#define PRCMU_FW_PROJECT_U8420 14
#define PRCMU_FW_PROJECT_A9420 20
/* [32..63] 9540 and derivatives */
#define PRCMU_FW_PROJECT_U9540 32
/* [64..95] 8540 and derivatives */
#define PRCMU_FW_PROJECT_L8540 64
/* [96..126] 8580 and derivatives */
#define PRCMU_FW_PROJECT_L8580 96
#define PRCMU_FW_PROJECT_NAME_LEN 20
struct prcmu_fw_version {
u32 project; /* Notice, project shifted with 8 on ux540 */
u8 api_version;
u8 func_version;
u8 errata;
char project_name[PRCMU_FW_PROJECT_NAME_LEN];
};
#include <linux/mfd/db8500-prcmu.h>
#if defined(CONFIG_UX500_SOC_DB8500)
static inline void prcmu_early_init(u32 phy_base, u32 size)
{
return db8500_prcmu_early_init(phy_base, size);
}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return db8500_prcmu_set_power_state(state, keep_ulp_clk,
keep_ap_pll);
}
static inline u8 prcmu_get_power_state_result(void)
{
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return db8500_prcmu_set_epod(epod_id, epod_state);
}
static inline void prcmu_enable_wakeups(u32 wakeups)
{
db8500_prcmu_enable_wakeups(wakeups);
}
static inline void prcmu_disable_wakeups(void)
{
prcmu_enable_wakeups(0);
}
static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
db8500_prcmu_config_abb_event_readout(abb_events);
}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
db8500_prcmu_get_abb_event_buffer(buf);
}
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
static inline int prcmu_request_clock(u8 clock, bool enable)
{
return db8500_prcmu_request_clock(clock, enable);
}
unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);
static inline int prcmu_set_ddr_opp(u8 opp)
{
return db8500_prcmu_set_ddr_opp(opp);
}
static inline int prcmu_get_ddr_opp(void)
{
return db8500_prcmu_get_ddr_opp();
}
static inline int prcmu_set_arm_opp(u8 opp)
{
return db8500_prcmu_set_arm_opp(opp);
}
static inline int prcmu_get_arm_opp(void)
{
return db8500_prcmu_get_arm_opp();
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return db8500_prcmu_set_ape_opp(opp);
}
static inline int prcmu_get_ape_opp(void)
{
return db8500_prcmu_get_ape_opp();
}
static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
return db8500_prcmu_request_ape_opp_100_voltage(enable);
}
static inline void prcmu_system_reset(u16 reset_code)
{
return db8500_prcmu_system_reset(reset_code);
}
static inline u16 prcmu_get_reset_code(void)
{
return db8500_prcmu_get_reset_code();
}
int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
return db8500_prcmu_modem_reset();
}
static inline bool prcmu_is_ac_wake_requested(void)
{
return db8500_prcmu_is_ac_wake_requested();
}
static inline int prcmu_set_display_clocks(void)
{
return db8500_prcmu_set_display_clocks();
}
static inline int prcmu_disable_dsipll(void)
{
return db8500_prcmu_disable_dsipll();
}
static inline int prcmu_enable_dsipll(void)
{
return db8500_prcmu_enable_dsipll();
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return db8500_prcmu_config_esram0_deep_sleep(state);
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return db8500_prcmu_config_hotdog(threshold);
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return db8500_prcmu_config_hotmon(low, high);
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return db8500_prcmu_start_temp_sense(cycles32k);
}
static inline int prcmu_stop_temp_sense(void)
{
return db8500_prcmu_stop_temp_sense();
}
static inline u32 prcmu_read(unsigned int reg)
{
return db8500_prcmu_read(reg);
}
static inline void prcmu_write(unsigned int reg, u32 value)
{
db8500_prcmu_write(reg, value);
}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
db8500_prcmu_write_masked(reg, mask, value);
}
static inline int prcmu_enable_a9wdog(u8 id)
{
return db8500_prcmu_enable_a9wdog(id);
}
static inline int prcmu_disable_a9wdog(u8 id)
{
return db8500_prcmu_disable_a9wdog(id);
}
static inline int prcmu_kick_a9wdog(u8 id)
{
return db8500_prcmu_kick_a9wdog(id);
}
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
return db8500_prcmu_load_a9wdog(id, timeout);
}
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else
static inline void prcmu_early_init(u32 phy_base, u32 size) {}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline void prcmu_enable_wakeups(u32 wakeups) {}
static inline void prcmu_disable_wakeups(void) {}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
u8 size)
{
return -ENOSYS;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline unsigned long prcmu_clock_rate(u8 clock)
{
return 0;
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
return 0;
}
static inline int prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_arm_opp(void)
{
return ARM_100_OPP;
}
static inline int prcmu_set_ddr_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_system_reset(u16 reset_code) {}
static inline u16 prcmu_get_reset_code(void)
{
return 0;
}
static inline int prcmu_ac_wake_req(void)
{
return 0;
}
static inline void prcmu_ac_sleep_req(void) {}
static inline void prcmu_modem_reset(void) {}
static inline bool prcmu_is_ac_wake_requested(void)
{
return false;
}
static inline int prcmu_set_display_clocks(void)
{
return 0;
}
static inline int prcmu_disable_dsipll(void)
{
return 0;
}
static inline int prcmu_enable_dsipll(void)
{
return 0;
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
*buf = NULL;
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int prcmu_stop_temp_sense(void)
{
return 0;
}
static inline u32 prcmu_read(unsigned int reg)
{
return 0;
}
static inline void prcmu_write(unsigned int reg, u32 value) {}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
#endif
static inline void prcmu_set(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, bits);
}
static inline void prcmu_clear(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, 0);
}
/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1
#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
void prcmu_qos_force_opp(int, s32);
int prcmu_qos_requirement(int pm_qos_class);
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
int prcmu_qos_add_notifier(int prcmu_qos_class,
struct notifier_block *notifier);
int prcmu_qos_remove_notifier(int prcmu_qos_class,
struct notifier_block *notifier);
#else
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
{
return 0;
}
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
static inline int prcmu_qos_requirement(int prcmu_qos_class)
{
return 0;
}
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
char *name, s32 value)
{
return 0;
}
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
char *name, s32 new_value)
{
return 0;
}
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
struct notifier_block *notifier)
{
return 0;
}
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
struct notifier_block *notifier)
{
return 0;
}
#endif
#endif /* __MACH_PRCMU_H */

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/* MFD cell driver data for the DS1WM driver */
struct ds1wm_driver_data {
int active_high;
int clock_rate;
/* in milliseconds, the amount of time to */
/* sleep following a reset pulse. Zero */
/* should work if your bus devices recover*/
/* time respects the 1-wire spec since the*/
/* ds1wm implements the precise timings of*/
/* a reset pulse/presence detect sequence.*/
unsigned int reset_recover_delay;
};

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/*
* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
*
* For further information, please see http://wiki.openezx.org/PCAP2
*/
#ifndef EZX_PCAP_H
#define EZX_PCAP_H
struct pcap_subdev {
int id;
const char *name;
void *platform_data;
};
struct pcap_platform_data {
unsigned int irq_base;
unsigned int config;
int gpio;
void (*init) (void *); /* board specific init */
int num_subdevs;
struct pcap_subdev *subdevs;
};
struct pcap_chip;
int ezx_pcap_write(struct pcap_chip *, u8, u32);
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
int pcap_to_irq(struct pcap_chip *, int);
int irq_to_pcap(struct pcap_chip *, int);
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
void pcap_set_ts_bits(struct pcap_chip *, u32);
#define PCAP_SECOND_PORT 1
#define PCAP_CS_AH 2
#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
#define PCAP_REGISTER_READ_OP_BIT 0x00000000
#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
#define PCAP_REGISTER_ADDRESS_SHIFT 26
#define PCAP_REGISTER_NUMBER 32
#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
/* registers accessible by both pcap ports */
#define PCAP_REG_ISR 0x0 /* Interrupt Status */
#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
#define PCAP_REG_PSTAT 0x2 /* Processor Status */
#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
#define PCAP_REG_BATT 0x8 /* Battery Control */
#define PCAP_REG_ADC 0x9 /* AD Control */
#define PCAP_REG_ADR 0xa /* AD Result */
#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
#define PCAP_REG_GP 0x1b /* General Purpose */
#define PCAP_REG_TEST1 0x1c
#define PCAP_REG_TEST2 0x1d
#define PCAP_REG_VENDOR_TEST1 0x1e
#define PCAP_REG_VENDOR_TEST2 0x1f
/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
#define PCAP_REG_PWR 0x13 /* Power Control */
#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
#define PCAP_REG_VENDOR_REV 0x17
#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
/* PCAP2 Interrupts */
#define PCAP_NIRQS 23
#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
#define PCAP_IRQ_TS 1 /* Touch Screen */
#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
#define PCAP_IRQ_WH 3 /* ADC above high limit */
#define PCAP_IRQ_WL 4 /* ADC below low limit */
#define PCAP_IRQ_TODA 5 /* Time of day alarm */
#define PCAP_IRQ_USB4V 6 /* USB above 4V */
#define PCAP_IRQ_ONOFF 7 /* On/Off button */
#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
#define PCAP_IRQ_USB1V 9 /* USB above 1V */
#define PCAP_IRQ_MOBPORT 10
#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
#define PCAP_IRQ_HS 12 /* Headset attach */
#define PCAP_IRQ_ST 13
#define PCAP_IRQ_PC 14 /* Power Cut */
#define PCAP_IRQ_WARM 15
#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
#define PCAP_IRQ_CLK 17
#define PCAP_IRQ_SYSRST 18 /* System Reset */
#define PCAP_IRQ_DUMMY 19
#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
#define PCAP_IRQ_SOFTRESET 21
#define PCAP_IRQ_MNEXB 22
/* voltage regulators */
#define V1 0
#define V2 1
#define V3 2
#define V4 3
#define V5 4
#define V6 5
#define V7 6
#define V8 7
#define V9 8
#define V10 9
#define VAUX1 10
#define VAUX2 11
#define VAUX3 12
#define VAUX4 13
#define VSIM 14
#define VSIM2 15
#define VVIB 16
#define SW1 17
#define SW2 18
#define SW3 19
#define SW1S 20
#define SW2S 21
#define PCAP_BATT_DAC_MASK 0x000000ff
#define PCAP_BATT_DAC_SHIFT 0
#define PCAP_BATT_B_FDBK (1 << 8)
#define PCAP_BATT_EXT_ISENSE (1 << 9)
#define PCAP_BATT_V_COIN_MASK 0x00003c00
#define PCAP_BATT_V_COIN_SHIFT 10
#define PCAP_BATT_I_COIN (1 << 14)
#define PCAP_BATT_COIN_CH_EN (1 << 15)
#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
#define PCAP_BATT_EOL_SEL_SHIFT 17
#define PCAP_BATT_EOL_CMP_EN (1 << 20)
#define PCAP_BATT_BATT_DET_EN (1 << 21)
#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
#define PCAP_ADC_ADEN (1 << 0)
#define PCAP_ADC_RAND (1 << 1)
#define PCAP_ADC_AD_SEL1 (1 << 2)
#define PCAP_ADC_AD_SEL2 (1 << 3)
#define PCAP_ADC_ADA1_MASK 0x00000070
#define PCAP_ADC_ADA1_SHIFT 4
#define PCAP_ADC_ADA2_MASK 0x00000380
#define PCAP_ADC_ADA2_SHIFT 7
#define PCAP_ADC_ATO_MASK 0x00003c00
#define PCAP_ADC_ATO_SHIFT 10
#define PCAP_ADC_ATOX (1 << 14)
#define PCAP_ADC_MTR1 (1 << 15)
#define PCAP_ADC_MTR2 (1 << 16)
#define PCAP_ADC_TS_M_MASK 0x000e0000
#define PCAP_ADC_TS_M_SHIFT 17
#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
#define PCAP_ADC_TS_REFENB (1 << 21)
#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
#define PCAP_ADC_BATT_I_ADC (1 << 23)
#define PCAP_ADC_BANK_0 0
#define PCAP_ADC_BANK_1 1
/* ADC bank 0 */
#define PCAP_ADC_CH_COIN 0
#define PCAP_ADC_CH_BATT 1
#define PCAP_ADC_CH_BPLUS 2
#define PCAP_ADC_CH_MOBPORTB 3
#define PCAP_ADC_CH_TEMPERATURE 4
#define PCAP_ADC_CH_CHARGER_ID 5
#define PCAP_ADC_CH_AD6 6
/* ADC bank 1 */
#define PCAP_ADC_CH_AD7 0
#define PCAP_ADC_CH_AD8 1
#define PCAP_ADC_CH_AD9 2
#define PCAP_ADC_CH_TS_X1 3
#define PCAP_ADC_CH_TS_X2 4
#define PCAP_ADC_CH_TS_Y1 5
#define PCAP_ADC_CH_TS_Y2 6
#define PCAP_ADC_T_NOW 0
#define PCAP_ADC_T_IN_BURST 1
#define PCAP_ADC_T_OUT_BURST 2
#define PCAP_ADC_ATO_IN_BURST 6
#define PCAP_ADC_ATO_OUT_BURST 0
#define PCAP_ADC_TS_M_XY 1
#define PCAP_ADC_TS_M_PRESSURE 2
#define PCAP_ADC_TS_M_PLATE_X 3
#define PCAP_ADC_TS_M_PLATE_Y 4
#define PCAP_ADC_TS_M_STANDBY 5
#define PCAP_ADC_TS_M_NONTS 6
#define PCAP_ADR_ADD1_MASK 0x000003ff
#define PCAP_ADR_ADD1_SHIFT 0
#define PCAP_ADR_ADD2_MASK 0x000ffc00
#define PCAP_ADR_ADD2_SHIFT 10
#define PCAP_ADR_ADINC1 (1 << 20)
#define PCAP_ADR_ADINC2 (1 << 21)
#define PCAP_ADR_ASC (1 << 22)
#define PCAP_ADR_ONESHOT (1 << 23)
#define PCAP_BUSCTRL_FSENB (1 << 0)
#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
#define PCAP_BUSCTRL_USB_PU (1 << 2)
#define PCAP_BUSCTRL_USB_PD (1 << 3)
#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
#define PCAP_BUSCTRL_USB_PS (1 << 5)
#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
#define PCAP_BUSCTRL_CURRLIM (1 << 8)
#define PCAP_BUSCTRL_RS232ENB (1 << 9)
#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
#define PCAP_BUSCTRL_USB_PDM (1 << 12)
#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
/* leds */
#define PCAP_LED0 0
#define PCAP_LED1 1
#define PCAP_BL0 2
#define PCAP_BL1 3
#define PCAP_LED_3MA 0
#define PCAP_LED_4MA 1
#define PCAP_LED_5MA 2
#define PCAP_LED_9MA 3
#define PCAP_LED_T_MASK 0xf
#define PCAP_LED_C_MASK 0x3
#define PCAP_BL_MASK 0x1f
#define PCAP_BL0_SHIFT 0
#define PCAP_LED0_EN (1 << 5)
#define PCAP_LED1_EN (1 << 6)
#define PCAP_LED0_T_SHIFT 7
#define PCAP_LED1_T_SHIFT 11
#define PCAP_LED0_C_SHIFT 15
#define PCAP_LED1_C_SHIFT 17
#define PCAP_BL1_SHIFT 20
/* RTC */
#define PCAP_RTC_DAY_MASK 0x3fff
#define PCAP_RTC_TOD_MASK 0xffff
#define PCAP_RTC_PC_MASK 0x7
#define SEC_PER_DAY 86400
#endif

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/*
* HTC simple EGPIO irq and gpio extender
*/
#ifndef __HTC_EGPIO_H__
#define __HTC_EGPIO_H__
#include <linux/gpio.h>
/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
#define HTC_EGPIO_OUTPUT (~0)
#define HTC_EGPIO_INPUT 0
/**
* struct htc_egpio_chip - descriptor to create gpio_chip for register range
* @reg_start: index of first register
* @gpio_base: gpio number of first pin in this register range
* @num_gpios: number of gpios in this register range, max BITS_PER_LONG
* (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
* @direction: bitfield, '0' = input, '1' = output,
*/
struct htc_egpio_chip {
int reg_start;
int gpio_base;
int num_gpios;
unsigned long direction;
unsigned long initial_values;
};
/**
* struct htc_egpio_platform_data - description provided by the arch
* @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
* @num_irqs: number of irqs
* @reg_width: number of bits per register, either 8 or 16 bit
* @bus_width: alignment of the registers, either 16 or 32 bit
* @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
* @ack_register: location of the irq/ack register
* @chip: pointer to array of htc_egpio_chip descriptors
* @num_chips: number of egpio chip descriptors
*/
struct htc_egpio_platform_data {
int bus_width;
int reg_width;
int irq_base;
int num_irqs;
int invert_acks;
int ack_register;
struct htc_egpio_chip *chip;
int num_chips;
};
/* Determine the wakeup irq, to be called during early resume */
extern int htc_egpio_get_wakeup_irq(struct device *dev);
#endif

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include/linux/mfd/htc-pasic3.h Normal file
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/*
* HTC PASIC3 driver - LEDs and DS1WM
*
* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef __PASIC3_H
#define __PASIC3_H
#include <linux/platform_device.h>
#include <linux/leds.h>
extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
extern u8 pasic3_read_register(struct device *dev, u32 reg);
/*
* mask for registers 0x20,0x21,0x22
*/
#define PASIC3_MASK_LED0 0x04
#define PASIC3_MASK_LED1 0x08
#define PASIC3_MASK_LED2 0x40
/*
* bits in register 0x06
*/
#define PASIC3_BIT2_LED0 0x08
#define PASIC3_BIT2_LED1 0x10
#define PASIC3_BIT2_LED2 0x20
struct pasic3_led {
struct led_classdev led;
unsigned int hw_num;
unsigned int bit2;
unsigned int mask;
struct pasic3_leds_machinfo *pdata;
};
struct pasic3_leds_machinfo {
unsigned int num_leds;
unsigned int power_gpio;
struct pasic3_led *leds;
};
struct pasic3_platform_data {
struct pasic3_leds_machinfo *led_pdata;
unsigned int clock_rate;
};
#endif

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/*
* include/linux/mfd/intel_msic.h - Core interface for Intel MSIC
*
* Copyright (C) 2011, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_INTEL_MSIC_H__
#define __LINUX_MFD_INTEL_MSIC_H__
/* ID */
#define INTEL_MSIC_ID0 0x000 /* RO */
#define INTEL_MSIC_ID1 0x001 /* RO */
/* IRQ */
#define INTEL_MSIC_IRQLVL1 0x002
#define INTEL_MSIC_ADC1INT 0x003
#define INTEL_MSIC_CCINT 0x004
#define INTEL_MSIC_PWRSRCINT 0x005
#define INTEL_MSIC_PWRSRCINT1 0x006
#define INTEL_MSIC_CHRINT 0x007
#define INTEL_MSIC_CHRINT1 0x008
#define INTEL_MSIC_RTCIRQ 0x009
#define INTEL_MSIC_GPIO0LVIRQ 0x00a
#define INTEL_MSIC_GPIO1LVIRQ 0x00b
#define INTEL_MSIC_GPIOHVIRQ 0x00c
#define INTEL_MSIC_VRINT 0x00d
#define INTEL_MSIC_OCAUDIO 0x00e
#define INTEL_MSIC_ACCDET 0x00f
#define INTEL_MSIC_RESETIRQ1 0x010
#define INTEL_MSIC_RESETIRQ2 0x011
#define INTEL_MSIC_MADC1INT 0x012
#define INTEL_MSIC_MCCINT 0x013
#define INTEL_MSIC_MPWRSRCINT 0x014
#define INTEL_MSIC_MPWRSRCINT1 0x015
#define INTEL_MSIC_MCHRINT 0x016
#define INTEL_MSIC_MCHRINT1 0x017
#define INTEL_MSIC_RTCIRQMASK 0x018
#define INTEL_MSIC_GPIO0LVIRQMASK 0x019
#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a
#define INTEL_MSIC_GPIOHVIRQMASK 0x01b
#define INTEL_MSIC_VRINTMASK 0x01c
#define INTEL_MSIC_OCAUDIOMASK 0x01d
#define INTEL_MSIC_ACCDETMASK 0x01e
#define INTEL_MSIC_RESETIRQ1MASK 0x01f
#define INTEL_MSIC_RESETIRQ2MASK 0x020
#define INTEL_MSIC_IRQLVL1MSK 0x021
#define INTEL_MSIC_PBCONFIG 0x03e
#define INTEL_MSIC_PBSTATUS 0x03f /* RO */
/* GPIO */
#define INTEL_MSIC_GPIO0LV7CTLO 0x040
#define INTEL_MSIC_GPIO0LV6CTLO 0x041
#define INTEL_MSIC_GPIO0LV5CTLO 0x042
#define INTEL_MSIC_GPIO0LV4CTLO 0x043
#define INTEL_MSIC_GPIO0LV3CTLO 0x044
#define INTEL_MSIC_GPIO0LV2CTLO 0x045
#define INTEL_MSIC_GPIO0LV1CTLO 0x046
#define INTEL_MSIC_GPIO0LV0CTLO 0x047
#define INTEL_MSIC_GPIO1LV7CTLOS 0x048
#define INTEL_MSIC_GPIO1LV6CTLO 0x049
#define INTEL_MSIC_GPIO1LV5CTLO 0x04a
#define INTEL_MSIC_GPIO1LV4CTLO 0x04b
#define INTEL_MSIC_GPIO1LV3CTLO 0x04c
#define INTEL_MSIC_GPIO1LV2CTLO 0x04d
#define INTEL_MSIC_GPIO1LV1CTLO 0x04e
#define INTEL_MSIC_GPIO1LV0CTLO 0x04f
#define INTEL_MSIC_GPIO0LV7CTLI 0x050
#define INTEL_MSIC_GPIO0LV6CTLI 0x051
#define INTEL_MSIC_GPIO0LV5CTLI 0x052
#define INTEL_MSIC_GPIO0LV4CTLI 0x053
#define INTEL_MSIC_GPIO0LV3CTLI 0x054
#define INTEL_MSIC_GPIO0LV2CTLI 0x055
#define INTEL_MSIC_GPIO0LV1CTLI 0x056
#define INTEL_MSIC_GPIO0LV0CTLI 0x057
#define INTEL_MSIC_GPIO1LV7CTLIS 0x058
#define INTEL_MSIC_GPIO1LV6CTLI 0x059
#define INTEL_MSIC_GPIO1LV5CTLI 0x05a
#define INTEL_MSIC_GPIO1LV4CTLI 0x05b
#define INTEL_MSIC_GPIO1LV3CTLI 0x05c
#define INTEL_MSIC_GPIO1LV2CTLI 0x05d
#define INTEL_MSIC_GPIO1LV1CTLI 0x05e
#define INTEL_MSIC_GPIO1LV0CTLI 0x05f
#define INTEL_MSIC_PWM0CLKDIV1 0x061
#define INTEL_MSIC_PWM0CLKDIV0 0x062
#define INTEL_MSIC_PWM1CLKDIV1 0x063
#define INTEL_MSIC_PWM1CLKDIV0 0x064
#define INTEL_MSIC_PWM2CLKDIV1 0x065
#define INTEL_MSIC_PWM2CLKDIV0 0x066
#define INTEL_MSIC_PWM0DUTYCYCLE 0x067
#define INTEL_MSIC_PWM1DUTYCYCLE 0x068
#define INTEL_MSIC_PWM2DUTYCYCLE 0x069
#define INTEL_MSIC_GPIO0HV3CTLO 0x06d
#define INTEL_MSIC_GPIO0HV2CTLO 0x06e
#define INTEL_MSIC_GPIO0HV1CTLO 0x06f
#define INTEL_MSIC_GPIO0HV0CTLO 0x070
#define INTEL_MSIC_GPIO1HV3CTLO 0x071
#define INTEL_MSIC_GPIO1HV2CTLO 0x072
#define INTEL_MSIC_GPIO1HV1CTLO 0x073
#define INTEL_MSIC_GPIO1HV0CTLO 0x074
#define INTEL_MSIC_GPIO0HV3CTLI 0x075
#define INTEL_MSIC_GPIO0HV2CTLI 0x076
#define INTEL_MSIC_GPIO0HV1CTLI 0x077
#define INTEL_MSIC_GPIO0HV0CTLI 0x078
#define INTEL_MSIC_GPIO1HV3CTLI 0x079
#define INTEL_MSIC_GPIO1HV2CTLI 0x07a
#define INTEL_MSIC_GPIO1HV1CTLI 0x07b
#define INTEL_MSIC_GPIO1HV0CTLI 0x07c
/* SVID */
#define INTEL_MSIC_SVIDCTRL0 0x080
#define INTEL_MSIC_SVIDCTRL1 0x081
#define INTEL_MSIC_SVIDCTRL2 0x082
#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */
#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087
#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088
#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089
#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a
#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b
#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c
#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */
/* VREG */
#define INTEL_MSIC_VCCLATCH 0x0c0
#define INTEL_MSIC_VNNLATCH 0x0c1
#define INTEL_MSIC_VCCCNT 0x0c2
#define INTEL_MSIC_SMPSRAMP 0x0c3
#define INTEL_MSIC_VNNCNT 0x0c4
#define INTEL_MSIC_VNNAONCNT 0x0c5
#define INTEL_MSIC_VCC122AONCNT 0x0c6
#define INTEL_MSIC_V180AONCNT 0x0c7
#define INTEL_MSIC_V500CNT 0x0c8
#define INTEL_MSIC_VIHFCNT 0x0c9
#define INTEL_MSIC_LDORAMP1 0x0ca
#define INTEL_MSIC_LDORAMP2 0x0cb
#define INTEL_MSIC_VCC108AONCNT 0x0cc
#define INTEL_MSIC_VCC108ASCNT 0x0cd
#define INTEL_MSIC_VCC108CNT 0x0ce
#define INTEL_MSIC_VCCA100ASCNT 0x0cf
#define INTEL_MSIC_VCCA100CNT 0x0d0
#define INTEL_MSIC_VCC180AONCNT 0x0d1
#define INTEL_MSIC_VCC180CNT 0x0d2
#define INTEL_MSIC_VCC330CNT 0x0d3
#define INTEL_MSIC_VUSB330CNT 0x0d4
#define INTEL_MSIC_VCCSDIOCNT 0x0d5
#define INTEL_MSIC_VPROG1CNT 0x0d6
#define INTEL_MSIC_VPROG2CNT 0x0d7
#define INTEL_MSIC_VEMMCSCNT 0x0d8
#define INTEL_MSIC_VEMMC1CNT 0x0d9
#define INTEL_MSIC_VEMMC2CNT 0x0da
#define INTEL_MSIC_VAUDACNT 0x0db
#define INTEL_MSIC_VHSPCNT 0x0dc
#define INTEL_MSIC_VHSNCNT 0x0dd
#define INTEL_MSIC_VHDMICNT 0x0de
#define INTEL_MSIC_VOTGCNT 0x0df
#define INTEL_MSIC_V1P35CNT 0x0e0
#define INTEL_MSIC_V330AONCNT 0x0e1
/* RESET */
#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */
#define INTEL_MSIC_ERCONFIG 0x101
/* BURST */
#define INTEL_MSIC_BATCURRENTLIMIT12 0x102
#define INTEL_MSIC_BATTIMELIMIT12 0x103
#define INTEL_MSIC_BATTIMELIMIT3 0x104
#define INTEL_MSIC_BATTIMEDB 0x105
#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106
#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107
#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108
/* RTC */
#define INTEL_MSIC_RTCB1 0x140 /* RO */
#define INTEL_MSIC_RTCB2 0x141 /* RO */
#define INTEL_MSIC_RTCB3 0x142 /* RO */
#define INTEL_MSIC_RTCB4 0x143 /* RO */
#define INTEL_MSIC_RTCOB1 0x144
#define INTEL_MSIC_RTCOB2 0x145
#define INTEL_MSIC_RTCOB3 0x146
#define INTEL_MSIC_RTCOB4 0x147
#define INTEL_MSIC_RTCAB1 0x148
#define INTEL_MSIC_RTCAB2 0x149
#define INTEL_MSIC_RTCAB3 0x14a
#define INTEL_MSIC_RTCAB4 0x14b
#define INTEL_MSIC_RTCWAB1 0x14c
#define INTEL_MSIC_RTCWAB2 0x14d
#define INTEL_MSIC_RTCWAB3 0x14e
#define INTEL_MSIC_RTCWAB4 0x14f
#define INTEL_MSIC_RTCSC1 0x150
#define INTEL_MSIC_RTCSC2 0x151
#define INTEL_MSIC_RTCSC3 0x152
#define INTEL_MSIC_RTCSC4 0x153
#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */
#define INTEL_MSIC_RTCCONFIG1 0x155
#define INTEL_MSIC_RTCCONFIG2 0x156
/* CHARGER */
#define INTEL_MSIC_BDTIMER 0x180
#define INTEL_MSIC_BATTRMV 0x181
#define INTEL_MSIC_VBUSDET 0x182
#define INTEL_MSIC_VBUSDET1 0x183
#define INTEL_MSIC_ADPHVDET 0x184
#define INTEL_MSIC_ADPLVDET 0x185
#define INTEL_MSIC_ADPDETDBDM 0x186
#define INTEL_MSIC_LOWBATTDET 0x187
#define INTEL_MSIC_CHRCTRL 0x188
#define INTEL_MSIC_CHRCVOLTAGE 0x189
#define INTEL_MSIC_CHRCCURRENT 0x18a
#define INTEL_MSIC_SPCHARGER 0x18b
#define INTEL_MSIC_CHRTTIME 0x18c
#define INTEL_MSIC_CHRCTRL1 0x18d
#define INTEL_MSIC_PWRSRCLMT 0x18e
#define INTEL_MSIC_CHRSTWDT 0x18f
#define INTEL_MSIC_WDTWRITE 0x190 /* WO */
#define INTEL_MSIC_CHRSAFELMT 0x191
#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */
#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */
#define INTEL_MSIC_CHRLEDPWM 0x194
#define INTEL_MSIC_CHRLEDCTRL 0x195
/* ADC */
#define INTEL_MSIC_ADC1CNTL1 0x1c0
#define INTEL_MSIC_ADC1CNTL2 0x1c1
#define INTEL_MSIC_ADC1CNTL3 0x1c2
#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */
#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */
#define INTEL_MSIC_ADC1ADDR0 0x1c5
#define INTEL_MSIC_ADC1ADDR1 0x1c6
#define INTEL_MSIC_ADC1ADDR2 0x1c7
#define INTEL_MSIC_ADC1ADDR3 0x1c8
#define INTEL_MSIC_ADC1ADDR4 0x1c9
#define INTEL_MSIC_ADC1ADDR5 0x1ca
#define INTEL_MSIC_ADC1ADDR6 0x1cb
#define INTEL_MSIC_ADC1ADDR7 0x1cc
#define INTEL_MSIC_ADC1ADDR8 0x1cd
#define INTEL_MSIC_ADC1ADDR9 0x1ce
#define INTEL_MSIC_ADC1ADDR10 0x1cf
#define INTEL_MSIC_ADC1ADDR11 0x1d0
#define INTEL_MSIC_ADC1ADDR12 0x1d1
#define INTEL_MSIC_ADC1ADDR13 0x1d2
#define INTEL_MSIC_ADC1ADDR14 0x1d3
#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */
#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */
#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */
#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */
#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */
#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */
#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */
#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */
#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */
#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */
#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */
#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */
#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */
#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */
#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */
#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */
#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */
#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */
#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */
#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */
#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */
#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */
#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */
#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */
#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */
#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */
#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */
#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */
#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */
#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */
#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */
#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */
#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */
#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */
#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */
#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */
#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */
#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */
#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */
#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */
#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */
#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */
#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */
#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */
#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */
#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */
#define INTEL_MSIC_CCCNTL 0x202
#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */
#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */
#define INTEL_MSIC_CCADCHA 0x205 /* RO */
#define INTEL_MSIC_CCADCLA 0x206 /* RO */
/* AUDIO */
#define INTEL_MSIC_AUDPLLCTRL 0x240
#define INTEL_MSIC_DMICBUF0123 0x241
#define INTEL_MSIC_DMICBUF45 0x242
#define INTEL_MSIC_DMICGPO 0x244
#define INTEL_MSIC_DMICMUX 0x245
#define INTEL_MSIC_DMICCLK 0x246
#define INTEL_MSIC_MICBIAS 0x247
#define INTEL_MSIC_ADCCONFIG 0x248
#define INTEL_MSIC_MICAMP1 0x249
#define INTEL_MSIC_MICAMP2 0x24a
#define INTEL_MSIC_NOISEMUX 0x24b
#define INTEL_MSIC_AUDIOMUX12 0x24c
#define INTEL_MSIC_AUDIOMUX34 0x24d
#define INTEL_MSIC_AUDIOSINC 0x24e
#define INTEL_MSIC_AUDIOTXEN 0x24f
#define INTEL_MSIC_HSEPRXCTRL 0x250
#define INTEL_MSIC_IHFRXCTRL 0x251
#define INTEL_MSIC_VOICETXVOL 0x252
#define INTEL_MSIC_SIDETONEVOL 0x253
#define INTEL_MSIC_MUSICSHARVOL 0x254
#define INTEL_MSIC_VOICETXCTRL 0x255
#define INTEL_MSIC_HSMIXER 0x256
#define INTEL_MSIC_DACCONFIG 0x257
#define INTEL_MSIC_SOFTMUTE 0x258
#define INTEL_MSIC_HSLVOLCTRL 0x259
#define INTEL_MSIC_HSRVOLCTRL 0x25a
#define INTEL_MSIC_IHFLVOLCTRL 0x25b
#define INTEL_MSIC_IHFRVOLCTRL 0x25c
#define INTEL_MSIC_DRIVEREN 0x25d
#define INTEL_MSIC_LINEOUTCTRL 0x25e
#define INTEL_MSIC_VIB1CTRL1 0x25f
#define INTEL_MSIC_VIB1CTRL2 0x260
#define INTEL_MSIC_VIB1CTRL3 0x261
#define INTEL_MSIC_VIB1SPIPCM_1 0x262
#define INTEL_MSIC_VIB1SPIPCM_2 0x263
#define INTEL_MSIC_VIB1CTRL5 0x264
#define INTEL_MSIC_VIB2CTRL1 0x265
#define INTEL_MSIC_VIB2CTRL2 0x266
#define INTEL_MSIC_VIB2CTRL3 0x267
#define INTEL_MSIC_VIB2SPIPCM_1 0x268
#define INTEL_MSIC_VIB2SPIPCM_2 0x269
#define INTEL_MSIC_VIB2CTRL5 0x26a
#define INTEL_MSIC_BTNCTRL1 0x26b
#define INTEL_MSIC_BTNCTRL2 0x26c
#define INTEL_MSIC_PCM1TXSLOT01 0x26d
#define INTEL_MSIC_PCM1TXSLOT23 0x26e
#define INTEL_MSIC_PCM1TXSLOT45 0x26f
#define INTEL_MSIC_PCM1RXSLOT0123 0x270
#define INTEL_MSIC_PCM1RXSLOT045 0x271
#define INTEL_MSIC_PCM2TXSLOT01 0x272
#define INTEL_MSIC_PCM2TXSLOT23 0x273
#define INTEL_MSIC_PCM2TXSLOT45 0x274
#define INTEL_MSIC_PCM2RXSLOT01 0x275
#define INTEL_MSIC_PCM2RXSLOT23 0x276
#define INTEL_MSIC_PCM2RXSLOT45 0x277
#define INTEL_MSIC_PCM1CTRL1 0x278
#define INTEL_MSIC_PCM1CTRL2 0x279
#define INTEL_MSIC_PCM1CTRL3 0x27a
#define INTEL_MSIC_PCM2CTRL1 0x27b
#define INTEL_MSIC_PCM2CTRL2 0x27c
/* HDMI */
#define INTEL_MSIC_HDMIPUEN 0x280
#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */
/* Physical address of the start of the MSIC interrupt tree in SRAM */
#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0
/**
* struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
* @gpio_base: base number for the GPIOs
*/
struct intel_msic_gpio_pdata {
unsigned gpio_base;
};
/**
* struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
* @gpio: GPIO number used for OCD interrupts
*
* The MSIC MFD driver converts @gpio into an IRQ number and passes it to
* the OCD driver as %IORESOURCE_IRQ.
*/
struct intel_msic_ocd_pdata {
unsigned gpio;
};
/* MSIC embedded blocks (subdevices) */
enum intel_msic_block {
INTEL_MSIC_BLOCK_TOUCH,
INTEL_MSIC_BLOCK_ADC,
INTEL_MSIC_BLOCK_BATTERY,
INTEL_MSIC_BLOCK_GPIO,
INTEL_MSIC_BLOCK_AUDIO,
INTEL_MSIC_BLOCK_HDMI,
INTEL_MSIC_BLOCK_THERMAL,
INTEL_MSIC_BLOCK_POWER_BTN,
INTEL_MSIC_BLOCK_OCD,
INTEL_MSIC_BLOCK_LAST,
};
/**
* struct intel_msic_platform_data - platform data for the MSIC driver
* @irq: array of interrupt numbers, one per device. If @irq is set to %0
* for a given block, the corresponding platform device is not
* created. For devices which don't have an interrupt, use %0xff
* (this is same as in SFI spec).
* @gpio: platform data for the MSIC GPIO driver
* @ocd: platform data for the MSIC OCD driver
*
* Once the MSIC driver is initialized, the register interface is ready to
* use. All the platform devices for subdevices are created after the
* register interface is ready so that we can guarantee its availability to
* the subdevice drivers.
*
* Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
* resources of the created platform device.
*/
struct intel_msic_platform_data {
int irq[INTEL_MSIC_BLOCK_LAST];
struct intel_msic_gpio_pdata *gpio;
struct intel_msic_ocd_pdata *ocd;
};
struct intel_msic;
extern int intel_msic_reg_read(unsigned short reg, u8 *val);
extern int intel_msic_reg_write(unsigned short reg, u8 val);
extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
/*
* pdev_to_intel_msic - gets an MSIC instance from the platform device
* @pdev: platform device pointer
*
* The client drivers need to have pointer to the MSIC instance if they
* want to call intel_msic_irq_read(). This macro can be used for
* convenience to get the MSIC pointer from @pdev where needed. This is
* _only_ valid for devices which are managed by the MSIC.
*/
#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))
extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
u8 *val);
#endif /* __LINUX_MFD_INTEL_MSIC_H__ */

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include/linux/mfd/janz.h Normal file
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/*
* Common Definitions for Janz MODULbus devices
*
* Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef JANZ_H
#define JANZ_H
struct janz_platform_data {
/* MODULbus Module Number */
unsigned int modno;
};
/* PLX bridge chip onboard registers */
struct janz_cmodio_onboard_regs {
u8 unused1;
/*
* Read access: interrupt status
* Write access: interrupt disable
*/
u8 int_disable;
u8 unused2;
/*
* Read access: MODULbus number (hex switch)
* Write access: interrupt enable
*/
u8 int_enable;
u8 unused3;
/* write-only */
u8 reset_assert;
u8 unused4;
/* write-only */
u8 reset_deassert;
u8 unused5;
/* read-write access to serial EEPROM */
u8 eep;
u8 unused6;
/* write-only access to EEPROM chip select */
u8 enid;
};
#endif /* JANZ_H */

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/*
* lm3533.h -- LM3533 interface
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <jhovold@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_LM3533_H
#define __LINUX_MFD_LM3533_H
#define LM3533_ATTR_RO(_name) \
DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL)
#define LM3533_ATTR_RW(_name) \
DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
struct device;
struct regmap;
struct lm3533 {
struct device *dev;
struct regmap *regmap;
int gpio_hwen;
int irq;
unsigned have_als:1;
unsigned have_backlights:1;
unsigned have_leds:1;
};
struct lm3533_ctrlbank {
struct lm3533 *lm3533;
struct device *dev;
int id;
};
struct lm3533_als_platform_data {
unsigned pwm_mode:1; /* PWM input mode (default analog) */
u8 r_select; /* 1 - 127 (ignored in PWM-mode) */
};
struct lm3533_bl_platform_data {
char *name;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 default_brightness; /* 0 - 255 */
u8 pwm; /* 0 - 0x3f */
};
struct lm3533_led_platform_data {
char *name;
const char *default_trigger;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 pwm; /* 0 - 0x3f */
};
enum lm3533_boost_freq {
LM3533_BOOST_FREQ_500KHZ,
LM3533_BOOST_FREQ_1000KHZ,
};
enum lm3533_boost_ovp {
LM3533_BOOST_OVP_16V,
LM3533_BOOST_OVP_24V,
LM3533_BOOST_OVP_32V,
LM3533_BOOST_OVP_40V,
};
struct lm3533_platform_data {
int gpio_hwen;
enum lm3533_boost_ovp boost_ovp;
enum lm3533_boost_freq boost_freq;
struct lm3533_als_platform_data *als;
struct lm3533_bl_platform_data *backlights;
int num_backlights;
struct lm3533_led_platform_data *leds;
int num_leds;
};
extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb,
u16 imax);
extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val);
extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val);
extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_LM3533_H */

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include/linux/mfd/lp8788-isink.h Normal file
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/*
* TI LP8788 MFD - common definitions for current sinks
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ISINK_LP8788_H__
#define __ISINK_LP8788_H__
/* register address */
#define LP8788_ISINK_CTRL 0x99
#define LP8788_ISINK12_IOUT 0x9A
#define LP8788_ISINK3_IOUT 0x9B
#define LP8788_ISINK1_PWM 0x9C
#define LP8788_ISINK2_PWM 0x9D
#define LP8788_ISINK3_PWM 0x9E
/* mask bits */
#define LP8788_ISINK1_IOUT_M 0x0F /* Addr 9Ah */
#define LP8788_ISINK2_IOUT_M 0xF0
#define LP8788_ISINK3_IOUT_M 0x0F /* Addr 9Bh */
/* 6 bits used for PWM code : Addr 9C ~ 9Eh */
#define LP8788_ISINK_MAX_PWM 63
#define LP8788_ISINK_SCALE_OFFSET 3
static const u8 lp8788_iout_addr[] = {
LP8788_ISINK12_IOUT,
LP8788_ISINK12_IOUT,
LP8788_ISINK3_IOUT,
};
static const u8 lp8788_iout_mask[] = {
LP8788_ISINK1_IOUT_M,
LP8788_ISINK2_IOUT_M,
LP8788_ISINK3_IOUT_M,
};
static const u8 lp8788_pwm_addr[] = {
LP8788_ISINK1_PWM,
LP8788_ISINK2_PWM,
LP8788_ISINK3_PWM,
};
#endif

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include/linux/mfd/lp8788.h Normal file
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/*
* TI LP8788 MFD Device
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __MFD_LP8788_H__
#define __MFD_LP8788_H__
#include <linux/gpio.h>
#include <linux/irqdomain.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#define LP8788_DEV_BUCK "lp8788-buck"
#define LP8788_DEV_DLDO "lp8788-dldo"
#define LP8788_DEV_ALDO "lp8788-aldo"
#define LP8788_DEV_CHARGER "lp8788-charger"
#define LP8788_DEV_RTC "lp8788-rtc"
#define LP8788_DEV_BACKLIGHT "lp8788-backlight"
#define LP8788_DEV_VIBRATOR "lp8788-vibrator"
#define LP8788_DEV_KEYLED "lp8788-keyled"
#define LP8788_DEV_ADC "lp8788-adc"
#define LP8788_NUM_BUCKS 4
#define LP8788_NUM_DLDOS 12
#define LP8788_NUM_ALDOS 10
#define LP8788_NUM_BUCK2_DVS 2
#define LP8788_CHG_IRQ "CHG_IRQ"
#define LP8788_PRSW_IRQ "PRSW_IRQ"
#define LP8788_BATT_IRQ "BATT_IRQ"
#define LP8788_ALM_IRQ "ALARM_IRQ"
enum lp8788_int_id {
/* interrup register 1 : Addr 00h */
LP8788_INT_TSDL,
LP8788_INT_TSDH,
LP8788_INT_UVLO,
LP8788_INT_FLAGMON,
LP8788_INT_PWRON_TIME,
LP8788_INT_PWRON,
LP8788_INT_COMP1,
LP8788_INT_COMP2,
/* interrupt register 2 : Addr 01h */
LP8788_INT_CHG_INPUT_STATE,
LP8788_INT_CHG_STATE,
LP8788_INT_EOC,
LP8788_INT_CHG_RESTART,
LP8788_INT_RESTART_TIMEOUT,
LP8788_INT_FULLCHG_TIMEOUT,
LP8788_INT_PRECHG_TIMEOUT,
/* interrupt register 3 : Addr 02h */
LP8788_INT_RTC_ALARM1 = 17,
LP8788_INT_RTC_ALARM2,
LP8788_INT_ENTER_SYS_SUPPORT,
LP8788_INT_EXIT_SYS_SUPPORT,
LP8788_INT_BATT_LOW,
LP8788_INT_NO_BATT,
LP8788_INT_MAX = 24,
};
enum lp8788_dvs_sel {
DVS_SEL_V0,
DVS_SEL_V1,
DVS_SEL_V2,
DVS_SEL_V3,
};
enum lp8788_ext_ldo_en_id {
EN_ALDO1,
EN_ALDO234,
EN_ALDO5,
EN_ALDO7,
EN_DLDO7,
EN_DLDO911,
EN_LDOS_MAX,
};
enum lp8788_charger_event {
NO_CHARGER,
CHARGER_DETECTED,
};
enum lp8788_bl_ctrl_mode {
LP8788_BL_REGISTER_ONLY,
LP8788_BL_COMB_PWM_BASED, /* PWM + I2C, changed by PWM input */
LP8788_BL_COMB_REGISTER_BASED, /* PWM + I2C, changed by I2C */
};
enum lp8788_bl_dim_mode {
LP8788_DIM_EXPONENTIAL,
LP8788_DIM_LINEAR,
};
enum lp8788_bl_full_scale_current {
LP8788_FULLSCALE_5000uA,
LP8788_FULLSCALE_8500uA,
LP8788_FULLSCALE_1200uA,
LP8788_FULLSCALE_1550uA,
LP8788_FULLSCALE_1900uA,
LP8788_FULLSCALE_2250uA,
LP8788_FULLSCALE_2600uA,
LP8788_FULLSCALE_2950uA,
};
enum lp8788_bl_ramp_step {
LP8788_RAMP_8us,
LP8788_RAMP_1024us,
LP8788_RAMP_2048us,
LP8788_RAMP_4096us,
LP8788_RAMP_8192us,
LP8788_RAMP_16384us,
LP8788_RAMP_32768us,
LP8788_RAMP_65538us,
};
enum lp8788_isink_scale {
LP8788_ISINK_SCALE_100mA,
LP8788_ISINK_SCALE_120mA,
};
enum lp8788_isink_number {
LP8788_ISINK_1,
LP8788_ISINK_2,
LP8788_ISINK_3,
};
enum lp8788_alarm_sel {
LP8788_ALARM_1,
LP8788_ALARM_2,
LP8788_ALARM_MAX,
};
enum lp8788_adc_id {
LPADC_VBATT_5P5,
LPADC_VIN_CHG,
LPADC_IBATT,
LPADC_IC_TEMP,
LPADC_VBATT_6P0,
LPADC_VBATT_5P0,
LPADC_ADC1,
LPADC_ADC2,
LPADC_VDD,
LPADC_VCOIN,
LPADC_VDD_LDO,
LPADC_ADC3,
LPADC_ADC4,
LPADC_MAX,
};
struct lp8788;
/*
* lp8788_buck1_dvs
* @gpio : gpio pin number for dvs control
* @vsel : dvs selector for buck v1 register
*/
struct lp8788_buck1_dvs {
int gpio;
enum lp8788_dvs_sel vsel;
};
/*
* lp8788_buck2_dvs
* @gpio : two gpio pin numbers are used for dvs
* @vsel : dvs selector for buck v2 register
*/
struct lp8788_buck2_dvs {
int gpio[LP8788_NUM_BUCK2_DVS];
enum lp8788_dvs_sel vsel;
};
/*
* struct lp8788_ldo_enable_pin
*
* Basically, all LDOs are enabled through the I2C commands.
* But ALDO 1 ~ 5, 7, DLDO 7, 9, 11 can be enabled by external gpio pins.
*
* @gpio : gpio number which is used for enabling ldos
* @init_state : initial gpio state (ex. GPIOF_OUT_INIT_LOW)
*/
struct lp8788_ldo_enable_pin {
int gpio;
int init_state;
};
/*
* struct lp8788_chg_param
* @addr : charging control register address (range : 0x11 ~ 0x1C)
* @val : charging parameter value
*/
struct lp8788_chg_param {
u8 addr;
u8 val;
};
/*
* struct lp8788_charger_platform_data
* @adc_vbatt : adc channel name for battery voltage
* @adc_batt_temp : adc channel name for battery temperature
* @max_vbatt_mv : used for calculating battery capacity
* @chg_params : initial charging parameters
* @num_chg_params : numbers of charging parameters
* @charger_event : the charger event can be reported to the platform side
*/
struct lp8788_charger_platform_data {
const char *adc_vbatt;
const char *adc_batt_temp;
unsigned int max_vbatt_mv;
struct lp8788_chg_param *chg_params;
int num_chg_params;
void (*charger_event) (struct lp8788 *lp,
enum lp8788_charger_event event);
};
/*
* struct lp8788_backlight_platform_data
* @name : backlight driver name. (default: "lcd-backlight")
* @initial_brightness : initial value of backlight brightness
* @bl_mode : brightness control by pwm or lp8788 register
* @dim_mode : dimming mode selection
* @full_scale : full scale current setting
* @rise_time : brightness ramp up step time
* @fall_time : brightness ramp down step time
* @pwm_pol : pwm polarity setting when bl_mode is pwm based
* @period_ns : platform specific pwm period value. unit is nano.
Only valid when bl_mode is LP8788_BL_COMB_PWM_BASED
*/
struct lp8788_backlight_platform_data {
char *name;
int initial_brightness;
enum lp8788_bl_ctrl_mode bl_mode;
enum lp8788_bl_dim_mode dim_mode;
enum lp8788_bl_full_scale_current full_scale;
enum lp8788_bl_ramp_step rise_time;
enum lp8788_bl_ramp_step fall_time;
enum pwm_polarity pwm_pol;
unsigned int period_ns;
};
/*
* struct lp8788_led_platform_data
* @name : led driver name. (default: "keyboard-backlight")
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
*/
struct lp8788_led_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
};
/*
* struct lp8788_vib_platform_data
* @name : vibrator driver name
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
* @pwm_code : PWM code value (Addr 9Ch ~ 9Eh)
*/
struct lp8788_vib_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
int pwm_code;
};
/*
* struct lp8788_platform_data
* @init_func : used for initializing registers
* before mfd driver is registered
* @buck_data : regulator initial data for buck
* @dldo_data : regulator initial data for digital ldo
* @aldo_data : regulator initial data for analog ldo
* @buck1_dvs : gpio configurations for buck1 dvs
* @buck2_dvs : gpio configurations for buck2 dvs
* @ldo_pin : gpio configurations for enabling LDOs
* @chg_pdata : platform data for charger driver
* @alarm_sel : rtc alarm selection (1 or 2)
* @bl_pdata : configurable data for backlight driver
* @led_pdata : configurable data for led driver
* @vib_pdata : configurable data for vibrator driver
* @adc_pdata : iio map data for adc driver
*/
struct lp8788_platform_data {
/* general system information */
int (*init_func) (struct lp8788 *lp);
/* regulators */
struct regulator_init_data *buck_data[LP8788_NUM_BUCKS];
struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS];
struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS];
struct lp8788_buck1_dvs *buck1_dvs;
struct lp8788_buck2_dvs *buck2_dvs;
struct lp8788_ldo_enable_pin *ldo_pin[EN_LDOS_MAX];
/* charger */
struct lp8788_charger_platform_data *chg_pdata;
/* rtc alarm */
enum lp8788_alarm_sel alarm_sel;
/* backlight */
struct lp8788_backlight_platform_data *bl_pdata;
/* current sinks */
struct lp8788_led_platform_data *led_pdata;
struct lp8788_vib_platform_data *vib_pdata;
/* adc iio map data */
struct iio_map *adc_pdata;
};
/*
* struct lp8788
* @dev : parent device pointer
* @regmap : used for i2c communcation on accessing registers
* @irqdm : interrupt domain for handling nested interrupt
* @irq : pin number of IRQ_N
* @pdata : lp8788 platform specific data
*/
struct lp8788 {
struct device *dev;
struct regmap *regmap;
struct irq_domain *irqdm;
int irq;
struct lp8788_platform_data *pdata;
};
int lp8788_irq_init(struct lp8788 *lp, int chip_irq);
void lp8788_irq_exit(struct lp8788 *lp);
int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data);
int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count);
int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data);
int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data);
#endif

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/*
* linux/drivers/mfd/lpc_ich.h
*
* Copyright (c) 2012 Extreme Engineering Solution, Inc.
* Author: Aaron Sierra <asierra@xes-inc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License 2 as published
* by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef LPC_ICH_H
#define LPC_ICH_H
/* Watchdog resources */
#define ICH_RES_IO_TCO 0
#define ICH_RES_IO_SMI 1
#define ICH_RES_MEM_OFF 2
#define ICH_RES_MEM_GCS 0
/* GPIO resources */
#define ICH_RES_GPIO 0
#define ICH_RES_GPE0 1
/* GPIO compatibility */
#define ICH_I3100_GPIO 0x401
#define ICH_V5_GPIO 0x501
#define ICH_V6_GPIO 0x601
#define ICH_V7_GPIO 0x701
#define ICH_V9_GPIO 0x801
#define ICH_V10CORP_GPIO 0xa01
#define ICH_V10CONS_GPIO 0xa11
struct lpc_ich_info {
char name[32];
unsigned int iTCO_version;
unsigned int gpio_version;
u8 use_gpio;
};
#endif

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/*
* max77686.h - Voltage regulator driver for the Maxim 77686
*
* Copyright (C) 2012 Samsung Electrnoics
* Chiwoong Byun <woong.byun@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX77686_PRIV_H
#define __LINUX_MFD_MAX77686_PRIV_H
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/module.h>
#define MAX77686_REG_INVALID (0xff)
enum max77686_pmic_reg {
MAX77686_REG_DEVICE_ID = 0x00,
MAX77686_REG_INTSRC = 0x01,
MAX77686_REG_INT1 = 0x02,
MAX77686_REG_INT2 = 0x03,
MAX77686_REG_INT1MSK = 0x04,
MAX77686_REG_INT2MSK = 0x05,
MAX77686_REG_STATUS1 = 0x06,
MAX77686_REG_STATUS2 = 0x07,
MAX77686_REG_PWRON = 0x08,
MAX77686_REG_ONOFF_DELAY = 0x09,
MAX77686_REG_MRSTB = 0x0A,
/* Reserved: 0x0B-0x0F */
MAX77686_REG_BUCK1CTRL = 0x10,
MAX77686_REG_BUCK1OUT = 0x11,
MAX77686_REG_BUCK2CTRL1 = 0x12,
MAX77686_REG_BUCK234FREQ = 0x13,
MAX77686_REG_BUCK2DVS1 = 0x14,
MAX77686_REG_BUCK2DVS2 = 0x15,
MAX77686_REG_BUCK2DVS3 = 0x16,
MAX77686_REG_BUCK2DVS4 = 0x17,
MAX77686_REG_BUCK2DVS5 = 0x18,
MAX77686_REG_BUCK2DVS6 = 0x19,
MAX77686_REG_BUCK2DVS7 = 0x1A,
MAX77686_REG_BUCK2DVS8 = 0x1B,
MAX77686_REG_BUCK3CTRL1 = 0x1C,
/* Reserved: 0x1D */
MAX77686_REG_BUCK3DVS1 = 0x1E,
MAX77686_REG_BUCK3DVS2 = 0x1F,
MAX77686_REG_BUCK3DVS3 = 0x20,
MAX77686_REG_BUCK3DVS4 = 0x21,
MAX77686_REG_BUCK3DVS5 = 0x22,
MAX77686_REG_BUCK3DVS6 = 0x23,
MAX77686_REG_BUCK3DVS7 = 0x24,
MAX77686_REG_BUCK3DVS8 = 0x25,
MAX77686_REG_BUCK4CTRL1 = 0x26,
/* Reserved: 0x27 */
MAX77686_REG_BUCK4DVS1 = 0x28,
MAX77686_REG_BUCK4DVS2 = 0x29,
MAX77686_REG_BUCK4DVS3 = 0x2A,
MAX77686_REG_BUCK4DVS4 = 0x2B,
MAX77686_REG_BUCK4DVS5 = 0x2C,
MAX77686_REG_BUCK4DVS6 = 0x2D,
MAX77686_REG_BUCK4DVS7 = 0x2E,
MAX77686_REG_BUCK4DVS8 = 0x2F,
MAX77686_REG_BUCK5CTRL = 0x30,
MAX77686_REG_BUCK5OUT = 0x31,
MAX77686_REG_BUCK6CTRL = 0x32,
MAX77686_REG_BUCK6OUT = 0x33,
MAX77686_REG_BUCK7CTRL = 0x34,
MAX77686_REG_BUCK7OUT = 0x35,
MAX77686_REG_BUCK8CTRL = 0x36,
MAX77686_REG_BUCK8OUT = 0x37,
MAX77686_REG_BUCK9CTRL = 0x38,
MAX77686_REG_BUCK9OUT = 0x39,
/* Reserved: 0x3A-0x3F */
MAX77686_REG_LDO1CTRL1 = 0x40,
MAX77686_REG_LDO2CTRL1 = 0x41,
MAX77686_REG_LDO3CTRL1 = 0x42,
MAX77686_REG_LDO4CTRL1 = 0x43,
MAX77686_REG_LDO5CTRL1 = 0x44,
MAX77686_REG_LDO6CTRL1 = 0x45,
MAX77686_REG_LDO7CTRL1 = 0x46,
MAX77686_REG_LDO8CTRL1 = 0x47,
MAX77686_REG_LDO9CTRL1 = 0x48,
MAX77686_REG_LDO10CTRL1 = 0x49,
MAX77686_REG_LDO11CTRL1 = 0x4A,
MAX77686_REG_LDO12CTRL1 = 0x4B,
MAX77686_REG_LDO13CTRL1 = 0x4C,
MAX77686_REG_LDO14CTRL1 = 0x4D,
MAX77686_REG_LDO15CTRL1 = 0x4E,
MAX77686_REG_LDO16CTRL1 = 0x4F,
MAX77686_REG_LDO17CTRL1 = 0x50,
MAX77686_REG_LDO18CTRL1 = 0x51,
MAX77686_REG_LDO19CTRL1 = 0x52,
MAX77686_REG_LDO20CTRL1 = 0x53,
MAX77686_REG_LDO21CTRL1 = 0x54,
MAX77686_REG_LDO22CTRL1 = 0x55,
MAX77686_REG_LDO23CTRL1 = 0x56,
MAX77686_REG_LDO24CTRL1 = 0x57,
MAX77686_REG_LDO25CTRL1 = 0x58,
MAX77686_REG_LDO26CTRL1 = 0x59,
/* Reserved: 0x5A-0x5F */
MAX77686_REG_LDO1CTRL2 = 0x60,
MAX77686_REG_LDO2CTRL2 = 0x61,
MAX77686_REG_LDO3CTRL2 = 0x62,
MAX77686_REG_LDO4CTRL2 = 0x63,
MAX77686_REG_LDO5CTRL2 = 0x64,
MAX77686_REG_LDO6CTRL2 = 0x65,
MAX77686_REG_LDO7CTRL2 = 0x66,
MAX77686_REG_LDO8CTRL2 = 0x67,
MAX77686_REG_LDO9CTRL2 = 0x68,
MAX77686_REG_LDO10CTRL2 = 0x69,
MAX77686_REG_LDO11CTRL2 = 0x6A,
MAX77686_REG_LDO12CTRL2 = 0x6B,
MAX77686_REG_LDO13CTRL2 = 0x6C,
MAX77686_REG_LDO14CTRL2 = 0x6D,
MAX77686_REG_LDO15CTRL2 = 0x6E,
MAX77686_REG_LDO16CTRL2 = 0x6F,
MAX77686_REG_LDO17CTRL2 = 0x70,
MAX77686_REG_LDO18CTRL2 = 0x71,
MAX77686_REG_LDO19CTRL2 = 0x72,
MAX77686_REG_LDO20CTRL2 = 0x73,
MAX77686_REG_LDO21CTRL2 = 0x74,
MAX77686_REG_LDO22CTRL2 = 0x75,
MAX77686_REG_LDO23CTRL2 = 0x76,
MAX77686_REG_LDO24CTRL2 = 0x77,
MAX77686_REG_LDO25CTRL2 = 0x78,
MAX77686_REG_LDO26CTRL2 = 0x79,
/* Reserved: 0x7A-0x7D */
MAX77686_REG_BBAT_CHG = 0x7E,
MAX77686_REG_32KHZ = 0x7F,
MAX77686_REG_PMIC_END = 0x80,
};
enum max77686_rtc_reg {
MAX77686_RTC_INT = 0x00,
MAX77686_RTC_INTM = 0x01,
MAX77686_RTC_CONTROLM = 0x02,
MAX77686_RTC_CONTROL = 0x03,
MAX77686_RTC_UPDATE0 = 0x04,
/* Reserved: 0x5 */
MAX77686_WTSR_SMPL_CNTL = 0x06,
MAX77686_RTC_SEC = 0x07,
MAX77686_RTC_MIN = 0x08,
MAX77686_RTC_HOUR = 0x09,
MAX77686_RTC_WEEKDAY = 0x0A,
MAX77686_RTC_MONTH = 0x0B,
MAX77686_RTC_YEAR = 0x0C,
MAX77686_RTC_DATE = 0x0D,
MAX77686_ALARM1_SEC = 0x0E,
MAX77686_ALARM1_MIN = 0x0F,
MAX77686_ALARM1_HOUR = 0x10,
MAX77686_ALARM1_WEEKDAY = 0x11,
MAX77686_ALARM1_MONTH = 0x12,
MAX77686_ALARM1_YEAR = 0x13,
MAX77686_ALARM1_DATE = 0x14,
MAX77686_ALARM2_SEC = 0x15,
MAX77686_ALARM2_MIN = 0x16,
MAX77686_ALARM2_HOUR = 0x17,
MAX77686_ALARM2_WEEKDAY = 0x18,
MAX77686_ALARM2_MONTH = 0x19,
MAX77686_ALARM2_YEAR = 0x1A,
MAX77686_ALARM2_DATE = 0x1B,
};
#define MAX77686_IRQSRC_PMIC (0)
#define MAX77686_IRQSRC_RTC (1 << 0)
enum max77686_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
RTC_INT,
MAX77686_IRQ_GROUP_NR,
};
enum max77686_irq {
MAX77686_PMICIRQ_PWRONF,
MAX77686_PMICIRQ_PWRONR,
MAX77686_PMICIRQ_JIGONBF,
MAX77686_PMICIRQ_JIGONBR,
MAX77686_PMICIRQ_ACOKBF,
MAX77686_PMICIRQ_ACOKBR,
MAX77686_PMICIRQ_ONKEY1S,
MAX77686_PMICIRQ_MRSTB,
MAX77686_PMICIRQ_140C,
MAX77686_PMICIRQ_120C,
MAX77686_RTCIRQ_RTC60S,
MAX77686_RTCIRQ_RTCA1,
MAX77686_RTCIRQ_RTCA2,
MAX77686_RTCIRQ_SMPL,
MAX77686_RTCIRQ_RTC1S,
MAX77686_RTCIRQ_WTSR,
MAX77686_IRQ_NR,
};
struct max77686_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
struct i2c_client *rtc; /* slave addr 0x0c */
int type;
struct regmap *regmap; /* regmap for mfd */
struct regmap *rtc_regmap; /* regmap for rtc */
struct irq_domain *irq_domain;
int irq;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
};
enum max77686_types {
TYPE_MAX77686,
};
extern int max77686_irq_init(struct max77686_dev *max77686);
extern void max77686_irq_exit(struct max77686_dev *max77686);
extern int max77686_irq_resume(struct max77686_dev *max77686);
#endif /* __LINUX_MFD_MAX77686_PRIV_H */

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/*
* max77686.h - Driver for the Maxim 77686
*
* Copyright (C) 2012 Samsung Electrnoics
* Chiwoong Byun <woong.byun@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8997.h
*
* MAX77686 has PMIC, RTC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __LINUX_MFD_MAX77686_H
#define __LINUX_MFD_MAX77686_H
#include <linux/regulator/consumer.h>
/* MAX77686 regulator IDs */
enum max77686_regulators {
MAX77686_LDO1 = 0,
MAX77686_LDO2,
MAX77686_LDO3,
MAX77686_LDO4,
MAX77686_LDO5,
MAX77686_LDO6,
MAX77686_LDO7,
MAX77686_LDO8,
MAX77686_LDO9,
MAX77686_LDO10,
MAX77686_LDO11,
MAX77686_LDO12,
MAX77686_LDO13,
MAX77686_LDO14,
MAX77686_LDO15,
MAX77686_LDO16,
MAX77686_LDO17,
MAX77686_LDO18,
MAX77686_LDO19,
MAX77686_LDO20,
MAX77686_LDO21,
MAX77686_LDO22,
MAX77686_LDO23,
MAX77686_LDO24,
MAX77686_LDO25,
MAX77686_LDO26,
MAX77686_BUCK1,
MAX77686_BUCK2,
MAX77686_BUCK3,
MAX77686_BUCK4,
MAX77686_BUCK5,
MAX77686_BUCK6,
MAX77686_BUCK7,
MAX77686_BUCK8,
MAX77686_BUCK9,
MAX77686_REG_MAX,
};
struct max77686_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *of_node;
};
enum max77686_opmode {
MAX77686_OPMODE_NORMAL,
MAX77686_OPMODE_LP,
MAX77686_OPMODE_STANDBY,
};
struct max77686_opmode_data {
int id;
int mode;
};
struct max77686_platform_data {
/* IRQ */
int irq_gpio;
int ono;
int wakeup;
/* ---- PMIC ---- */
struct max77686_regulator_data *regulators;
int num_regulators;
struct max77686_opmode_data *opmode_data;
/*
* GPIO-DVS feature is not enabled with the current version of
* MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
* voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
*/
int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
unsigned int buck3_voltage[8];
unsigned int buck4_voltage[8];
};
#endif /* __LINUX_MFD_MAX77686_H */

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/*
* max77693-private.h - Voltage regulator driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electrnoics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX77693_PRIV_H
#define __LINUX_MFD_MAX77693_PRIV_H
#include <linux/i2c.h>
#define MAX77693_NUM_IRQ_MUIC_REGS 3
#define MAX77693_REG_INVALID (0xff)
/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
enum max77693_pmic_reg {
MAX77693_LED_REG_IFLASH1 = 0x00,
MAX77693_LED_REG_IFLASH2 = 0x01,
MAX77693_LED_REG_ITORCH = 0x02,
MAX77693_LED_REG_ITORCHTIMER = 0x03,
MAX77693_LED_REG_FLASH_TIMER = 0x04,
MAX77693_LED_REG_FLASH_EN = 0x05,
MAX77693_LED_REG_MAX_FLASH1 = 0x06,
MAX77693_LED_REG_MAX_FLASH2 = 0x07,
MAX77693_LED_REG_MAX_FLASH3 = 0x08,
MAX77693_LED_REG_MAX_FLASH4 = 0x09,
MAX77693_LED_REG_VOUT_CNTL = 0x0A,
MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
MAX77693_LED_REG_FLASH_INT = 0x0E,
MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
MAX77693_LED_REG_FLASH_INT_STATUS = 0x10,
MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
MAX77693_PMIC_REG_INTSRC = 0x22,
MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
MAX77693_PMIC_REG_LSCNFG = 0x2B,
MAX77693_CHG_REG_CHG_INT = 0xB0,
MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
MAX77693_PMIC_REG_END,
};
/* Slave addr = 0x4A: MUIC */
enum max77693_muic_reg {
MAX77693_MUIC_REG_ID = 0x00,
MAX77693_MUIC_REG_INT1 = 0x01,
MAX77693_MUIC_REG_INT2 = 0x02,
MAX77693_MUIC_REG_INT3 = 0x03,
MAX77693_MUIC_REG_STATUS1 = 0x04,
MAX77693_MUIC_REG_STATUS2 = 0x05,
MAX77693_MUIC_REG_STATUS3 = 0x06,
MAX77693_MUIC_REG_INTMASK1 = 0x07,
MAX77693_MUIC_REG_INTMASK2 = 0x08,
MAX77693_MUIC_REG_INTMASK3 = 0x09,
MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
MAX77693_MUIC_REG_CTRL1 = 0x0C,
MAX77693_MUIC_REG_CTRL2 = 0x0D,
MAX77693_MUIC_REG_CTRL3 = 0x0E,
MAX77693_MUIC_REG_END,
};
/* MAX77693 INTMASK1~2 Register */
#define INTMASK1_ADC1K_SHIFT 3
#define INTMASK1_ADCERR_SHIFT 2
#define INTMASK1_ADCLOW_SHIFT 1
#define INTMASK1_ADC_SHIFT 0
#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
#define INTMASK2_VIDRM_SHIFT 5
#define INTMASK2_VBVOLT_SHIFT 4
#define INTMASK2_DXOVP_SHIFT 3
#define INTMASK2_DCDTMR_SHIFT 2
#define INTMASK2_CHGDETRUN_SHIFT 1
#define INTMASK2_CHGTYP_SHIFT 0
#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
/* MAX77693 MUIC - STATUS1~3 Register */
#define STATUS1_ADC_SHIFT (0)
#define STATUS1_ADCLOW_SHIFT (5)
#define STATUS1_ADCERR_SHIFT (6)
#define STATUS1_ADC1K_SHIFT (7)
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
#define STATUS2_CHGTYP_SHIFT (0)
#define STATUS2_CHGDETRUN_SHIFT (3)
#define STATUS2_DCDTMR_SHIFT (4)
#define STATUS2_DXOVP_SHIFT (5)
#define STATUS2_VBVOLT_SHIFT (6)
#define STATUS2_VIDRM_SHIFT (7)
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
#define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
#define STATUS3_OVP_SHIFT (2)
#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
/* MAX77693 CDETCTRL1~2 register */
#define CDETCTRL1_CHGDETEN_SHIFT (0)
#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
#define CDETCTRL1_DCDEN_SHIFT (2)
#define CDETCTRL1_DCD2SCT_SHIFT (3)
#define CDETCTRL1_CDDELAY_SHIFT (4)
#define CDETCTRL1_DCDCPL_SHIFT (5)
#define CDETCTRL1_CDPDET_SHIFT (7)
#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
#define CDETCTRL2_VIDRMEN_SHIFT (1)
#define CDETCTRL2_DXOVPEN_SHIFT (3)
#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
/* MAX77693 MUIC - CONTROL1~3 register */
#define COMN1SW_SHIFT (0)
#define COMP2SW_SHIFT (3)
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
| (1 << COMN1SW_SHIFT))
#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
| (2 << COMN1SW_SHIFT))
#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
| (3 << COMN1SW_SHIFT))
#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
| (0 << COMN1SW_SHIFT))
#define CONTROL2_LOWPWR_SHIFT (0)
#define CONTROL2_ADCEN_SHIFT (1)
#define CONTROL2_CPEN_SHIFT (2)
#define CONTROL2_SFOUTASRT_SHIFT (3)
#define CONTROL2_SFOUTORD_SHIFT (4)
#define CONTROL2_ACCDET_SHIFT (5)
#define CONTROL2_USBCPINT_SHIFT (6)
#define CONTROL2_RCPS_SHIFT (7)
#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
#define CONTROL3_JIGSET_SHIFT (0)
#define CONTROL3_BTLDSET_SHIFT (2)
#define CONTROL3_ADCDBSET_SHIFT (4)
#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
/* Slave addr = 0x90: Haptic */
enum max77693_haptic_reg {
MAX77693_HAPTIC_REG_STATUS = 0x00,
MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
MAX77693_HAPTIC_REG_REV = 0x10,
MAX77693_HAPTIC_REG_END,
};
enum max77693_irq_source {
LED_INT = 0,
TOPSYS_INT,
CHG_INT,
MUIC_INT1,
MUIC_INT2,
MUIC_INT3,
MAX77693_IRQ_GROUP_NR,
};
enum max77693_irq {
/* PMIC - FLASH */
MAX77693_LED_IRQ_FLED2_OPEN,
MAX77693_LED_IRQ_FLED2_SHORT,
MAX77693_LED_IRQ_FLED1_OPEN,
MAX77693_LED_IRQ_FLED1_SHORT,
MAX77693_LED_IRQ_MAX_FLASH,
/* PMIC - TOPSYS */
MAX77693_TOPSYS_IRQ_T120C_INT,
MAX77693_TOPSYS_IRQ_T140C_INT,
MAX77693_TOPSYS_IRQ_LOWSYS_INT,
/* PMIC - Charger */
MAX77693_CHG_IRQ_BYP_I,
MAX77693_CHG_IRQ_THM_I,
MAX77693_CHG_IRQ_BAT_I,
MAX77693_CHG_IRQ_CHG_I,
MAX77693_CHG_IRQ_CHGIN_I,
/* MUIC INT1 */
MAX77693_MUIC_IRQ_INT1_ADC,
MAX77693_MUIC_IRQ_INT1_ADC_LOW,
MAX77693_MUIC_IRQ_INT1_ADC_ERR,
MAX77693_MUIC_IRQ_INT1_ADC1K,
/* MUIC INT2 */
MAX77693_MUIC_IRQ_INT2_CHGTYP,
MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
MAX77693_MUIC_IRQ_INT2_DCDTMR,
MAX77693_MUIC_IRQ_INT2_DXOVP,
MAX77693_MUIC_IRQ_INT2_VBVOLT,
MAX77693_MUIC_IRQ_INT2_VIDRM,
/* MUIC INT3 */
MAX77693_MUIC_IRQ_INT3_EOC,
MAX77693_MUIC_IRQ_INT3_CGMBC,
MAX77693_MUIC_IRQ_INT3_OVP,
MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
MAX77693_MUIC_IRQ_INT3_BAT_DET,
MAX77693_IRQ_NR,
};
struct max77693_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
struct i2c_client *muic; /* 0x4A , MUIC */
struct i2c_client *haptic; /* 0x90 , Haptic */
int type;
struct regmap *regmap;
struct regmap *regmap_muic;
struct regmap *regmap_haptic;
struct irq_domain *irq_domain;
int irq;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
};
enum max77693_types {
TYPE_MAX77693,
};
extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
u8 *buf);
extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
u8 *buf);
extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
extern int max77693_irq_init(struct max77693_dev *max77686);
extern void max77693_irq_exit(struct max77693_dev *max77686);
extern int max77693_irq_resume(struct max77693_dev *max77686);
#endif /* __LINUX_MFD_MAX77693_PRIV_H */

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/*
* max77693.h - Driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electrnoics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8997.h
*
* MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __LINUX_MFD_MAX77693_H
#define __LINUX_MFD_MAX77693_H
struct max77693_reg_data {
u8 addr;
u8 data;
};
struct max77693_muic_platform_data {
struct max77693_reg_data *init_data;
int num_init_data;
int detcable_delay_ms;
/*
* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
* h/w path of COMP2/COMN1 on CONTROL1 register.
*/
int path_usb;
int path_uart;
};
struct max77693_platform_data {
int wakeup;
/* muic data */
struct max77693_muic_platform_data *muic_data;
};
#endif /* __LINUX_MFD_MAX77693_H */

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/*
* Functions to access MAX8907 power management chip.
*
* Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
* Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_MAX8907_H
#define __LINUX_MFD_MAX8907_H
#include <linux/mutex.h>
#include <linux/pm.h>
#define MAX8907_GEN_I2C_ADDR (0x78 >> 1)
#define MAX8907_ADC_I2C_ADDR (0x8e >> 1)
#define MAX8907_RTC_I2C_ADDR (0xd0 >> 1)
/* MAX8907 register map */
#define MAX8907_REG_SYSENSEL 0x00
#define MAX8907_REG_ON_OFF_IRQ1 0x01
#define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02
#define MAX8907_REG_ON_OFF_STAT 0x03
#define MAX8907_REG_SDCTL1 0x04
#define MAX8907_REG_SDSEQCNT1 0x05
#define MAX8907_REG_SDV1 0x06
#define MAX8907_REG_SDCTL2 0x07
#define MAX8907_REG_SDSEQCNT2 0x08
#define MAX8907_REG_SDV2 0x09
#define MAX8907_REG_SDCTL3 0x0A
#define MAX8907_REG_SDSEQCNT3 0x0B
#define MAX8907_REG_SDV3 0x0C
#define MAX8907_REG_ON_OFF_IRQ2 0x0D
#define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E
#define MAX8907_REG_RESET_CNFG 0x0F
#define MAX8907_REG_LDOCTL16 0x10
#define MAX8907_REG_LDOSEQCNT16 0x11
#define MAX8907_REG_LDO16VOUT 0x12
#define MAX8907_REG_SDBYSEQCNT 0x13
#define MAX8907_REG_LDOCTL17 0x14
#define MAX8907_REG_LDOSEQCNT17 0x15
#define MAX8907_REG_LDO17VOUT 0x16
#define MAX8907_REG_LDOCTL1 0x18
#define MAX8907_REG_LDOSEQCNT1 0x19
#define MAX8907_REG_LDO1VOUT 0x1A
#define MAX8907_REG_LDOCTL2 0x1C
#define MAX8907_REG_LDOSEQCNT2 0x1D
#define MAX8907_REG_LDO2VOUT 0x1E
#define MAX8907_REG_LDOCTL3 0x20
#define MAX8907_REG_LDOSEQCNT3 0x21
#define MAX8907_REG_LDO3VOUT 0x22
#define MAX8907_REG_LDOCTL4 0x24
#define MAX8907_REG_LDOSEQCNT4 0x25
#define MAX8907_REG_LDO4VOUT 0x26
#define MAX8907_REG_LDOCTL5 0x28
#define MAX8907_REG_LDOSEQCNT5 0x29
#define MAX8907_REG_LDO5VOUT 0x2A
#define MAX8907_REG_LDOCTL6 0x2C
#define MAX8907_REG_LDOSEQCNT6 0x2D
#define MAX8907_REG_LDO6VOUT 0x2E
#define MAX8907_REG_LDOCTL7 0x30
#define MAX8907_REG_LDOSEQCNT7 0x31
#define MAX8907_REG_LDO7VOUT 0x32
#define MAX8907_REG_LDOCTL8 0x34
#define MAX8907_REG_LDOSEQCNT8 0x35
#define MAX8907_REG_LDO8VOUT 0x36
#define MAX8907_REG_LDOCTL9 0x38
#define MAX8907_REG_LDOSEQCNT9 0x39
#define MAX8907_REG_LDO9VOUT 0x3A
#define MAX8907_REG_LDOCTL10 0x3C
#define MAX8907_REG_LDOSEQCNT10 0x3D
#define MAX8907_REG_LDO10VOUT 0x3E
#define MAX8907_REG_LDOCTL11 0x40
#define MAX8907_REG_LDOSEQCNT11 0x41
#define MAX8907_REG_LDO11VOUT 0x42
#define MAX8907_REG_LDOCTL12 0x44
#define MAX8907_REG_LDOSEQCNT12 0x45
#define MAX8907_REG_LDO12VOUT 0x46
#define MAX8907_REG_LDOCTL13 0x48
#define MAX8907_REG_LDOSEQCNT13 0x49
#define MAX8907_REG_LDO13VOUT 0x4A
#define MAX8907_REG_LDOCTL14 0x4C
#define MAX8907_REG_LDOSEQCNT14 0x4D
#define MAX8907_REG_LDO14VOUT 0x4E
#define MAX8907_REG_LDOCTL15 0x50
#define MAX8907_REG_LDOSEQCNT15 0x51
#define MAX8907_REG_LDO15VOUT 0x52
#define MAX8907_REG_OUT5VEN 0x54
#define MAX8907_REG_OUT5VSEQ 0x55
#define MAX8907_REG_OUT33VEN 0x58
#define MAX8907_REG_OUT33VSEQ 0x59
#define MAX8907_REG_LDOCTL19 0x5C
#define MAX8907_REG_LDOSEQCNT19 0x5D
#define MAX8907_REG_LDO19VOUT 0x5E
#define MAX8907_REG_LBCNFG 0x60
#define MAX8907_REG_SEQ1CNFG 0x64
#define MAX8907_REG_SEQ2CNFG 0x65
#define MAX8907_REG_SEQ3CNFG 0x66
#define MAX8907_REG_SEQ4CNFG 0x67
#define MAX8907_REG_SEQ5CNFG 0x68
#define MAX8907_REG_SEQ6CNFG 0x69
#define MAX8907_REG_SEQ7CNFG 0x6A
#define MAX8907_REG_LDOCTL18 0x72
#define MAX8907_REG_LDOSEQCNT18 0x73
#define MAX8907_REG_LDO18VOUT 0x74
#define MAX8907_REG_BBAT_CNFG 0x78
#define MAX8907_REG_CHG_CNTL1 0x7C
#define MAX8907_REG_CHG_CNTL2 0x7D
#define MAX8907_REG_CHG_IRQ1 0x7E
#define MAX8907_REG_CHG_IRQ2 0x7F
#define MAX8907_REG_CHG_IRQ1_MASK 0x80
#define MAX8907_REG_CHG_IRQ2_MASK 0x81
#define MAX8907_REG_CHG_STAT 0x82
#define MAX8907_REG_WLED_MODE_CNTL 0x84
#define MAX8907_REG_ILED_CNTL 0x84
#define MAX8907_REG_II1RR 0x8E
#define MAX8907_REG_II2RR 0x8F
#define MAX8907_REG_LDOCTL20 0x9C
#define MAX8907_REG_LDOSEQCNT20 0x9D
#define MAX8907_REG_LDO20VOUT 0x9E
/* RTC register map */
#define MAX8907_REG_RTC_SEC 0x00
#define MAX8907_REG_RTC_MIN 0x01
#define MAX8907_REG_RTC_HOURS 0x02
#define MAX8907_REG_RTC_WEEKDAY 0x03
#define MAX8907_REG_RTC_DATE 0x04
#define MAX8907_REG_RTC_MONTH 0x05
#define MAX8907_REG_RTC_YEAR1 0x06
#define MAX8907_REG_RTC_YEAR2 0x07
#define MAX8907_REG_ALARM0_SEC 0x08
#define MAX8907_REG_ALARM0_MIN 0x09
#define MAX8907_REG_ALARM0_HOURS 0x0A
#define MAX8907_REG_ALARM0_WEEKDAY 0x0B
#define MAX8907_REG_ALARM0_DATE 0x0C
#define MAX8907_REG_ALARM0_MONTH 0x0D
#define MAX8907_REG_ALARM0_YEAR1 0x0E
#define MAX8907_REG_ALARM0_YEAR2 0x0F
#define MAX8907_REG_ALARM1_SEC 0x10
#define MAX8907_REG_ALARM1_MIN 0x11
#define MAX8907_REG_ALARM1_HOURS 0x12
#define MAX8907_REG_ALARM1_WEEKDAY 0x13
#define MAX8907_REG_ALARM1_DATE 0x14
#define MAX8907_REG_ALARM1_MONTH 0x15
#define MAX8907_REG_ALARM1_YEAR1 0x16
#define MAX8907_REG_ALARM1_YEAR2 0x17
#define MAX8907_REG_ALARM0_CNTL 0x18
#define MAX8907_REG_ALARM1_CNTL 0x19
#define MAX8907_REG_RTC_STATUS 0x1A
#define MAX8907_REG_RTC_CNTL 0x1B
#define MAX8907_REG_RTC_IRQ 0x1C
#define MAX8907_REG_RTC_IRQ_MASK 0x1D
#define MAX8907_REG_MPL_CNTL 0x1E
/* ADC and Touch Screen Controller register map */
#define MAX8907_CTL 0
#define MAX8907_SEQCNT 1
#define MAX8907_VOUT 2
/* mask bit fields */
#define MAX8907_MASK_LDO_SEQ 0x1C
#define MAX8907_MASK_LDO_EN 0x01
#define MAX8907_MASK_VBBATTCV 0x03
#define MAX8907_MASK_OUT5V_VINEN 0x10
#define MAX8907_MASK_OUT5V_ENSRC 0x0E
#define MAX8907_MASK_OUT5V_EN 0x01
#define MAX8907_MASK_POWER_OFF 0x40
/* Regulator IDs */
#define MAX8907_MBATT 0
#define MAX8907_SD1 1
#define MAX8907_SD2 2
#define MAX8907_SD3 3
#define MAX8907_LDO1 4
#define MAX8907_LDO2 5
#define MAX8907_LDO3 6
#define MAX8907_LDO4 7
#define MAX8907_LDO5 8
#define MAX8907_LDO6 9
#define MAX8907_LDO7 10
#define MAX8907_LDO8 11
#define MAX8907_LDO9 12
#define MAX8907_LDO10 13
#define MAX8907_LDO11 14
#define MAX8907_LDO12 15
#define MAX8907_LDO13 16
#define MAX8907_LDO14 17
#define MAX8907_LDO15 18
#define MAX8907_LDO16 19
#define MAX8907_LDO17 20
#define MAX8907_LDO18 21
#define MAX8907_LDO19 22
#define MAX8907_LDO20 23
#define MAX8907_OUT5V 24
#define MAX8907_OUT33V 25
#define MAX8907_BBAT 26
#define MAX8907_SDBY 27
#define MAX8907_VRTC 28
#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
/* IRQ definitions */
enum {
MAX8907_IRQ_VCHG_DC_OVP = 0,
MAX8907_IRQ_VCHG_DC_F,
MAX8907_IRQ_VCHG_DC_R,
MAX8907_IRQ_VCHG_THM_OK_R,
MAX8907_IRQ_VCHG_THM_OK_F,
MAX8907_IRQ_VCHG_MBATTLOW_F,
MAX8907_IRQ_VCHG_MBATTLOW_R,
MAX8907_IRQ_VCHG_RST,
MAX8907_IRQ_VCHG_DONE,
MAX8907_IRQ_VCHG_TOPOFF,
MAX8907_IRQ_VCHG_TMR_FAULT,
MAX8907_IRQ_GPM_RSTIN = 0,
MAX8907_IRQ_GPM_MPL,
MAX8907_IRQ_GPM_SW_3SEC,
MAX8907_IRQ_GPM_EXTON_F,
MAX8907_IRQ_GPM_EXTON_R,
MAX8907_IRQ_GPM_SW_1SEC,
MAX8907_IRQ_GPM_SW_F,
MAX8907_IRQ_GPM_SW_R,
MAX8907_IRQ_GPM_SYSCKEN_F,
MAX8907_IRQ_GPM_SYSCKEN_R,
MAX8907_IRQ_RTC_ALARM1 = 0,
MAX8907_IRQ_RTC_ALARM0,
};
struct max8907_platform_data {
struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
bool pm_off;
};
struct regmap_irq_chips_data;
struct max8907 {
struct device *dev;
struct mutex irq_lock;
struct i2c_client *i2c_gen;
struct i2c_client *i2c_rtc;
struct regmap *regmap_gen;
struct regmap *regmap_rtc;
struct regmap_irq_chip_data *irqc_chg;
struct regmap_irq_chip_data *irqc_on_off;
struct regmap_irq_chip_data *irqc_rtc;
};
#endif

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include/linux/mfd/max8925.h Normal file
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/*
* Maxim8925 Interface
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_MAX8925_H
#define __LINUX_MFD_MAX8925_H
#include <linux/mutex.h>
#include <linux/interrupt.h>
/* Unified sub device IDs for MAX8925 */
enum {
MAX8925_ID_SD1,
MAX8925_ID_SD2,
MAX8925_ID_SD3,
MAX8925_ID_LDO1,
MAX8925_ID_LDO2,
MAX8925_ID_LDO3,
MAX8925_ID_LDO4,
MAX8925_ID_LDO5,
MAX8925_ID_LDO6,
MAX8925_ID_LDO7,
MAX8925_ID_LDO8,
MAX8925_ID_LDO9,
MAX8925_ID_LDO10,
MAX8925_ID_LDO11,
MAX8925_ID_LDO12,
MAX8925_ID_LDO13,
MAX8925_ID_LDO14,
MAX8925_ID_LDO15,
MAX8925_ID_LDO16,
MAX8925_ID_LDO17,
MAX8925_ID_LDO18,
MAX8925_ID_LDO19,
MAX8925_ID_LDO20,
MAX8925_ID_MAX,
};
enum {
/*
* Charging current threshold trigger going from fast charge
* to TOPOFF charge. From 5% to 20% of fasting charging current.
*/
MAX8925_TOPOFF_THR_5PER,
MAX8925_TOPOFF_THR_10PER,
MAX8925_TOPOFF_THR_15PER,
MAX8925_TOPOFF_THR_20PER,
};
enum {
/* Fast charging current */
MAX8925_FCHG_85MA,
MAX8925_FCHG_300MA,
MAX8925_FCHG_460MA,
MAX8925_FCHG_600MA,
MAX8925_FCHG_700MA,
MAX8925_FCHG_800MA,
MAX8925_FCHG_900MA,
MAX8925_FCHG_1000MA,
};
/* Charger registers */
#define MAX8925_CHG_IRQ1 (0x7e)
#define MAX8925_CHG_IRQ2 (0x7f)
#define MAX8925_CHG_IRQ1_MASK (0x80)
#define MAX8925_CHG_IRQ2_MASK (0x81)
#define MAX8925_CHG_STATUS (0x82)
/* GPM registers */
#define MAX8925_SYSENSEL (0x00)
#define MAX8925_ON_OFF_IRQ1 (0x01)
#define MAX8925_ON_OFF_IRQ1_MASK (0x02)
#define MAX8925_ON_OFF_STATUS (0x03)
#define MAX8925_ON_OFF_IRQ2 (0x0d)
#define MAX8925_ON_OFF_IRQ2_MASK (0x0e)
#define MAX8925_RESET_CNFG (0x0f)
/* Touch registers */
#define MAX8925_TSC_IRQ (0x00)
#define MAX8925_TSC_IRQ_MASK (0x01)
#define MAX8925_TSC_CNFG1 (0x02)
#define MAX8925_ADC_SCHED (0x10)
#define MAX8925_ADC_RES_END (0x6f)
#define MAX8925_NREF_OK (1 << 4)
/* RTC registers */
#define MAX8925_ALARM0_CNTL (0x18)
#define MAX8925_ALARM1_CNTL (0x19)
#define MAX8925_RTC_IRQ (0x1c)
#define MAX8925_RTC_IRQ_MASK (0x1d)
#define MAX8925_MPL_CNTL (0x1e)
/* WLED registers */
#define MAX8925_WLED_MODE_CNTL (0x84)
#define MAX8925_WLED_CNTL (0x85)
/* MAX8925 Registers */
#define MAX8925_SDCTL1 (0x04)
#define MAX8925_SDCTL2 (0x07)
#define MAX8925_SDCTL3 (0x0A)
#define MAX8925_SDV1 (0x06)
#define MAX8925_SDV2 (0x09)
#define MAX8925_SDV3 (0x0C)
#define MAX8925_LDOCTL1 (0x18)
#define MAX8925_LDOCTL2 (0x1C)
#define MAX8925_LDOCTL3 (0x20)
#define MAX8925_LDOCTL4 (0x24)
#define MAX8925_LDOCTL5 (0x28)
#define MAX8925_LDOCTL6 (0x2C)
#define MAX8925_LDOCTL7 (0x30)
#define MAX8925_LDOCTL8 (0x34)
#define MAX8925_LDOCTL9 (0x38)
#define MAX8925_LDOCTL10 (0x3C)
#define MAX8925_LDOCTL11 (0x40)
#define MAX8925_LDOCTL12 (0x44)
#define MAX8925_LDOCTL13 (0x48)
#define MAX8925_LDOCTL14 (0x4C)
#define MAX8925_LDOCTL15 (0x50)
#define MAX8925_LDOCTL16 (0x10)
#define MAX8925_LDOCTL17 (0x14)
#define MAX8925_LDOCTL18 (0x72)
#define MAX8925_LDOCTL19 (0x5C)
#define MAX8925_LDOCTL20 (0x9C)
#define MAX8925_LDOVOUT1 (0x1A)
#define MAX8925_LDOVOUT2 (0x1E)
#define MAX8925_LDOVOUT3 (0x22)
#define MAX8925_LDOVOUT4 (0x26)
#define MAX8925_LDOVOUT5 (0x2A)
#define MAX8925_LDOVOUT6 (0x2E)
#define MAX8925_LDOVOUT7 (0x32)
#define MAX8925_LDOVOUT8 (0x36)
#define MAX8925_LDOVOUT9 (0x3A)
#define MAX8925_LDOVOUT10 (0x3E)
#define MAX8925_LDOVOUT11 (0x42)
#define MAX8925_LDOVOUT12 (0x46)
#define MAX8925_LDOVOUT13 (0x4A)
#define MAX8925_LDOVOUT14 (0x4E)
#define MAX8925_LDOVOUT15 (0x52)
#define MAX8925_LDOVOUT16 (0x12)
#define MAX8925_LDOVOUT17 (0x16)
#define MAX8925_LDOVOUT18 (0x74)
#define MAX8925_LDOVOUT19 (0x5E)
#define MAX8925_LDOVOUT20 (0x9E)
/* bit definitions */
#define CHG_IRQ1_MASK (0x07)
#define CHG_IRQ2_MASK (0xff)
#define ON_OFF_IRQ1_MASK (0xff)
#define ON_OFF_IRQ2_MASK (0x03)
#define TSC_IRQ_MASK (0x03)
#define RTC_IRQ_MASK (0x0c)
#define MAX8925_NAME_SIZE (32)
/* IRQ definitions */
enum {
MAX8925_IRQ_VCHG_DC_OVP,
MAX8925_IRQ_VCHG_DC_F,
MAX8925_IRQ_VCHG_DC_R,
MAX8925_IRQ_VCHG_THM_OK_R,
MAX8925_IRQ_VCHG_THM_OK_F,
MAX8925_IRQ_VCHG_SYSLOW_F,
MAX8925_IRQ_VCHG_SYSLOW_R,
MAX8925_IRQ_VCHG_RST,
MAX8925_IRQ_VCHG_DONE,
MAX8925_IRQ_VCHG_TOPOFF,
MAX8925_IRQ_VCHG_TMR_FAULT,
MAX8925_IRQ_GPM_RSTIN,
MAX8925_IRQ_GPM_MPL,
MAX8925_IRQ_GPM_SW_3SEC,
MAX8925_IRQ_GPM_EXTON_F,
MAX8925_IRQ_GPM_EXTON_R,
MAX8925_IRQ_GPM_SW_1SEC,
MAX8925_IRQ_GPM_SW_F,
MAX8925_IRQ_GPM_SW_R,
MAX8925_IRQ_GPM_SYSCKEN_F,
MAX8925_IRQ_GPM_SYSCKEN_R,
MAX8925_IRQ_RTC_ALARM1,
MAX8925_IRQ_RTC_ALARM0,
MAX8925_IRQ_TSC_STICK,
MAX8925_IRQ_TSC_NSTICK,
MAX8925_NR_IRQS,
};
struct max8925_chip {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *adc;
struct i2c_client *rtc;
struct mutex io_lock;
struct mutex irq_lock;
int irq_base;
int core_irq;
int tsc_irq;
unsigned int wakeup_flag;
};
struct max8925_backlight_pdata {
int lxw_scl; /* 0/1 -- 0.8Ohm/0.4Ohm */
int lxw_freq; /* 700KHz ~ 1400KHz */
int dual_string; /* 0/1 -- single/dual string */
};
struct max8925_touch_pdata {
unsigned int flags;
};
struct max8925_power_pdata {
int (*set_charger)(int);
unsigned batt_detect:1;
unsigned topoff_threshold:2;
unsigned fast_charge:3; /* charge current */
unsigned no_temp_support:1; /* set if no temperature detect */
unsigned no_insert_detect:1; /* set if no ac insert detect */
char **supplied_to;
int num_supplicants;
};
/*
* irq_base: stores IRQ base number of MAX8925 in platform
* tsc_irq: stores IRQ number of MAX8925 TSC
*/
struct max8925_platform_data {
struct max8925_backlight_pdata *backlight;
struct max8925_touch_pdata *touch;
struct max8925_power_pdata *power;
struct regulator_init_data *sd1;
struct regulator_init_data *sd2;
struct regulator_init_data *sd3;
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldo8;
struct regulator_init_data *ldo9;
struct regulator_init_data *ldo10;
struct regulator_init_data *ldo11;
struct regulator_init_data *ldo12;
struct regulator_init_data *ldo13;
struct regulator_init_data *ldo14;
struct regulator_init_data *ldo15;
struct regulator_init_data *ldo16;
struct regulator_init_data *ldo17;
struct regulator_init_data *ldo18;
struct regulator_init_data *ldo19;
struct regulator_init_data *ldo20;
int irq_base;
int tsc_irq;
};
extern int max8925_reg_read(struct i2c_client *, int);
extern int max8925_reg_write(struct i2c_client *, int, unsigned char);
extern int max8925_bulk_read(struct i2c_client *, int, int, unsigned char *);
extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *);
extern int max8925_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int max8925_device_init(struct max8925_chip *,
struct max8925_platform_data *);
extern void max8925_device_exit(struct max8925_chip *);
#endif /* __LINUX_MFD_MAX8925_H */

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include/linux/mfd/max8997-private.h Normal file
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/*
* max8997.h - Voltage regulator driver for the Maxim 8997
*
* Copyright (C) 2010 Samsung Electrnoics
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8997_PRIV_H
#define __LINUX_MFD_MAX8997_PRIV_H
#include <linux/i2c.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#define MAX8997_REG_INVALID (0xff)
enum max8997_pmic_reg {
MAX8997_REG_PMIC_ID0 = 0x00,
MAX8997_REG_PMIC_ID1 = 0x01,
MAX8997_REG_INTSRC = 0x02,
MAX8997_REG_INT1 = 0x03,
MAX8997_REG_INT2 = 0x04,
MAX8997_REG_INT3 = 0x05,
MAX8997_REG_INT4 = 0x06,
MAX8997_REG_INT1MSK = 0x08,
MAX8997_REG_INT2MSK = 0x09,
MAX8997_REG_INT3MSK = 0x0a,
MAX8997_REG_INT4MSK = 0x0b,
MAX8997_REG_STATUS1 = 0x0d,
MAX8997_REG_STATUS2 = 0x0e,
MAX8997_REG_STATUS3 = 0x0f,
MAX8997_REG_STATUS4 = 0x10,
MAX8997_REG_MAINCON1 = 0x13,
MAX8997_REG_MAINCON2 = 0x14,
MAX8997_REG_BUCKRAMP = 0x15,
MAX8997_REG_BUCK1CTRL = 0x18,
MAX8997_REG_BUCK1DVS1 = 0x19,
MAX8997_REG_BUCK1DVS2 = 0x1a,
MAX8997_REG_BUCK1DVS3 = 0x1b,
MAX8997_REG_BUCK1DVS4 = 0x1c,
MAX8997_REG_BUCK1DVS5 = 0x1d,
MAX8997_REG_BUCK1DVS6 = 0x1e,
MAX8997_REG_BUCK1DVS7 = 0x1f,
MAX8997_REG_BUCK1DVS8 = 0x20,
MAX8997_REG_BUCK2CTRL = 0x21,
MAX8997_REG_BUCK2DVS1 = 0x22,
MAX8997_REG_BUCK2DVS2 = 0x23,
MAX8997_REG_BUCK2DVS3 = 0x24,
MAX8997_REG_BUCK2DVS4 = 0x25,
MAX8997_REG_BUCK2DVS5 = 0x26,
MAX8997_REG_BUCK2DVS6 = 0x27,
MAX8997_REG_BUCK2DVS7 = 0x28,
MAX8997_REG_BUCK2DVS8 = 0x29,
MAX8997_REG_BUCK3CTRL = 0x2a,
MAX8997_REG_BUCK3DVS = 0x2b,
MAX8997_REG_BUCK4CTRL = 0x2c,
MAX8997_REG_BUCK4DVS = 0x2d,
MAX8997_REG_BUCK5CTRL = 0x2e,
MAX8997_REG_BUCK5DVS1 = 0x2f,
MAX8997_REG_BUCK5DVS2 = 0x30,
MAX8997_REG_BUCK5DVS3 = 0x31,
MAX8997_REG_BUCK5DVS4 = 0x32,
MAX8997_REG_BUCK5DVS5 = 0x33,
MAX8997_REG_BUCK5DVS6 = 0x34,
MAX8997_REG_BUCK5DVS7 = 0x35,
MAX8997_REG_BUCK5DVS8 = 0x36,
MAX8997_REG_BUCK6CTRL = 0x37,
MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
MAX8997_REG_BUCK7CTRL = 0x39,
MAX8997_REG_BUCK7DVS = 0x3a,
MAX8997_REG_LDO1CTRL = 0x3b,
MAX8997_REG_LDO2CTRL = 0x3c,
MAX8997_REG_LDO3CTRL = 0x3d,
MAX8997_REG_LDO4CTRL = 0x3e,
MAX8997_REG_LDO5CTRL = 0x3f,
MAX8997_REG_LDO6CTRL = 0x40,
MAX8997_REG_LDO7CTRL = 0x41,
MAX8997_REG_LDO8CTRL = 0x42,
MAX8997_REG_LDO9CTRL = 0x43,
MAX8997_REG_LDO10CTRL = 0x44,
MAX8997_REG_LDO11CTRL = 0x45,
MAX8997_REG_LDO12CTRL = 0x46,
MAX8997_REG_LDO13CTRL = 0x47,
MAX8997_REG_LDO14CTRL = 0x48,
MAX8997_REG_LDO15CTRL = 0x49,
MAX8997_REG_LDO16CTRL = 0x4a,
MAX8997_REG_LDO17CTRL = 0x4b,
MAX8997_REG_LDO18CTRL = 0x4c,
MAX8997_REG_LDO21CTRL = 0x4d,
MAX8997_REG_MBCCTRL1 = 0x50,
MAX8997_REG_MBCCTRL2 = 0x51,
MAX8997_REG_MBCCTRL3 = 0x52,
MAX8997_REG_MBCCTRL4 = 0x53,
MAX8997_REG_MBCCTRL5 = 0x54,
MAX8997_REG_MBCCTRL6 = 0x55,
MAX8997_REG_OTPCGHCVS = 0x56,
MAX8997_REG_SAFEOUTCTRL = 0x5a,
MAX8997_REG_LBCNFG1 = 0x5e,
MAX8997_REG_LBCNFG2 = 0x5f,
MAX8997_REG_BBCCTRL = 0x60,
MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
MAX8997_REG_FLASH2_CUR = 0x64,
MAX8997_REG_MOVIE_CUR = 0x65,
MAX8997_REG_GSMB_CUR = 0x66,
MAX8997_REG_BOOST_CNTL = 0x67,
MAX8997_REG_LEN_CNTL = 0x68,
MAX8997_REG_FLASH_CNTL = 0x69,
MAX8997_REG_WDT_CNTL = 0x6a,
MAX8997_REG_MAXFLASH1 = 0x6b,
MAX8997_REG_MAXFLASH2 = 0x6c,
MAX8997_REG_FLASHSTATUS = 0x6d,
MAX8997_REG_FLASHSTATUSMASK = 0x6e,
MAX8997_REG_GPIOCNTL1 = 0x70,
MAX8997_REG_GPIOCNTL2 = 0x71,
MAX8997_REG_GPIOCNTL3 = 0x72,
MAX8997_REG_GPIOCNTL4 = 0x73,
MAX8997_REG_GPIOCNTL5 = 0x74,
MAX8997_REG_GPIOCNTL6 = 0x75,
MAX8997_REG_GPIOCNTL7 = 0x76,
MAX8997_REG_GPIOCNTL8 = 0x77,
MAX8997_REG_GPIOCNTL9 = 0x78,
MAX8997_REG_GPIOCNTL10 = 0x79,
MAX8997_REG_GPIOCNTL11 = 0x7a,
MAX8997_REG_GPIOCNTL12 = 0x7b,
MAX8997_REG_LDO1CONFIG = 0x80,
MAX8997_REG_LDO2CONFIG = 0x81,
MAX8997_REG_LDO3CONFIG = 0x82,
MAX8997_REG_LDO4CONFIG = 0x83,
MAX8997_REG_LDO5CONFIG = 0x84,
MAX8997_REG_LDO6CONFIG = 0x85,
MAX8997_REG_LDO7CONFIG = 0x86,
MAX8997_REG_LDO8CONFIG = 0x87,
MAX8997_REG_LDO9CONFIG = 0x88,
MAX8997_REG_LDO10CONFIG = 0x89,
MAX8997_REG_LDO11CONFIG = 0x8a,
MAX8997_REG_LDO12CONFIG = 0x8b,
MAX8997_REG_LDO13CONFIG = 0x8c,
MAX8997_REG_LDO14CONFIG = 0x8d,
MAX8997_REG_LDO15CONFIG = 0x8e,
MAX8997_REG_LDO16CONFIG = 0x8f,
MAX8997_REG_LDO17CONFIG = 0x90,
MAX8997_REG_LDO18CONFIG = 0x91,
MAX8997_REG_LDO21CONFIG = 0x92,
MAX8997_REG_DVSOKTIMER1 = 0x97,
MAX8997_REG_DVSOKTIMER2 = 0x98,
MAX8997_REG_DVSOKTIMER4 = 0x99,
MAX8997_REG_DVSOKTIMER5 = 0x9a,
MAX8997_REG_PMIC_END = 0x9b,
};
enum max8997_muic_reg {
MAX8997_MUIC_REG_ID = 0x0,
MAX8997_MUIC_REG_INT1 = 0x1,
MAX8997_MUIC_REG_INT2 = 0x2,
MAX8997_MUIC_REG_INT3 = 0x3,
MAX8997_MUIC_REG_STATUS1 = 0x4,
MAX8997_MUIC_REG_STATUS2 = 0x5,
MAX8997_MUIC_REG_STATUS3 = 0x6,
MAX8997_MUIC_REG_INTMASK1 = 0x7,
MAX8997_MUIC_REG_INTMASK2 = 0x8,
MAX8997_MUIC_REG_INTMASK3 = 0x9,
MAX8997_MUIC_REG_CDETCTRL = 0xa,
MAX8997_MUIC_REG_CONTROL1 = 0xc,
MAX8997_MUIC_REG_CONTROL2 = 0xd,
MAX8997_MUIC_REG_CONTROL3 = 0xe,
MAX8997_MUIC_REG_END = 0xf,
};
/* MAX8997-MUIC STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCLOW_SHIFT 5
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
/* MAX8997-MUIC STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DBCHG_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX8997-MUIC STATUS3 register */
#define STATUS3_OVP_SHIFT 2
#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
/* MAX8997-MUIC CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
| (1 << COMN1SW_SHIFT))
#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
| (2 << COMN1SW_SHIFT))
#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
| (3 << COMN1SW_SHIFT))
#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
| (0 << COMN1SW_SHIFT))
#define CONTROL2_LOWPWR_SHIFT (0)
#define CONTROL2_ADCEN_SHIFT (1)
#define CONTROL2_CPEN_SHIFT (2)
#define CONTROL2_SFOUTASRT_SHIFT (3)
#define CONTROL2_SFOUTORD_SHIFT (4)
#define CONTROL2_ACCDET_SHIFT (5)
#define CONTROL2_USBCPINT_SHIFT (6)
#define CONTROL2_RCPS_SHIFT (7)
#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
#define CONTROL3_JIGSET_SHIFT (0)
#define CONTROL3_BTLDSET_SHIFT (2)
#define CONTROL3_ADCDBSET_SHIFT (4)
#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
enum max8997_haptic_reg {
MAX8997_HAPTIC_REG_GENERAL = 0x00,
MAX8997_HAPTIC_REG_CONF1 = 0x01,
MAX8997_HAPTIC_REG_CONF2 = 0x02,
MAX8997_HAPTIC_REG_DRVCONF = 0x03,
MAX8997_HAPTIC_REG_CYCLECONF1 = 0x04,
MAX8997_HAPTIC_REG_CYCLECONF2 = 0x05,
MAX8997_HAPTIC_REG_SIGCONF1 = 0x06,
MAX8997_HAPTIC_REG_SIGCONF2 = 0x07,
MAX8997_HAPTIC_REG_SIGCONF3 = 0x08,
MAX8997_HAPTIC_REG_SIGCONF4 = 0x09,
MAX8997_HAPTIC_REG_SIGDC1 = 0x0a,
MAX8997_HAPTIC_REG_SIGDC2 = 0x0b,
MAX8997_HAPTIC_REG_SIGPWMDC1 = 0x0c,
MAX8997_HAPTIC_REG_SIGPWMDC2 = 0x0d,
MAX8997_HAPTIC_REG_SIGPWMDC3 = 0x0e,
MAX8997_HAPTIC_REG_SIGPWMDC4 = 0x0f,
MAX8997_HAPTIC_REG_MTR_REV = 0x10,
MAX8997_HAPTIC_REG_END = 0x11,
};
/* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
enum max8997_rtc_reg {
MAX8997_RTC_CTRLMASK = 0x02,
MAX8997_RTC_CTRL = 0x03,
MAX8997_RTC_UPDATE1 = 0x04,
MAX8997_RTC_UPDATE2 = 0x05,
MAX8997_RTC_WTSR_SMPL = 0x06,
MAX8997_RTC_SEC = 0x10,
MAX8997_RTC_MIN = 0x11,
MAX8997_RTC_HOUR = 0x12,
MAX8997_RTC_DAY_OF_WEEK = 0x13,
MAX8997_RTC_MONTH = 0x14,
MAX8997_RTC_YEAR = 0x15,
MAX8997_RTC_DAY_OF_MONTH = 0x16,
MAX8997_RTC_ALARM1_SEC = 0x17,
MAX8997_RTC_ALARM1_MIN = 0x18,
MAX8997_RTC_ALARM1_HOUR = 0x19,
MAX8997_RTC_ALARM1_DAY_OF_WEEK = 0x1a,
MAX8997_RTC_ALARM1_MONTH = 0x1b,
MAX8997_RTC_ALARM1_YEAR = 0x1c,
MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
MAX8997_RTC_ALARM2_SEC = 0x1e,
MAX8997_RTC_ALARM2_MIN = 0x1f,
MAX8997_RTC_ALARM2_HOUR = 0x20,
MAX8997_RTC_ALARM2_DAY_OF_WEEK = 0x21,
MAX8997_RTC_ALARM2_MONTH = 0x22,
MAX8997_RTC_ALARM2_YEAR = 0x23,
MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
};
enum max8997_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
PMIC_INT3,
PMIC_INT4,
FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
MUIC_INT1,
MUIC_INT2,
MUIC_INT3,
GPIO_LOW, /* Not implemented */
GPIO_HI, /* Not implemented */
FLASH_STATUS, /* Not implemented */
MAX8997_IRQ_GROUP_NR,
};
enum max8997_irq {
MAX8997_PMICIRQ_PWRONR,
MAX8997_PMICIRQ_PWRONF,
MAX8997_PMICIRQ_PWRON1SEC,
MAX8997_PMICIRQ_JIGONR,
MAX8997_PMICIRQ_JIGONF,
MAX8997_PMICIRQ_LOWBAT2,
MAX8997_PMICIRQ_LOWBAT1,
MAX8997_PMICIRQ_JIGR,
MAX8997_PMICIRQ_JIGF,
MAX8997_PMICIRQ_MR,
MAX8997_PMICIRQ_DVS1OK,
MAX8997_PMICIRQ_DVS2OK,
MAX8997_PMICIRQ_DVS3OK,
MAX8997_PMICIRQ_DVS4OK,
MAX8997_PMICIRQ_CHGINS,
MAX8997_PMICIRQ_CHGRM,
MAX8997_PMICIRQ_DCINOVP,
MAX8997_PMICIRQ_TOPOFFR,
MAX8997_PMICIRQ_CHGRSTF,
MAX8997_PMICIRQ_MBCHGTMEXPD,
MAX8997_PMICIRQ_RTC60S,
MAX8997_PMICIRQ_RTCA1,
MAX8997_PMICIRQ_RTCA2,
MAX8997_PMICIRQ_SMPL_INT,
MAX8997_PMICIRQ_RTC1S,
MAX8997_PMICIRQ_WTSR,
MAX8997_MUICIRQ_ADCError,
MAX8997_MUICIRQ_ADCLow,
MAX8997_MUICIRQ_ADC,
MAX8997_MUICIRQ_VBVolt,
MAX8997_MUICIRQ_DBChg,
MAX8997_MUICIRQ_DCDTmr,
MAX8997_MUICIRQ_ChgDetRun,
MAX8997_MUICIRQ_ChgTyp,
MAX8997_MUICIRQ_OVP,
MAX8997_IRQ_NR,
};
#define MAX8997_NUM_GPIO 12
struct max8997_dev {
struct device *dev;
struct max8997_platform_data *pdata;
struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
struct i2c_client *rtc; /* slave addr 0x0c */
struct i2c_client *haptic; /* slave addr 0x90 */
struct i2c_client *muic; /* slave addr 0x4a */
struct mutex iolock;
int type;
struct platform_device *battery; /* battery control (not fuel gauge) */
int irq;
int ono;
struct irq_domain *irq_domain;
struct mutex irqlock;
int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
/* For hibernation */
u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
MAX8997_HAPTIC_REG_END];
bool gpio_status[MAX8997_NUM_GPIO];
};
enum max8997_types {
TYPE_MAX8997,
TYPE_MAX8966,
};
extern int max8997_irq_init(struct max8997_dev *max8997);
extern void max8997_irq_exit(struct max8997_dev *max8997);
extern int max8997_irq_resume(struct max8997_dev *max8997);
extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
#define MAX8997_GPIO_INT_BOTH (0x3 << 4)
#define MAX8997_GPIO_INT_RISE (0x2 << 4)
#define MAX8997_GPIO_INT_FALL (0x1 << 4)
#define MAX8997_GPIO_INT_MASK (0x3 << 4)
#define MAX8997_GPIO_DATA_MASK (0x1 << 2)
#endif /* __LINUX_MFD_MAX8997_PRIV_H */

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/*
* max8997.h - Driver for the Maxim 8997/8966
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8998.h
*
* MAX8997 has PMIC, MUIC, HAPTIC, RTC, FLASH, and Fuel Gauge devices.
* Except Fuel Gauge, every device shares the same I2C bus and included in
* this mfd driver. Although the fuel gauge is included in the chip, it is
* excluded from the driver because a) it has a different I2C bus from
* others and b) it can be enabled simply by using MAX17042 driver.
*/
#ifndef __LINUX_MFD_MAX8998_H
#define __LINUX_MFD_MAX8998_H
#include <linux/regulator/consumer.h>
/* MAX8997/8966 regulator IDs */
enum max8998_regulators {
MAX8997_LDO1 = 0,
MAX8997_LDO2,
MAX8997_LDO3,
MAX8997_LDO4,
MAX8997_LDO5,
MAX8997_LDO6,
MAX8997_LDO7,
MAX8997_LDO8,
MAX8997_LDO9,
MAX8997_LDO10,
MAX8997_LDO11,
MAX8997_LDO12,
MAX8997_LDO13,
MAX8997_LDO14,
MAX8997_LDO15,
MAX8997_LDO16,
MAX8997_LDO17,
MAX8997_LDO18,
MAX8997_LDO21,
MAX8997_BUCK1,
MAX8997_BUCK2,
MAX8997_BUCK3,
MAX8997_BUCK4,
MAX8997_BUCK5,
MAX8997_BUCK6,
MAX8997_BUCK7,
MAX8997_EN32KHZ_AP,
MAX8997_EN32KHZ_CP,
MAX8997_ENVICHG,
MAX8997_ESAFEOUT1,
MAX8997_ESAFEOUT2,
MAX8997_CHARGER_CV, /* control MBCCV of MBCCTRL3 */
MAX8997_CHARGER, /* charger current, MBCCTRL4 */
MAX8997_CHARGER_TOPOFF, /* MBCCTRL5 */
MAX8997_REG_MAX,
};
struct max8997_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
struct max8997_muic_reg_data {
u8 addr;
u8 data;
};
/**
* struct max8997_muic_platform_data
* @init_data: array of max8997_muic_reg_data
* used for initializing registers of MAX8997 MUIC device
* @num_init_data: array size of init_data
*/
struct max8997_muic_platform_data {
struct max8997_muic_reg_data *init_data;
int num_init_data;
/* Check cable state after certain delay */
int detcable_delay_ms;
/*
* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
* h/w path of COMP2/COMN1 on CONTROL1 register.
*/
int path_usb;
int path_uart;
};
enum max8997_haptic_motor_type {
MAX8997_HAPTIC_ERM,
MAX8997_HAPTIC_LRA,
};
enum max8997_haptic_pulse_mode {
MAX8997_EXTERNAL_MODE,
MAX8997_INTERNAL_MODE,
};
enum max8997_haptic_pwm_divisor {
MAX8997_PWM_DIVISOR_32,
MAX8997_PWM_DIVISOR_64,
MAX8997_PWM_DIVISOR_128,
MAX8997_PWM_DIVISOR_256,
};
/**
* max8997_haptic_platform_data
* @pwm_channel_id: channel number of PWM device
* valid for MAX8997_EXTERNAL_MODE
* @pwm_period: period in nano second for PWM device
* valid for MAX8997_EXTERNAL_MODE
* @type: motor type
* @mode: pulse mode
* MAX8997_EXTERNAL_MODE: external PWM device is used to control motor
* MAX8997_INTERNAL_MODE: internal pulse generator is used to control motor
* @pwm_divisor: divisor for external PWM device
* @internal_mode_pattern: internal mode pattern for internal mode
* [0 - 3]: valid pattern number
* @pattern_cycle: the number of cycles of the waveform
* for the internal mode pattern
* [0 - 15]: available cycles
* @pattern_signal_period: period of the waveform for the internal mode pattern
* [0 - 255]: available period
*/
struct max8997_haptic_platform_data {
unsigned int pwm_channel_id;
unsigned int pwm_period;
enum max8997_haptic_motor_type type;
enum max8997_haptic_pulse_mode mode;
enum max8997_haptic_pwm_divisor pwm_divisor;
unsigned int internal_mode_pattern;
unsigned int pattern_cycle;
unsigned int pattern_signal_period;
};
enum max8997_led_mode {
MAX8997_NONE,
MAX8997_FLASH_MODE,
MAX8997_MOVIE_MODE,
MAX8997_FLASH_PIN_CONTROL_MODE,
MAX8997_MOVIE_PIN_CONTROL_MODE,
};
/**
* struct max8997_led_platform_data
* The number of LED devices for MAX8997 is two
* @mode: LED mode for each LED device
* @brightness: initial brightness for each LED device
* range:
* [0 - 31]: MAX8997_FLASH_MODE and MAX8997_FLASH_PIN_CONTROL_MODE
* [0 - 15]: MAX8997_MOVIE_MODE and MAX8997_MOVIE_PIN_CONTROL_MODE
*/
struct max8997_led_platform_data {
enum max8997_led_mode mode[2];
u8 brightness[2];
};
struct max8997_platform_data {
/* IRQ */
int ono;
int wakeup;
/* ---- PMIC ---- */
struct max8997_regulator_data *regulators;
int num_regulators;
/*
* SET1~3 DVS GPIOs control Buck1, 2, and 5 simultaneously. Therefore,
* With buckx_gpiodvs enabled, the buckx cannot be controlled
* independently. To control buckx (of 1, 2, and 5) independently,
* disable buckx_gpiodvs and control with BUCKxDVS1 register.
*
* When buckx_gpiodvs and bucky_gpiodvs are both enabled, set_voltage
* on buckx will change the voltage of bucky at the same time.
*
*/
bool ignore_gpiodvs_side_effect;
int buck125_gpios[3]; /* GPIO of [0]SET1, [1]SET2, [2]SET3 */
int buck125_default_idx; /* Default value of SET1, 2, 3 */
unsigned int buck1_voltage[8]; /* buckx_voltage in uV */
bool buck1_gpiodvs;
unsigned int buck2_voltage[8];
bool buck2_gpiodvs;
unsigned int buck5_voltage[8];
bool buck5_gpiodvs;
/* ---- Charger control ---- */
/* eoc stands for 'end of charge' */
int eoc_mA; /* 50 ~ 200mA by 10mA step */
/* charge Full Timeout */
int timeout; /* 0 (no timeout), 5, 6, 7 hours */
/* ---- MUIC ---- */
struct max8997_muic_platform_data *muic_pdata;
/* ---- HAPTIC ---- */
struct max8997_haptic_platform_data *haptic_pdata;
/* RTC: Not implemented */
/* ---- LED ---- */
struct max8997_led_platform_data *led_pdata;
};
#endif /* __LINUX_MFD_MAX8998_H */

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/*
* max8998.h - Voltage regulator driver for the Maxim 8998
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* Kyungmin Park <kyungmin.park@samsung.com>
* Marek Szyprowski <m.szyprowski@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8998_PRIV_H
#define __LINUX_MFD_MAX8998_PRIV_H
#define MAX8998_NUM_IRQ_REGS 4
/* MAX 8998 registers */
enum {
MAX8998_REG_IRQ1,
MAX8998_REG_IRQ2,
MAX8998_REG_IRQ3,
MAX8998_REG_IRQ4,
MAX8998_REG_IRQM1,
MAX8998_REG_IRQM2,
MAX8998_REG_IRQM3,
MAX8998_REG_IRQM4,
MAX8998_REG_STATUS1,
MAX8998_REG_STATUS2,
MAX8998_REG_STATUSM1,
MAX8998_REG_STATUSM2,
MAX8998_REG_CHGR1,
MAX8998_REG_CHGR2,
MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_REG_ONOFF1,
MAX8998_REG_ONOFF2,
MAX8998_REG_ONOFF3,
MAX8998_REG_ONOFF4,
MAX8998_REG_BUCK1_VOLTAGE1,
MAX8998_REG_BUCK1_VOLTAGE2,
MAX8998_REG_BUCK1_VOLTAGE3,
MAX8998_REG_BUCK1_VOLTAGE4,
MAX8998_REG_BUCK2_VOLTAGE1,
MAX8998_REG_BUCK2_VOLTAGE2,
MAX8998_REG_BUCK3,
MAX8998_REG_BUCK4,
MAX8998_REG_LDO2_LDO3,
MAX8998_REG_LDO4,
MAX8998_REG_LDO5,
MAX8998_REG_LDO6,
MAX8998_REG_LDO7,
MAX8998_REG_LDO8_LDO9,
MAX8998_REG_LDO10_LDO11,
MAX8998_REG_LDO12,
MAX8998_REG_LDO13,
MAX8998_REG_LDO14,
MAX8998_REG_LDO15,
MAX8998_REG_LDO16,
MAX8998_REG_LDO17,
MAX8998_REG_BKCHR,
MAX8998_REG_LBCNFG1,
MAX8998_REG_LBCNFG2,
};
/* IRQ definitions */
enum {
MAX8998_IRQ_DCINF,
MAX8998_IRQ_DCINR,
MAX8998_IRQ_JIGF,
MAX8998_IRQ_JIGR,
MAX8998_IRQ_PWRONF,
MAX8998_IRQ_PWRONR,
MAX8998_IRQ_WTSREVNT,
MAX8998_IRQ_SMPLEVNT,
MAX8998_IRQ_ALARM1,
MAX8998_IRQ_ALARM0,
MAX8998_IRQ_ONKEY1S,
MAX8998_IRQ_TOPOFFR,
MAX8998_IRQ_DCINOVPR,
MAX8998_IRQ_CHGRSTF,
MAX8998_IRQ_DONER,
MAX8998_IRQ_CHGFAULT,
MAX8998_IRQ_LOBAT1,
MAX8998_IRQ_LOBAT2,
MAX8998_IRQ_NR,
};
/* MAX8998 various variants */
enum {
TYPE_MAX8998 = 0, /* Default */
TYPE_LP3974, /* National version of MAX8998 */
TYPE_LP3979, /* Added AVS */
};
#define MAX8998_IRQ_DCINF_MASK (1 << 2)
#define MAX8998_IRQ_DCINR_MASK (1 << 3)
#define MAX8998_IRQ_JIGF_MASK (1 << 4)
#define MAX8998_IRQ_JIGR_MASK (1 << 5)
#define MAX8998_IRQ_PWRONF_MASK (1 << 6)
#define MAX8998_IRQ_PWRONR_MASK (1 << 7)
#define MAX8998_IRQ_WTSREVNT_MASK (1 << 0)
#define MAX8998_IRQ_SMPLEVNT_MASK (1 << 1)
#define MAX8998_IRQ_ALARM1_MASK (1 << 2)
#define MAX8998_IRQ_ALARM0_MASK (1 << 3)
#define MAX8998_IRQ_ONKEY1S_MASK (1 << 0)
#define MAX8998_IRQ_TOPOFFR_MASK (1 << 2)
#define MAX8998_IRQ_DCINOVPR_MASK (1 << 3)
#define MAX8998_IRQ_CHGRSTF_MASK (1 << 4)
#define MAX8998_IRQ_DONER_MASK (1 << 5)
#define MAX8998_IRQ_CHGFAULT_MASK (1 << 7)
#define MAX8998_IRQ_LOBAT1_MASK (1 << 0)
#define MAX8998_IRQ_LOBAT2_MASK (1 << 1)
#define MAX8998_ENRAMP (1 << 4)
/**
* struct max8998_dev - max8998 master device for sub-drivers
* @dev: master device of the chip (can be used to access platform data)
* @i2c: i2c client private data for regulator
* @rtc: i2c client private data for rtc
* @iolock: mutex for serializing io access
* @irqlock: mutex for buslock
* @irq_base: base IRQ number for max8998, required for IRQs
* @irq: generic IRQ number for max8998
* @ono: power onoff IRQ number for max8998
* @irq_masks_cur: currently active value
* @irq_masks_cache: cached hardware value
* @type: indicate which max8998 "variant" is used
*/
struct max8998_dev {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *rtc;
struct mutex iolock;
struct mutex irqlock;
int irq_base;
int irq;
int ono;
u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
int type;
bool wakeup;
};
int max8998_irq_init(struct max8998_dev *max8998);
void max8998_irq_exit(struct max8998_dev *max8998);
int max8998_irq_resume(struct max8998_dev *max8998);
extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_MAX8998_PRIV_H */

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/*
* max8998.h - Voltage regulator driver for the Maxim 8998
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* Kyungmin Park <kyungmin.park@samsung.com>
* Marek Szyprowski <m.szyprowski@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8998_H
#define __LINUX_MFD_MAX8998_H
#include <linux/regulator/machine.h>
/* MAX 8998 regulator ids */
enum {
MAX8998_LDO2 = 2,
MAX8998_LDO3,
MAX8998_LDO4,
MAX8998_LDO5,
MAX8998_LDO6,
MAX8998_LDO7,
MAX8998_LDO8,
MAX8998_LDO9,
MAX8998_LDO10,
MAX8998_LDO11,
MAX8998_LDO12,
MAX8998_LDO13,
MAX8998_LDO14,
MAX8998_LDO15,
MAX8998_LDO16,
MAX8998_LDO17,
MAX8998_BUCK1,
MAX8998_BUCK2,
MAX8998_BUCK3,
MAX8998_BUCK4,
MAX8998_EN32KHZ_AP,
MAX8998_EN32KHZ_CP,
MAX8998_ENVICHG,
MAX8998_ESAFEOUT1,
MAX8998_ESAFEOUT2,
};
/**
* max8998_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct max8998_regulator_data {
int id;
struct regulator_init_data *initdata;
};
/**
* struct max8998_board - packages regulator init data
* @regulators: array of defined regulators
* @num_regulators: number of regulators used
* @irq_base: base IRQ number for max8998, required for IRQs
* @ono: power onoff IRQ number for max8998
* @buck_voltage_lock: Do NOT change the values of the following six
* registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
* be other than the preset values.
* @buck1_voltage1: BUCK1 DVS mode 1 voltage register
* @buck1_voltage2: BUCK1 DVS mode 2 voltage register
* @buck1_voltage3: BUCK1 DVS mode 3 voltage register
* @buck1_voltage4: BUCK1 DVS mode 4 voltage register
* @buck2_voltage1: BUCK2 DVS mode 1 voltage register
* @buck2_voltage2: BUCK2 DVS mode 2 voltage register
* @buck1_set1: BUCK1 gpio pin 1 to set output voltage
* @buck1_set2: BUCK1 gpio pin 2 to set output voltage
* @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
* @buck2_set3: BUCK2 gpio pin to set output voltage
* @buck2_default_idx: Default for BUCK2 gpio pin.
* @wakeup: Allow to wake up from suspend
* @rtc_delay: LP3974 RTC chip bug that requires delay after a register
* write before reading it.
* @eoc: End of Charge Level in percent: 10% ~ 45% by 5% step
* If it equals 0, leave it unchanged.
* Otherwise, it is a invalid value.
* @restart: Restart Level in mV: 100, 150, 200, and -1 for disable.
* If it equals 0, leave it unchanged.
* Otherwise, it is a invalid value.
* @timeout: Full Timeout in hours: 5, 6, 7, and -1 for disable.
* If it equals 0, leave it unchanged.
* Otherwise, leave it unchanged.
*/
struct max8998_platform_data {
struct max8998_regulator_data *regulators;
int num_regulators;
int irq_base;
int ono;
bool buck_voltage_lock;
int buck1_voltage1;
int buck1_voltage2;
int buck1_voltage3;
int buck1_voltage4;
int buck2_voltage1;
int buck2_voltage2;
int buck1_set1;
int buck1_set2;
int buck1_default_idx;
int buck2_set3;
int buck2_default_idx;
bool wakeup;
bool rtc_delay;
int eoc;
int restart;
int timeout;
};
#endif /* __LINUX_MFD_MAX8998_H */

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/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13783_H
#define __LINUX_MFD_MC13783_H
#include <linux/mfd/mc13xxx.h>
#define MC13783_REG_SW1A 0
#define MC13783_REG_SW1B 1
#define MC13783_REG_SW2A 2
#define MC13783_REG_SW2B 3
#define MC13783_REG_SW3 4
#define MC13783_REG_PLL 5
#define MC13783_REG_VAUDIO 6
#define MC13783_REG_VIOHI 7
#define MC13783_REG_VIOLO 8
#define MC13783_REG_VDIG 9
#define MC13783_REG_VGEN 10
#define MC13783_REG_VRFDIG 11
#define MC13783_REG_VRFREF 12
#define MC13783_REG_VRFCP 13
#define MC13783_REG_VSIM 14
#define MC13783_REG_VESIM 15
#define MC13783_REG_VCAM 16
#define MC13783_REG_VRFBG 17
#define MC13783_REG_VVIB 18
#define MC13783_REG_VRF1 19
#define MC13783_REG_VRF2 20
#define MC13783_REG_VMMC1 21
#define MC13783_REG_VMMC2 22
#define MC13783_REG_GPO1 23
#define MC13783_REG_GPO2 24
#define MC13783_REG_GPO3 25
#define MC13783_REG_GPO4 26
#define MC13783_REG_V1 27
#define MC13783_REG_V2 28
#define MC13783_REG_V3 29
#define MC13783_REG_V4 30
#define MC13783_REG_PWGT1SPI 31
#define MC13783_REG_PWGT2SPI 32
#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
#define MC13783_IRQ_TS MC13XXX_IRQ_TS
#define MC13783_IRQ_WHIGH 3
#define MC13783_IRQ_WLOW 4
#define MC13783_IRQ_CHGDET MC13XXX_IRQ_CHGDET
#define MC13783_IRQ_CHGOV 7
#define MC13783_IRQ_CHGREV MC13XXX_IRQ_CHGREV
#define MC13783_IRQ_CHGSHORT MC13XXX_IRQ_CHGSHORT
#define MC13783_IRQ_CCCV MC13XXX_IRQ_CCCV
#define MC13783_IRQ_CHGCURR MC13XXX_IRQ_CHGCURR
#define MC13783_IRQ_BPON MC13XXX_IRQ_BPON
#define MC13783_IRQ_LOBATL MC13XXX_IRQ_LOBATL
#define MC13783_IRQ_LOBATH MC13XXX_IRQ_LOBATH
#define MC13783_IRQ_UDP 15
#define MC13783_IRQ_USB 16
#define MC13783_IRQ_ID 19
#define MC13783_IRQ_SE1 21
#define MC13783_IRQ_CKDET 22
#define MC13783_IRQ_UDM 23
#define MC13783_IRQ_1HZ MC13XXX_IRQ_1HZ
#define MC13783_IRQ_TODA MC13XXX_IRQ_TODA
#define MC13783_IRQ_ONOFD1 27
#define MC13783_IRQ_ONOFD2 28
#define MC13783_IRQ_ONOFD3 29
#define MC13783_IRQ_SYSRST MC13XXX_IRQ_SYSRST
#define MC13783_IRQ_RTCRST MC13XXX_IRQ_RTCRST
#define MC13783_IRQ_PC MC13XXX_IRQ_PC
#define MC13783_IRQ_WARM MC13XXX_IRQ_WARM
#define MC13783_IRQ_MEMHLD MC13XXX_IRQ_MEMHLD
#define MC13783_IRQ_PWRRDY 35
#define MC13783_IRQ_THWARNL MC13XXX_IRQ_THWARNL
#define MC13783_IRQ_THWARNH MC13XXX_IRQ_THWARNH
#define MC13783_IRQ_CLK MC13XXX_IRQ_CLK
#define MC13783_IRQ_SEMAF 39
#define MC13783_IRQ_MC2B 41
#define MC13783_IRQ_HSDET 42
#define MC13783_IRQ_HSL 43
#define MC13783_IRQ_ALSPTH 44
#define MC13783_IRQ_AHSSHORT 45
#define MC13783_NUM_IRQ MC13XXX_NUM_IRQ
#endif /* ifndef __LINUX_MFD_MC13783_H */

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/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13892_H
#define __LINUX_MFD_MC13892_H
#include <linux/mfd/mc13xxx.h>
#define MC13892_SW1 0
#define MC13892_SW2 1
#define MC13892_SW3 2
#define MC13892_SW4 3
#define MC13892_SWBST 4
#define MC13892_VIOHI 5
#define MC13892_VPLL 6
#define MC13892_VDIG 7
#define MC13892_VSD 8
#define MC13892_VUSB2 9
#define MC13892_VVIDEO 10
#define MC13892_VAUDIO 11
#define MC13892_VCAM 12
#define MC13892_VGEN1 13
#define MC13892_VGEN2 14
#define MC13892_VGEN3 15
#define MC13892_VUSB 16
#define MC13892_GPO1 17
#define MC13892_GPO2 18
#define MC13892_GPO3 19
#define MC13892_GPO4 20
#define MC13892_PWGT1SPI 21
#define MC13892_PWGT2SPI 22
#define MC13892_VCOINCELL 23
#endif

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/*
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13XXX_H
#define __LINUX_MFD_MC13XXX_H
#include <linux/interrupt.h>
struct mc13xxx;
void mc13xxx_lock(struct mc13xxx *mc13xxx);
void mc13xxx_unlock(struct mc13xxx *mc13xxx);
int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val);
int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val);
int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
u32 mask, u32 val);
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
irq_handler_t handler, const char *name, void *dev);
int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
irq_handler_t handler, const char *name, void *dev);
int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev);
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
int *enabled, int *pending);
int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
unsigned int mode, unsigned int channel,
u8 ato, bool atox, unsigned int *sample);
#define MC13XXX_IRQ_ADCDONE 0
#define MC13XXX_IRQ_ADCBISDONE 1
#define MC13XXX_IRQ_TS 2
#define MC13XXX_IRQ_CHGDET 6
#define MC13XXX_IRQ_CHGREV 8
#define MC13XXX_IRQ_CHGSHORT 9
#define MC13XXX_IRQ_CCCV 10
#define MC13XXX_IRQ_CHGCURR 11
#define MC13XXX_IRQ_BPON 12
#define MC13XXX_IRQ_LOBATL 13
#define MC13XXX_IRQ_LOBATH 14
#define MC13XXX_IRQ_1HZ 24
#define MC13XXX_IRQ_TODA 25
#define MC13XXX_IRQ_SYSRST 30
#define MC13XXX_IRQ_RTCRST 31
#define MC13XXX_IRQ_PC 32
#define MC13XXX_IRQ_WARM 33
#define MC13XXX_IRQ_MEMHLD 34
#define MC13XXX_IRQ_THWARNL 36
#define MC13XXX_IRQ_THWARNH 37
#define MC13XXX_IRQ_CLK 38
#define MC13XXX_NUM_IRQ 46
struct regulator_init_data;
struct mc13xxx_regulator_init_data {
int id;
struct regulator_init_data *init_data;
struct device_node *node;
};
struct mc13xxx_regulator_platform_data {
int num_regulators;
struct mc13xxx_regulator_init_data *regulators;
};
struct mc13xxx_led_platform_data {
#define MC13783_LED_MD 0
#define MC13783_LED_AD 1
#define MC13783_LED_KP 2
#define MC13783_LED_R1 3
#define MC13783_LED_G1 4
#define MC13783_LED_B1 5
#define MC13783_LED_R2 6
#define MC13783_LED_G2 7
#define MC13783_LED_B2 8
#define MC13783_LED_R3 9
#define MC13783_LED_G3 10
#define MC13783_LED_B3 11
#define MC13783_LED_MAX MC13783_LED_B3
int id;
const char *name;
const char *default_trigger;
/* Three or two bits current selection depending on the led */
char max_current;
};
struct mc13xxx_leds_platform_data {
int num_leds;
struct mc13xxx_led_platform_data *led;
#define MC13783_LED_TRIODE_MD (1 << 0)
#define MC13783_LED_TRIODE_AD (1 << 1)
#define MC13783_LED_TRIODE_KP (1 << 2)
#define MC13783_LED_BOOST_EN (1 << 3)
#define MC13783_LED_TC1HALF (1 << 4)
#define MC13783_LED_SLEWLIMTC (1 << 5)
#define MC13783_LED_SLEWLIMBL (1 << 6)
#define MC13783_LED_TRIODE_TC1 (1 << 7)
#define MC13783_LED_TRIODE_TC2 (1 << 8)
#define MC13783_LED_TRIODE_TC3 (1 << 9)
int flags;
#define MC13783_LED_AB_DISABLED 0
#define MC13783_LED_AB_MD1 1
#define MC13783_LED_AB_MD12 2
#define MC13783_LED_AB_MD123 3
#define MC13783_LED_AB_MD1234 4
#define MC13783_LED_AB_MD1234_AD1 5
#define MC13783_LED_AB_MD1234_AD12 6
#define MC13783_LED_AB_MD1_AD 7
char abmode;
#define MC13783_LED_ABREF_200MV 0
#define MC13783_LED_ABREF_400MV 1
#define MC13783_LED_ABREF_600MV 2
#define MC13783_LED_ABREF_800MV 3
char abref;
#define MC13783_LED_PERIOD_10MS 0
#define MC13783_LED_PERIOD_100MS 1
#define MC13783_LED_PERIOD_500MS 2
#define MC13783_LED_PERIOD_2S 3
char bl_period;
char tc1_period;
char tc2_period;
char tc3_period;
};
struct mc13xxx_buttons_platform_data {
#define MC13783_BUTTON_DBNC_0MS 0
#define MC13783_BUTTON_DBNC_30MS 1
#define MC13783_BUTTON_DBNC_150MS 2
#define MC13783_BUTTON_DBNC_750MS 3
#define MC13783_BUTTON_ENABLE (1 << 2)
#define MC13783_BUTTON_POL_INVERT (1 << 3)
#define MC13783_BUTTON_RESET_EN (1 << 4)
int b1on_flags;
unsigned short b1on_key;
int b2on_flags;
unsigned short b2on_key;
int b3on_flags;
unsigned short b3on_key;
};
struct mc13xxx_ts_platform_data {
/* Delay between Touchscreen polarization and ADC Conversion.
* Given in clock ticks of a 32 kHz clock which gives a granularity of
* about 30.5ms */
u8 ato;
#define MC13783_TS_ATO_FIRST false
#define MC13783_TS_ATO_EACH true
/* Use the ATO delay only for the first conversion or for each one */
bool atox;
};
enum mc13783_ssi_port {
MC13783_SSI1_PORT,
MC13783_SSI2_PORT,
};
struct mc13xxx_codec_platform_data {
enum mc13783_ssi_port adc_ssi_port;
enum mc13783_ssi_port dac_ssi_port;
};
struct mc13xxx_platform_data {
#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
#define MC13XXX_USE_CODEC (1 << 1)
#define MC13XXX_USE_ADC (1 << 2)
#define MC13XXX_USE_RTC (1 << 3)
unsigned int flags;
struct mc13xxx_regulator_platform_data regulators;
struct mc13xxx_leds_platform_data *leds;
struct mc13xxx_buttons_platform_data *buttons;
struct mc13xxx_ts_platform_data touch;
struct mc13xxx_codec_platform_data *codec;
};
#define MC13XXX_ADC_MODE_TS 1
#define MC13XXX_ADC_MODE_SINGLE_CHAN 2
#define MC13XXX_ADC_MODE_MULT_CHAN 3
#define MC13XXX_ADC0 43
#define MC13XXX_ADC0_LICELLCON (1 << 0)
#define MC13XXX_ADC0_CHRGICON (1 << 1)
#define MC13XXX_ADC0_BATICON (1 << 2)
#define MC13XXX_ADC0_ADREFEN (1 << 10)
#define MC13XXX_ADC0_TSMOD0 (1 << 12)
#define MC13XXX_ADC0_TSMOD1 (1 << 13)
#define MC13XXX_ADC0_TSMOD2 (1 << 14)
#define MC13XXX_ADC0_ADINC1 (1 << 16)
#define MC13XXX_ADC0_ADINC2 (1 << 17)
#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \
MC13XXX_ADC0_TSMOD1 | \
MC13XXX_ADC0_TSMOD2)
#define MC13XXX_ADC0_CONFIG_MASK (MC13XXX_ADC0_TSMOD_MASK | \
MC13XXX_ADC0_LICELLCON | \
MC13XXX_ADC0_CHRGICON | \
MC13XXX_ADC0_BATICON)
#endif /* ifndef __LINUX_MFD_MC13XXX_H */

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/*
* linux/drivers/mfd/mcp.h
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#ifndef MCP_H
#define MCP_H
struct mcp_ops;
struct mcp {
struct module *owner;
struct mcp_ops *ops;
spinlock_t lock;
int use_count;
unsigned int sclk_rate;
unsigned int rw_timeout;
struct device attached_device;
};
struct mcp_ops {
void (*set_telecom_divisor)(struct mcp *, unsigned int);
void (*set_audio_divisor)(struct mcp *, unsigned int);
void (*reg_write)(struct mcp *, unsigned int, unsigned int);
unsigned int (*reg_read)(struct mcp *, unsigned int);
void (*enable)(struct mcp *);
void (*disable)(struct mcp *);
};
void mcp_set_telecom_divisor(struct mcp *, unsigned int);
void mcp_set_audio_divisor(struct mcp *, unsigned int);
void mcp_reg_write(struct mcp *, unsigned int, unsigned int);
unsigned int mcp_reg_read(struct mcp *, unsigned int);
void mcp_enable(struct mcp *);
void mcp_disable(struct mcp *);
#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate)
struct mcp *mcp_host_alloc(struct device *, size_t);
int mcp_host_add(struct mcp *, void *);
void mcp_host_del(struct mcp *);
void mcp_host_free(struct mcp *);
struct mcp_driver {
struct device_driver drv;
int (*probe)(struct mcp *);
void (*remove)(struct mcp *);
};
int mcp_driver_register(struct mcp_driver *);
void mcp_driver_unregister(struct mcp_driver *);
#define mcp_get_drvdata(mcp) dev_get_drvdata(&(mcp)->attached_device)
#define mcp_set_drvdata(mcp,d) dev_set_drvdata(&(mcp)->attached_device, d)
static inline void *mcp_priv(struct mcp *mcp)
{
return mcp + 1;
}
#endif

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/*
* Functions to access Menelaus power management chip
*/
#ifndef __ASM_ARCH_MENELAUS_H
#define __ASM_ARCH_MENELAUS_H
struct device;
struct menelaus_platform_data {
int (* late_init)(struct device *dev);
};
extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
void *data);
extern void menelaus_unregister_mmc_callback(void);
extern int menelaus_set_mmc_opendrain(int slot, int enable);
extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
extern int menelaus_set_vmem(unsigned int mV);
extern int menelaus_set_vio(unsigned int mV);
extern int menelaus_set_vmmc(unsigned int mV);
extern int menelaus_set_vaux(unsigned int mV);
extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
extern int menelaus_set_slot_sel(int enable);
extern int menelaus_get_slot_pin_states(void);
extern int menelaus_set_vcore_sw(unsigned int mV);
extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
#define EN_VPLL_SLEEP (1 << 7)
#define EN_VMMC_SLEEP (1 << 6)
#define EN_VAUX_SLEEP (1 << 5)
#define EN_VIO_SLEEP (1 << 4)
#define EN_VMEM_SLEEP (1 << 3)
#define EN_DC3_SLEEP (1 << 2)
#define EN_DC2_SLEEP (1 << 1)
#define EN_VC_SLEEP (1 << 0)
extern int menelaus_set_regulator_sleep(int enable, u32 val);
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
#define omap_has_menelaus() 1
#else
#define omap_has_menelaus() 0
#endif
#endif

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/*
* adc.h -- Driver for NXP PCF50633 ADC
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_ADC_H
#define __LINUX_MFD_PCF50633_ADC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
/* ADC Registers */
#define PCF50633_REG_ADCC3 0x52
#define PCF50633_REG_ADCC2 0x53
#define PCF50633_REG_ADCC1 0x54
#define PCF50633_REG_ADCS1 0x55
#define PCF50633_REG_ADCS2 0x56
#define PCF50633_REG_ADCS3 0x57
#define PCF50633_ADCC1_ADCSTART 0x01
#define PCF50633_ADCC1_RES_8BIT 0x02
#define PCF50633_ADCC1_RES_10BIT 0x00
#define PCF50633_ADCC1_AVERAGE_NO 0x00
#define PCF50633_ADCC1_AVERAGE_4 0x04
#define PCF50633_ADCC1_AVERAGE_8 0x08
#define PCF50633_ADCC1_AVERAGE_16 0x0c
#define PCF50633_ADCC1_MUX_BATSNS_RES 0x00
#define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
#define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20
#define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
#define PCF50633_ADCC1_MUX_BATTEMP 0x60
#define PCF50633_ADCC1_MUX_ADCIN1 0x70
#define PCF50633_ADCC1_AVERAGE_MASK 0x0c
#define PCF50633_ADCC1_ADCMUX_MASK 0xf0
#define PCF50633_ADCC2_RATIO_NONE 0x00
#define PCF50633_ADCC2_RATIO_BATTEMP 0x01
#define PCF50633_ADCC2_RATIO_ADCIN1 0x02
#define PCF50633_ADCC2_RATIO_BOTH 0x03
#define PCF50633_ADCC2_RATIOSETTL_100US 0x04
#define PCF50633_ADCC3_ACCSW_EN 0x01
#define PCF50633_ADCC3_NTCSW_EN 0x04
#define PCF50633_ADCC3_RES_DIV_TWO 0x10
#define PCF50633_ADCC3_RES_DIV_THREE 0x00
#define PCF50633_ADCS3_REF_NTCSW 0x00
#define PCF50633_ADCS3_REF_ACCSW 0x10
#define PCF50633_ADCS3_REF_2V0 0x20
#define PCF50633_ADCS3_REF_VISA 0x30
#define PCF50633_ADCS3_REF_2V0_2 0x70
#define PCF50633_ADCS3_ADCRDY 0x80
#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03
#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c
#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2
#define PCF50633_ASCS3_REF_MASK 0x70
extern int
pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
void (*callback)(struct pcf50633 *, void *, int),
void *callback_param);
extern int
pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
#endif /* __LINUX_PCF50633_ADC_H */

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/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* PCF50633 backlight device driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __LINUX_MFD_PCF50633_BACKLIGHT
#define __LINUX_MFD_PCF50633_BACKLIGHT
/*
* @default_brightness: Backlight brightness is initialized to this value
*
* Brightness to be used after the driver has been probed.
* Valid range 0-63.
*
* @default_brightness_limit: The actual brightness is limited by this value
*
* Brightness limit to be used after the driver has been probed. This is useful
* when it is not known how much power is available for the backlight during
* probe.
* Valid range 0-63. Can be changed later with pcf50633_bl_set_brightness_limit.
*
* @ramp_time: Display ramp time when changing brightness
*
* When changing the backlights brightness the change is not instant, instead
* it fades smooth from one state to another. This value specifies how long
* the fade should take. The lower the value the higher the fade time.
* Valid range 0-255
*/
struct pcf50633_bl_platform_data {
unsigned int default_brightness;
unsigned int default_brightness_limit;
uint8_t ramp_time;
};
struct pcf50633;
int pcf50633_bl_set_brightness_limit(struct pcf50633 *pcf, unsigned int limit);
#endif

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/*
* core.h -- Core driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_CORE_H
#define __LINUX_MFD_PCF50633_CORE_H
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/power_supply.h>
#include <linux/mfd/pcf50633/backlight.h>
struct pcf50633;
struct regmap;
#define PCF50633_NUM_REGULATORS 11
struct pcf50633_platform_data {
struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
char **batteries;
int num_batteries;
/*
* Should be set accordingly to the reference resistor used, see
* I_{ch(ref)} charger reference current in the pcf50633 User
* Manual.
*/
int charger_reference_current_ma;
/* Callbacks */
void (*probe_done)(struct pcf50633 *);
void (*mbc_event_callback)(struct pcf50633 *, int);
void (*regulator_registered)(struct pcf50633 *, int);
void (*force_shutdown)(struct pcf50633 *);
u8 resumers[5];
struct pcf50633_bl_platform_data *backlight_data;
};
struct pcf50633_irq {
void (*handler) (int, void *);
void *data;
};
int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
void (*handler) (int, void *), void *data);
int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
int pcf50633_read_block(struct pcf50633 *, u8 reg,
int nr_regs, u8 *data);
int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
int nr_regs, u8 *data);
u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
/* Interrupt registers */
#define PCF50633_REG_INT1 0x02
#define PCF50633_REG_INT2 0x03
#define PCF50633_REG_INT3 0x04
#define PCF50633_REG_INT4 0x05
#define PCF50633_REG_INT5 0x06
#define PCF50633_REG_INT1M 0x07
#define PCF50633_REG_INT2M 0x08
#define PCF50633_REG_INT3M 0x09
#define PCF50633_REG_INT4M 0x0a
#define PCF50633_REG_INT5M 0x0b
enum {
/* Chip IRQs */
PCF50633_IRQ_ADPINS,
PCF50633_IRQ_ADPREM,
PCF50633_IRQ_USBINS,
PCF50633_IRQ_USBREM,
PCF50633_IRQ_RESERVED1,
PCF50633_IRQ_RESERVED2,
PCF50633_IRQ_ALARM,
PCF50633_IRQ_SECOND,
PCF50633_IRQ_ONKEYR,
PCF50633_IRQ_ONKEYF,
PCF50633_IRQ_EXTON1R,
PCF50633_IRQ_EXTON1F,
PCF50633_IRQ_EXTON2R,
PCF50633_IRQ_EXTON2F,
PCF50633_IRQ_EXTON3R,
PCF50633_IRQ_EXTON3F,
PCF50633_IRQ_BATFULL,
PCF50633_IRQ_CHGHALT,
PCF50633_IRQ_THLIMON,
PCF50633_IRQ_THLIMOFF,
PCF50633_IRQ_USBLIMON,
PCF50633_IRQ_USBLIMOFF,
PCF50633_IRQ_ADCRDY,
PCF50633_IRQ_ONKEY1S,
PCF50633_IRQ_LOWSYS,
PCF50633_IRQ_LOWBAT,
PCF50633_IRQ_HIGHTMP,
PCF50633_IRQ_AUTOPWRFAIL,
PCF50633_IRQ_DWN1PWRFAIL,
PCF50633_IRQ_DWN2PWRFAIL,
PCF50633_IRQ_LEDPWRFAIL,
PCF50633_IRQ_LEDOVP,
PCF50633_IRQ_LDO1PWRFAIL,
PCF50633_IRQ_LDO2PWRFAIL,
PCF50633_IRQ_LDO3PWRFAIL,
PCF50633_IRQ_LDO4PWRFAIL,
PCF50633_IRQ_LDO5PWRFAIL,
PCF50633_IRQ_LDO6PWRFAIL,
PCF50633_IRQ_HCLDOPWRFAIL,
PCF50633_IRQ_HCLDOOVL,
/* Always last */
PCF50633_NUM_IRQ,
};
struct pcf50633 {
struct device *dev;
struct regmap *regmap;
struct pcf50633_platform_data *pdata;
int irq;
struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
struct work_struct irq_work;
struct workqueue_struct *work_queue;
struct mutex lock;
u8 mask_regs[5];
u8 suspend_irq_masks[5];
u8 resume_reason[5];
int is_suspended;
int onkey1s_held;
struct platform_device *rtc_pdev;
struct platform_device *mbc_pdev;
struct platform_device *adc_pdev;
struct platform_device *input_pdev;
struct platform_device *bl_pdev;
struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
};
enum pcf50633_reg_int1 {
PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
PCF50633_INT1_USBINS = 0x04, /* USB inserted */
PCF50633_INT1_USBREM = 0x08, /* USB removed */
/* reserved */
PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
};
enum pcf50633_reg_int2 {
PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
};
enum pcf50633_reg_int3 {
PCF50633_INT3_BATFULL = 0x01, /* Battery full */
PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
PCF50633_INT3_THLIMON = 0x04,
PCF50633_INT3_THLIMOFF = 0x08,
PCF50633_INT3_USBLIMON = 0x10,
PCF50633_INT3_USBLIMOFF = 0x20,
PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
};
enum pcf50633_reg_int4 {
PCF50633_INT4_LOWSYS = 0x01,
PCF50633_INT4_LOWBAT = 0x02,
PCF50633_INT4_HIGHTMP = 0x04,
PCF50633_INT4_AUTOPWRFAIL = 0x08,
PCF50633_INT4_DWN1PWRFAIL = 0x10,
PCF50633_INT4_DWN2PWRFAIL = 0x20,
PCF50633_INT4_LEDPWRFAIL = 0x40,
PCF50633_INT4_LEDOVP = 0x80,
};
enum pcf50633_reg_int5 {
PCF50633_INT5_LDO1PWRFAIL = 0x01,
PCF50633_INT5_LDO2PWRFAIL = 0x02,
PCF50633_INT5_LDO3PWRFAIL = 0x04,
PCF50633_INT5_LDO4PWRFAIL = 0x08,
PCF50633_INT5_LDO5PWRFAIL = 0x10,
PCF50633_INT5_LDO6PWRFAIL = 0x20,
PCF50633_INT5_HCLDOPWRFAIL = 0x40,
PCF50633_INT5_HCLDOOVL = 0x80,
};
/* misc. registers */
#define PCF50633_REG_OOCSHDWN 0x0c
/* LED registers */
#define PCF50633_REG_LEDOUT 0x28
#define PCF50633_REG_LEDENA 0x29
#define PCF50633_REG_LEDCTL 0x2a
#define PCF50633_REG_LEDDIM 0x2b
static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
{
return dev_get_drvdata(dev);
}
int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
void pcf50633_irq_free(struct pcf50633 *pcf);
#ifdef CONFIG_PM
int pcf50633_irq_suspend(struct pcf50633 *pcf);
int pcf50633_irq_resume(struct pcf50633 *pcf);
#endif
#endif

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include/linux/mfd/pcf50633/gpio.h Normal file
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/*
* gpio.h -- GPIO driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_GPIO_H
#define __LINUX_MFD_PCF50633_GPIO_H
#include <linux/mfd/pcf50633/core.h>
#define PCF50633_GPIO1 1
#define PCF50633_GPIO2 2
#define PCF50633_GPIO3 3
#define PCF50633_GPO 4
#define PCF50633_REG_GPIO1CFG 0x14
#define PCF50633_REG_GPIO2CFG 0x15
#define PCF50633_REG_GPIO3CFG 0x16
#define PCF50633_REG_GPOCFG 0x17
#define PCF50633_GPOCFG_GPOSEL_MASK 0x07
enum pcf50633_reg_gpocfg {
PCF50633_GPOCFG_GPOSEL_0 = 0x00,
PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02,
PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03,
PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04,
PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05,
PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06,
PCF50633_GPOCFG_GPOSEL_1 = 0x07,
PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08,
};
int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val);
u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_power_supply_set(struct pcf50633 *,
int gpio, int regulator, int on);
#endif /* __LINUX_MFD_PCF50633_GPIO_H */

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/*
* mbc.h -- Driver for NXP PCF50633 Main Battery Charger
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_MBC_H
#define __LINUX_MFD_PCF50633_MBC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_MBCC1 0x43
#define PCF50633_REG_MBCC2 0x44
#define PCF50633_REG_MBCC3 0x45
#define PCF50633_REG_MBCC4 0x46
#define PCF50633_REG_MBCC5 0x47
#define PCF50633_REG_MBCC6 0x48
#define PCF50633_REG_MBCC7 0x49
#define PCF50633_REG_MBCC8 0x4a
#define PCF50633_REG_MBCS1 0x4b
#define PCF50633_REG_MBCS2 0x4c
#define PCF50633_REG_MBCS3 0x4d
enum pcf50633_reg_mbcc1 {
PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
PCF50633_MBCC1_AUTOSTOP = 0x02,
PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
PCF50633_MBCC1_WDTIME_1H = 0x00,
PCF50633_MBCC1_WDTIME_2H = 0x40,
PCF50633_MBCC1_WDTIME_4H = 0x80,
PCF50633_MBCC1_WDTIME_6H = 0xc0,
};
#define PCF50633_MBCC1_WDTIME_MASK 0xc0
enum pcf50633_reg_mbcc2 {
PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
PCF50633_MBCC2_VMAX_4V = 0x00,
PCF50633_MBCC2_VMAX_4V20 = 0x28,
PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
};
enum pcf50633_reg_mbcc7 {
PCF50633_MBCC7_USB_100mA = 0x00,
PCF50633_MBCC7_USB_500mA = 0x01,
PCF50633_MBCC7_USB_1000mA = 0x02,
PCF50633_MBCC7_USB_SUSPEND = 0x03,
PCF50633_MBCC7_BATTEMP_EN = 0x04,
PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00,
PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40,
PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80,
PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0,
};
#define PCF50633_MBCC7_USB_MASK 0x03
enum pcf50633_reg_mbcc8 {
PCF50633_MBCC8_USBENASUS = 0x10,
};
enum pcf50633_reg_mbcs1 {
PCF50633_MBCS1_USBPRES = 0x01,
PCF50633_MBCS1_USBOK = 0x02,
PCF50633_MBCS1_ADAPTPRES = 0x04,
PCF50633_MBCS1_ADAPTOK = 0x08,
PCF50633_MBCS1_TBAT_OK = 0x00,
PCF50633_MBCS1_TBAT_ABOVE = 0x10,
PCF50633_MBCS1_TBAT_BELOW = 0x20,
PCF50633_MBCS1_TBAT_UNDEF = 0x30,
PCF50633_MBCS1_PREWDTEXP = 0x40,
PCF50633_MBCS1_WDTEXP = 0x80,
};
enum pcf50633_reg_mbcs2_mbcmod {
PCF50633_MBCS2_MBC_PLAY = 0x00,
PCF50633_MBCS2_MBC_USB_PRE = 0x01,
PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
PCF50633_MBCS2_MBC_USB_FAST = 0x03,
PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05,
PCF50633_MBCS2_MBC_ADP_PRE = 0x06,
PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
PCF50633_MBCS2_MBC_ADP_FAST = 0x08,
PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
PCF50633_MBCS2_MBC_BAT_FULL = 0x0a,
PCF50633_MBCS2_MBC_HALT = 0x0b,
};
#define PCF50633_MBCS2_MBC_MASK 0x0f
enum pcf50633_reg_mbcs2_chgstat {
PCF50633_MBCS2_CHGS_NONE = 0x00,
PCF50633_MBCS2_CHGS_ADAPTER = 0x10,
PCF50633_MBCS2_CHGS_USB = 0x20,
PCF50633_MBCS2_CHGS_BOTH = 0x30,
};
#define PCF50633_MBCS2_RESSTAT_AUTO 0x40
enum pcf50633_reg_mbcs3 {
PCF50633_MBCS3_USBLIM_PLAY = 0x01,
PCF50633_MBCS3_USBLIM_CGH = 0x02,
PCF50633_MBCS3_TLIM_PLAY = 0x04,
PCF50633_MBCS3_TLIM_CHG = 0x08,
PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */
PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */
PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */
PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */
};
#define PCF50633_MBCC2_VBATCOND_MASK 0x03
#define PCF50633_MBCC2_VMAX_MASK 0x3c
/* Charger status */
#define PCF50633_MBC_USB_ONLINE 0x01
#define PCF50633_MBC_USB_ACTIVE 0x02
#define PCF50633_MBC_ADAPTER_ONLINE 0x04
#define PCF50633_MBC_ADAPTER_ACTIVE 0x08
int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
int pcf50633_mbc_get_status(struct pcf50633 *);
int pcf50633_mbc_get_usb_online_status(struct pcf50633 *);
#endif

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#ifndef __LINUX_MFD_PCF50633_PMIC_H
#define __LINUX_MFD_PCF50633_PMIC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_AUTOOUT 0x1a
#define PCF50633_REG_AUTOENA 0x1b
#define PCF50633_REG_AUTOCTL 0x1c
#define PCF50633_REG_AUTOMXC 0x1d
#define PCF50633_REG_DOWN1OUT 0x1e
#define PCF50633_REG_DOWN1ENA 0x1f
#define PCF50633_REG_DOWN1CTL 0x20
#define PCF50633_REG_DOWN1MXC 0x21
#define PCF50633_REG_DOWN2OUT 0x22
#define PCF50633_REG_DOWN2ENA 0x23
#define PCF50633_REG_DOWN2CTL 0x24
#define PCF50633_REG_DOWN2MXC 0x25
#define PCF50633_REG_MEMLDOOUT 0x26
#define PCF50633_REG_MEMLDOENA 0x27
#define PCF50633_REG_LDO1OUT 0x2d
#define PCF50633_REG_LDO1ENA 0x2e
#define PCF50633_REG_LDO2OUT 0x2f
#define PCF50633_REG_LDO2ENA 0x30
#define PCF50633_REG_LDO3OUT 0x31
#define PCF50633_REG_LDO3ENA 0x32
#define PCF50633_REG_LDO4OUT 0x33
#define PCF50633_REG_LDO4ENA 0x34
#define PCF50633_REG_LDO5OUT 0x35
#define PCF50633_REG_LDO5ENA 0x36
#define PCF50633_REG_LDO6OUT 0x37
#define PCF50633_REG_LDO6ENA 0x38
#define PCF50633_REG_HCLDOOUT 0x39
#define PCF50633_REG_HCLDOENA 0x3a
#define PCF50633_REG_HCLDOOVL 0x40
enum pcf50633_regulator_enable {
PCF50633_REGULATOR_ON = 0x01,
PCF50633_REGULATOR_ON_GPIO1 = 0x02,
PCF50633_REGULATOR_ON_GPIO2 = 0x04,
PCF50633_REGULATOR_ON_GPIO3 = 0x08,
};
#define PCF50633_REGULATOR_ON_MASK 0x0f
enum pcf50633_regulator_phase {
PCF50633_REGULATOR_ACTPH1 = 0x00,
PCF50633_REGULATOR_ACTPH2 = 0x10,
PCF50633_REGULATOR_ACTPH3 = 0x20,
PCF50633_REGULATOR_ACTPH4 = 0x30,
};
#define PCF50633_REGULATOR_ACTPH_MASK 0x30
enum pcf50633_regulator_id {
PCF50633_REGULATOR_AUTO,
PCF50633_REGULATOR_DOWN1,
PCF50633_REGULATOR_DOWN2,
PCF50633_REGULATOR_LDO1,
PCF50633_REGULATOR_LDO2,
PCF50633_REGULATOR_LDO3,
PCF50633_REGULATOR_LDO4,
PCF50633_REGULATOR_LDO5,
PCF50633_REGULATOR_LDO6,
PCF50633_REGULATOR_HCLDO,
PCF50633_REGULATOR_MEMLDO,
};
#endif

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include/linux/mfd/pm8xxx/core.h Normal file
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/*
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8xxx driver header file
*
*/
#ifndef __MFD_PM8XXX_CORE_H
#define __MFD_PM8XXX_CORE_H
#include <linux/mfd/core.h>
struct pm8xxx_drvdata {
int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
int n);
int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
int n);
int (*pmic_read_irq_stat) (const struct device *dev, int irq);
void *pm_chip_data;
};
static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_readb(dev, addr, val);
}
static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_writeb(dev, addr, val);
}
static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
int n)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_read_buf(dev, addr, buf, n);
}
static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
int n)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_write_buf(dev, addr, buf, n);
}
static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_read_irq_stat(dev, irq);
}
#endif

59
include/linux/mfd/pm8xxx/irq.h Normal file
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/*
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC irq 8xxx driver header file
*
*/
#ifndef __MFD_PM8XXX_IRQ_H
#define __MFD_PM8XXX_IRQ_H
#include <linux/errno.h>
#include <linux/err.h>
struct pm8xxx_irq_core_data {
u32 rev;
int nirqs;
};
struct pm8xxx_irq_platform_data {
int irq_base;
struct pm8xxx_irq_core_data irq_cdata;
int devirq;
int irq_trigger_flag;
};
struct pm_irq_chip;
#ifdef CONFIG_MFD_PM8XXX_IRQ
int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
const struct pm8xxx_irq_platform_data *pdata);
int pm8xxx_irq_exit(struct pm_irq_chip *chip);
#else
static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
{
return -ENXIO;
}
static inline struct pm_irq_chip *pm8xxx_irq_init(
const struct device *dev,
const struct pm8xxx_irq_platform_data *pdata)
{
return ERR_PTR(-ENXIO);
}
static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
{
return -ENXIO;
}
#endif /* CONFIG_MFD_PM8XXX_IRQ */
#endif /* __MFD_PM8XXX_IRQ_H */

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include/linux/mfd/pm8xxx/pm8921.h Normal file
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/*
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8921 driver header file
*
*/
#ifndef __MFD_PM8921_H
#define __MFD_PM8921_H
#include <linux/mfd/pm8xxx/irq.h>
#define PM8921_NR_IRQS 256
struct pm8921_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
};
#endif

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include/linux/mfd/pm8xxx/rtc.h Normal file
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __RTC_PM8XXX_H__
#define __RTC_PM8XXX_H__
#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx"
/**
* struct pm8xxx_rtc_pdata - RTC driver platform data
* @rtc_write_enable: variable stating RTC write capability
*/
struct pm8xxx_rtc_platform_data {
bool rtc_write_enable;
};
#endif /* __RTC_PM8XXX_H__ */

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/*
* Core driver interface to access RICOH_RC5T583 power management chip.
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <ldewangan@nvidia.com>
*
* Based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef __LINUX_MFD_RC5T583_H
#define __LINUX_MFD_RC5T583_H
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/regmap.h>
#define RC5T583_MAX_REGS 0xF8
/* Maximum number of main interrupts */
#define MAX_MAIN_INTERRUPT 5
#define RC5T583_MAX_GPEDGE_REG 2
#define RC5T583_MAX_INTERRUPT_EN_REGS 8
#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
/* Interrupt enable register */
#define RC5T583_INT_EN_SYS1 0x19
#define RC5T583_INT_EN_SYS2 0x1D
#define RC5T583_INT_EN_DCDC 0x41
#define RC5T583_INT_EN_RTC 0xED
#define RC5T583_INT_EN_ADC1 0x90
#define RC5T583_INT_EN_ADC2 0x91
#define RC5T583_INT_EN_ADC3 0x92
/* Interrupt status registers (monitor regs in Ricoh)*/
#define RC5T583_INTC_INTPOL 0xAD
#define RC5T583_INTC_INTEN 0xAE
#define RC5T583_INTC_INTMON 0xAF
#define RC5T583_INT_MON_GRP 0xAF
#define RC5T583_INT_MON_SYS1 0x1B
#define RC5T583_INT_MON_SYS2 0x1F
#define RC5T583_INT_MON_DCDC 0x43
#define RC5T583_INT_MON_RTC 0xEE
/* Interrupt clearing registers */
#define RC5T583_INT_IR_SYS1 0x1A
#define RC5T583_INT_IR_SYS2 0x1E
#define RC5T583_INT_IR_DCDC 0x42
#define RC5T583_INT_IR_RTC 0xEE
#define RC5T583_INT_IR_ADCL 0x94
#define RC5T583_INT_IR_ADCH 0x95
#define RC5T583_INT_IR_ADCEND 0x96
#define RC5T583_INT_IR_GPIOR 0xA9
#define RC5T583_INT_IR_GPIOF 0xAA
/* Sleep sequence registers */
#define RC5T583_SLPSEQ1 0x21
#define RC5T583_SLPSEQ2 0x22
#define RC5T583_SLPSEQ3 0x23
#define RC5T583_SLPSEQ4 0x24
#define RC5T583_SLPSEQ5 0x25
#define RC5T583_SLPSEQ6 0x26
#define RC5T583_SLPSEQ7 0x27
#define RC5T583_SLPSEQ8 0x28
#define RC5T583_SLPSEQ9 0x29
#define RC5T583_SLPSEQ10 0x2A
#define RC5T583_SLPSEQ11 0x2B
/* Regulator registers */
#define RC5T583_REG_DC0CTL 0x30
#define RC5T583_REG_DC0DAC 0x31
#define RC5T583_REG_DC0LATCTL 0x32
#define RC5T583_REG_SR0CTL 0x33
#define RC5T583_REG_DC1CTL 0x34
#define RC5T583_REG_DC1DAC 0x35
#define RC5T583_REG_DC1LATCTL 0x36
#define RC5T583_REG_SR1CTL 0x37
#define RC5T583_REG_DC2CTL 0x38
#define RC5T583_REG_DC2DAC 0x39
#define RC5T583_REG_DC2LATCTL 0x3A
#define RC5T583_REG_SR2CTL 0x3B
#define RC5T583_REG_DC3CTL 0x3C
#define RC5T583_REG_DC3DAC 0x3D
#define RC5T583_REG_DC3LATCTL 0x3E
#define RC5T583_REG_SR3CTL 0x3F
#define RC5T583_REG_LDOEN1 0x50
#define RC5T583_REG_LDOEN2 0x51
#define RC5T583_REG_LDODIS1 0x52
#define RC5T583_REG_LDODIS2 0x53
#define RC5T583_REG_LDO0DAC 0x54
#define RC5T583_REG_LDO1DAC 0x55
#define RC5T583_REG_LDO2DAC 0x56
#define RC5T583_REG_LDO3DAC 0x57
#define RC5T583_REG_LDO4DAC 0x58
#define RC5T583_REG_LDO5DAC 0x59
#define RC5T583_REG_LDO6DAC 0x5A
#define RC5T583_REG_LDO7DAC 0x5B
#define RC5T583_REG_LDO8DAC 0x5C
#define RC5T583_REG_LDO9DAC 0x5D
#define RC5T583_REG_DC0DAC_DS 0x60
#define RC5T583_REG_DC1DAC_DS 0x61
#define RC5T583_REG_DC2DAC_DS 0x62
#define RC5T583_REG_DC3DAC_DS 0x63
#define RC5T583_REG_LDO0DAC_DS 0x64
#define RC5T583_REG_LDO1DAC_DS 0x65
#define RC5T583_REG_LDO2DAC_DS 0x66
#define RC5T583_REG_LDO3DAC_DS 0x67
#define RC5T583_REG_LDO4DAC_DS 0x68
#define RC5T583_REG_LDO5DAC_DS 0x69
#define RC5T583_REG_LDO6DAC_DS 0x6A
#define RC5T583_REG_LDO7DAC_DS 0x6B
#define RC5T583_REG_LDO8DAC_DS 0x6C
#define RC5T583_REG_LDO9DAC_DS 0x6D
/* GPIO register base address */
#define RC5T583_GPIO_IOSEL 0xA0
#define RC5T583_GPIO_PDEN 0xA1
#define RC5T583_GPIO_IOOUT 0xA2
#define RC5T583_GPIO_PGSEL 0xA3
#define RC5T583_GPIO_GPINV 0xA4
#define RC5T583_GPIO_GPDEB 0xA5
#define RC5T583_GPIO_GPEDGE1 0xA6
#define RC5T583_GPIO_GPEDGE2 0xA7
#define RC5T583_GPIO_EN_INT 0xA8
#define RC5T583_GPIO_MON_IOIN 0xAB
#define RC5T583_GPIO_GPOFUNC 0xAC
/* RTC registers */
#define RC5T583_RTC_SEC 0xE0
#define RC5T583_RTC_MIN 0xE1
#define RC5T583_RTC_HOUR 0xE2
#define RC5T583_RTC_WDAY 0xE3
#define RC5T583_RTC_DAY 0xE4
#define RC5T583_RTC_MONTH 0xE5
#define RC5T583_RTC_YEAR 0xE6
#define RC5T583_RTC_ADJ 0xE7
#define RC5T583_RTC_AW_MIN 0xE8
#define RC5T583_RTC_AW_HOUR 0xE9
#define RC5T583_RTC_AW_WEEK 0xEA
#define RC5T583_RTC_AD_MIN 0xEB
#define RC5T583_RTC_AD_HOUR 0xEC
#define RC5T583_RTC_CTL1 0xED
#define RC5T583_RTC_CTL2 0xEE
#define RC5T583_RTC_AY_MIN 0xF0
#define RC5T583_RTC_AY_HOUR 0xF1
#define RC5T583_RTC_AY_DAY 0xF2
#define RC5T583_RTC_AY_MONTH 0xF3
#define RC5T583_RTC_AY_YEAR 0xF4
/* RICOH_RC5T583 IRQ definitions */
enum {
RC5T583_IRQ_ONKEY,
RC5T583_IRQ_ACOK,
RC5T583_IRQ_LIDOPEN,
RC5T583_IRQ_PREOT,
RC5T583_IRQ_CLKSTP,
RC5T583_IRQ_ONKEY_OFF,
RC5T583_IRQ_WD,
RC5T583_IRQ_EN_PWRREQ1,
RC5T583_IRQ_EN_PWRREQ2,
RC5T583_IRQ_PRE_VINDET,
RC5T583_IRQ_DC0LIM,
RC5T583_IRQ_DC1LIM,
RC5T583_IRQ_DC2LIM,
RC5T583_IRQ_DC3LIM,
RC5T583_IRQ_CTC,
RC5T583_IRQ_YALE,
RC5T583_IRQ_DALE,
RC5T583_IRQ_WALE,
RC5T583_IRQ_AIN1L,
RC5T583_IRQ_AIN2L,
RC5T583_IRQ_AIN3L,
RC5T583_IRQ_VBATL,
RC5T583_IRQ_VIN3L,
RC5T583_IRQ_VIN8L,
RC5T583_IRQ_AIN1H,
RC5T583_IRQ_AIN2H,
RC5T583_IRQ_AIN3H,
RC5T583_IRQ_VBATH,
RC5T583_IRQ_VIN3H,
RC5T583_IRQ_VIN8H,
RC5T583_IRQ_ADCEND,
RC5T583_IRQ_GPIO0,
RC5T583_IRQ_GPIO1,
RC5T583_IRQ_GPIO2,
RC5T583_IRQ_GPIO3,
RC5T583_IRQ_GPIO4,
RC5T583_IRQ_GPIO5,
RC5T583_IRQ_GPIO6,
RC5T583_IRQ_GPIO7,
/* Should be last entry */
RC5T583_MAX_IRQS,
};
/* Ricoh583 gpio definitions */
enum {
RC5T583_GPIO0,
RC5T583_GPIO1,
RC5T583_GPIO2,
RC5T583_GPIO3,
RC5T583_GPIO4,
RC5T583_GPIO5,
RC5T583_GPIO6,
RC5T583_GPIO7,
/* Should be last entry */
RC5T583_MAX_GPIO,
};
enum {
RC5T583_DS_NONE,
RC5T583_DS_DC0,
RC5T583_DS_DC1,
RC5T583_DS_DC2,
RC5T583_DS_DC3,
RC5T583_DS_LDO0,
RC5T583_DS_LDO1,
RC5T583_DS_LDO2,
RC5T583_DS_LDO3,
RC5T583_DS_LDO4,
RC5T583_DS_LDO5,
RC5T583_DS_LDO6,
RC5T583_DS_LDO7,
RC5T583_DS_LDO8,
RC5T583_DS_LDO9,
RC5T583_DS_PSO0,
RC5T583_DS_PSO1,
RC5T583_DS_PSO2,
RC5T583_DS_PSO3,
RC5T583_DS_PSO4,
RC5T583_DS_PSO5,
RC5T583_DS_PSO6,
RC5T583_DS_PSO7,
/* Should be last entry */
RC5T583_DS_MAX,
};
/*
* Ricoh pmic RC5T583 supports sleep through two external controls.
* The output of gpios and regulator can be enable/disable through
* this external signals.
*/
enum {
RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
};
enum {
RC5T583_REGULATOR_DC0,
RC5T583_REGULATOR_DC1,
RC5T583_REGULATOR_DC2,
RC5T583_REGULATOR_DC3,
RC5T583_REGULATOR_LDO0,
RC5T583_REGULATOR_LDO1,
RC5T583_REGULATOR_LDO2,
RC5T583_REGULATOR_LDO3,
RC5T583_REGULATOR_LDO4,
RC5T583_REGULATOR_LDO5,
RC5T583_REGULATOR_LDO6,
RC5T583_REGULATOR_LDO7,
RC5T583_REGULATOR_LDO8,
RC5T583_REGULATOR_LDO9,
/* Should be last entry */
RC5T583_REGULATOR_MAX,
};
struct rc5t583 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
int irq_base;
struct mutex irq_lock;
unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
/* For main interrupt bits in INTC */
uint8_t intc_inten_reg;
/* For group interrupt bits and address */
uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
/* For gpio edge */
uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
};
/*
* rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
* The board specific data is provided through this structure.
* @irq_base: Irq base number on which this device registers their interrupts.
* @gpio_base: GPIO base from which gpio of this device will start.
* @enable_shutdown: Enable shutdown through the input pin "shutdown".
* @regulator_deepsleep_slot: The slot number on which device goes to sleep
* in device sleep mode.
* @regulator_ext_pwr_control: External power request regulator control. The
* regulator output enable/disable is controlled by the external
* power request input state.
* @reg_init_data: Regulator init data.
*/
struct rc5t583_platform_data {
int irq_base;
int gpio_base;
bool enable_shutdown;
int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
};
static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_write(rc5t583->regmap, reg, val);
}
static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
unsigned int ival;
int ret;
ret = regmap_read(rc5t583->regmap, reg, &ival);
if (!ret)
*val = (uint8_t)ival;
return ret;
}
static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
}
static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
}
static inline int rc5t583_update(struct device *dev, unsigned int reg,
unsigned int val, unsigned int mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, mask, val);
}
int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
int ext_pwr_req, int deepsleep_slot_nr);
int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
int rc5t583_irq_exit(struct rc5t583 *rc5t583);
#endif

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#ifndef __RDC321X_MFD_H
#define __RDC321X_MFD_H
#include <linux/types.h>
#include <linux/pci.h>
/* Offsets to be accessed in the southbridge PCI
* device configuration register */
#define RDC321X_WDT_CTRL 0x44
#define RDC321X_GPIO_CTRL_REG1 0x48
#define RDC321X_GPIO_DATA_REG1 0x4c
#define RDC321X_GPIO_CTRL_REG2 0x84
#define RDC321X_GPIO_DATA_REG2 0x88
#define RDC321X_MAX_GPIO 58
struct rdc321x_gpio_pdata {
struct pci_dev *sb_pdev;
unsigned max_gpios;
};
struct rdc321x_wdt_pdata {
struct pci_dev *sb_pdev;
};
#endif /* __RDC321X_MFD_H */

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/*
* Retu/Tahvo MFD driver interface
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*/
#ifndef __LINUX_MFD_RETU_H
#define __LINUX_MFD_RETU_H
struct retu_dev;
int retu_read(struct retu_dev *, u8);
int retu_write(struct retu_dev *, u8, u16);
/* Registers */
#define RETU_REG_WATCHDOG 0x17 /* Watchdog */
#define RETU_REG_CC1 0x0d /* Common control register 1 */
#define RETU_REG_STATUS 0x16 /* Status register */
/* Interrupt sources */
#define TAHVO_INT_VBUS 0 /* VBUS state */
/* Interrupt status */
#define TAHVO_STAT_VBUS (1 << TAHVO_INT_VBUS)
#endif /* __LINUX_MFD_RETU_H */

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/* Driver for Realtek driver-based card reader
*
* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* Author:
* Wei WANG <wei_wang@realsil.com.cn>
*/
#ifndef __RTSX_COMMON_H
#define __RTSX_COMMON_H
#define DRV_NAME_RTSX_PCI "rtsx_pci"
#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc"
#define DRV_NAME_RTSX_PCI_MS "rtsx_pci_ms"
#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val))
#define RTSX_SSC_DEPTH_4M 0x01
#define RTSX_SSC_DEPTH_2M 0x02
#define RTSX_SSC_DEPTH_1M 0x03
#define RTSX_SSC_DEPTH_500K 0x04
#define RTSX_SSC_DEPTH_250K 0x05
#define RTSX_SD_CARD 0
#define RTSX_MS_CARD 1
#define CLK_TO_DIV_N 0
#define DIV_N_TO_CLK 1
struct platform_device;
struct rtsx_slot {
struct platform_device *p_dev;
void (*card_event)(struct platform_device *p_dev);
};
#endif

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include/linux/mfd/rtsx_pci.h Normal file
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/* Driver for Realtek PCI-Express card reader
*
* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* Author:
* Wei WANG <wei_wang@realsil.com.cn>
*/
#ifndef __RTSX_PCI_H
#define __RTSX_PCI_H
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/mfd/rtsx_common.h>
#define MAX_RW_REG_CNT 1024
/* PCI Operation Register Address */
#define RTSX_HCBAR 0x00
#define RTSX_HCBCTLR 0x04
#define RTSX_HDBAR 0x08
#define RTSX_HDBCTLR 0x0C
#define RTSX_HAIMR 0x10
#define RTSX_BIPR 0x14
#define RTSX_BIER 0x18
/* Host command buffer control register */
#define STOP_CMD (0x01 << 28)
/* Host data buffer control register */
#define SDMA_MODE 0x00
#define ADMA_MODE (0x02 << 26)
#define STOP_DMA (0x01 << 28)
#define TRIG_DMA (0x01 << 31)
/* Host access internal memory register */
#define HAIMR_TRANS_START (0x01 << 31)
#define HAIMR_READ 0x00
#define HAIMR_WRITE (0x01 << 30)
#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
#define HAIMR_TRANS_END (HAIMR_TRANS_START)
/* Bus interrupt pending register */
#define CMD_DONE_INT (1 << 31)
#define DATA_DONE_INT (1 << 30)
#define TRANS_OK_INT (1 << 29)
#define TRANS_FAIL_INT (1 << 28)
#define XD_INT (1 << 27)
#define MS_INT (1 << 26)
#define SD_INT (1 << 25)
#define GPIO0_INT (1 << 24)
#define OC_INT (1 << 23)
#define SD_WRITE_PROTECT (1 << 19)
#define XD_EXIST (1 << 18)
#define MS_EXIST (1 << 17)
#define SD_EXIST (1 << 16)
#define DELINK_INT GPIO0_INT
#define MS_OC_INT (1 << 23)
#define SD_OC_INT (1 << 22)
#define CARD_INT (XD_INT | MS_INT | SD_INT)
#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
CARD_INT | GPIO0_INT | OC_INT)
#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
/* Bus interrupt enable register */
#define CMD_DONE_INT_EN (1 << 31)
#define DATA_DONE_INT_EN (1 << 30)
#define TRANS_OK_INT_EN (1 << 29)
#define TRANS_FAIL_INT_EN (1 << 28)
#define XD_INT_EN (1 << 27)
#define MS_INT_EN (1 << 26)
#define SD_INT_EN (1 << 25)
#define GPIO0_INT_EN (1 << 24)
#define OC_INT_EN (1 << 23)
#define DELINK_INT_EN GPIO0_INT_EN
#define MS_OC_INT_EN (1 << 23)
#define SD_OC_INT_EN (1 << 22)
#define READ_REG_CMD 0
#define WRITE_REG_CMD 1
#define CHECK_REG_CMD 2
/*
* macros for easy use
*/
#define rtsx_pci_writel(pcr, reg, value) \
iowrite32(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readl(pcr, reg) \
ioread32((pcr)->remap_addr + reg)
#define rtsx_pci_writew(pcr, reg, value) \
iowrite16(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readw(pcr, reg) \
ioread16((pcr)->remap_addr + reg)
#define rtsx_pci_writeb(pcr, reg, value) \
iowrite8(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readb(pcr, reg) \
ioread8((pcr)->remap_addr + reg)
#define rtsx_pci_read_config_byte(pcr, where, val) \
pci_read_config_byte((pcr)->pci, where, val)
#define rtsx_pci_write_config_byte(pcr, where, val) \
pci_write_config_byte((pcr)->pci, where, val)
#define rtsx_pci_read_config_dword(pcr, where, val) \
pci_read_config_dword((pcr)->pci, where, val)
#define rtsx_pci_write_config_dword(pcr, where, val) \
pci_write_config_dword((pcr)->pci, where, val)
#define STATE_TRANS_NONE 0
#define STATE_TRANS_CMD 1
#define STATE_TRANS_BUF 2
#define STATE_TRANS_SG 3
#define TRANS_NOT_READY 0
#define TRANS_RESULT_OK 1
#define TRANS_RESULT_FAIL 2
#define TRANS_NO_DEVICE 3
#define RTSX_RESV_BUF_LEN 4096
#define HOST_CMDS_BUF_LEN 1024
#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
#define MAX_SG_ITEM_LEN 0x80000
#define HOST_TO_DEVICE 0
#define DEVICE_TO_HOST 1
#define MAX_PHASE 31
#define RX_TUNING_CNT 3
/* SG descriptor */
#define SG_INT 0x04
#define SG_END 0x02
#define SG_VALID 0x01
#define SG_NO_OP 0x00
#define SG_TRANS_DATA (0x02 << 4)
#define SG_LINK_DESC (0x03 << 4)
/* Output voltage */
#define OUTPUT_3V3 0
#define OUTPUT_1V8 1
/* Card Clock Enable Register */
#define SD_CLK_EN 0x04
#define MS_CLK_EN 0x08
/* Card Select Register */
#define SD_MOD_SEL 2
#define MS_MOD_SEL 3
/* Card Output Enable Register */
#define SD_OUTPUT_EN 0x04
#define MS_OUTPUT_EN 0x08
/* CARD_SHARE_MODE */
#define CARD_SHARE_MASK 0x0F
#define CARD_SHARE_MULTI_LUN 0x00
#define CARD_SHARE_NORMAL 0x00
#define CARD_SHARE_48_SD 0x04
#define CARD_SHARE_48_MS 0x08
/* CARD_SHARE_MODE for barossa */
#define CARD_SHARE_BAROSSA_SD 0x01
#define CARD_SHARE_BAROSSA_MS 0x02
/* SD30_DRIVE_SEL */
#define DRIVER_TYPE_A 0x05
#define DRIVER_TYPE_B 0x03
#define DRIVER_TYPE_C 0x02
#define DRIVER_TYPE_D 0x01
/* FPDCTL */
#define SSC_POWER_DOWN 0x01
#define SD_OC_POWER_DOWN 0x02
#define ALL_POWER_DOWN 0x07
#define OC_POWER_DOWN 0x06
/* CLK_CTL */
#define CHANGE_CLK 0x01
/* LDO_CTL */
#define BPP_ASIC_1V7 0x00
#define BPP_ASIC_1V8 0x01
#define BPP_ASIC_1V9 0x02
#define BPP_ASIC_2V0 0x03
#define BPP_ASIC_2V7 0x04
#define BPP_ASIC_2V8 0x05
#define BPP_ASIC_3V2 0x06
#define BPP_ASIC_3V3 0x07
#define BPP_REG_TUNED18 0x07
#define BPP_TUNED18_SHIFT_8402 5
#define BPP_TUNED18_SHIFT_8411 4
#define BPP_PAD_MASK 0x04
#define BPP_PAD_3V3 0x04
#define BPP_PAD_1V8 0x00
#define BPP_LDO_POWB 0x03
#define BPP_LDO_ON 0x00
#define BPP_LDO_SUSPEND 0x02
#define BPP_LDO_OFF 0x03
/* CD_PAD_CTL */
#define CD_DISABLE_MASK 0x07
#define MS_CD_DISABLE 0x04
#define SD_CD_DISABLE 0x02
#define XD_CD_DISABLE 0x01
#define CD_DISABLE 0x07
#define CD_ENABLE 0x00
#define MS_CD_EN_ONLY 0x03
#define SD_CD_EN_ONLY 0x05
#define XD_CD_EN_ONLY 0x06
#define FORCE_CD_LOW_MASK 0x38
#define FORCE_CD_XD_LOW 0x08
#define FORCE_CD_SD_LOW 0x10
#define FORCE_CD_MS_LOW 0x20
#define CD_AUTO_DISABLE 0x40
/* SD_STAT1 */
#define SD_CRC7_ERR 0x80
#define SD_CRC16_ERR 0x40
#define SD_CRC_WRITE_ERR 0x20
#define SD_CRC_WRITE_ERR_MASK 0x1C
#define GET_CRC_TIME_OUT 0x02
#define SD_TUNING_COMPARE_ERR 0x01
/* SD_STAT2 */
#define SD_RSP_80CLK_TIMEOUT 0x01
/* SD_BUS_STAT */
#define SD_CLK_TOGGLE_EN 0x80
#define SD_CLK_FORCE_STOP 0x40
#define SD_DAT3_STATUS 0x10
#define SD_DAT2_STATUS 0x08
#define SD_DAT1_STATUS 0x04
#define SD_DAT0_STATUS 0x02
#define SD_CMD_STATUS 0x01
/* SD_PAD_CTL */
#define SD_IO_USING_1V8 0x80
#define SD_IO_USING_3V3 0x7F
#define TYPE_A_DRIVING 0x00
#define TYPE_B_DRIVING 0x01
#define TYPE_C_DRIVING 0x02
#define TYPE_D_DRIVING 0x03
/* SD_SAMPLE_POINT_CTL */
#define DDR_FIX_RX_DAT 0x00
#define DDR_VAR_RX_DAT 0x80
#define DDR_FIX_RX_DAT_EDGE 0x00
#define DDR_FIX_RX_DAT_14_DELAY 0x40
#define DDR_FIX_RX_CMD 0x00
#define DDR_VAR_RX_CMD 0x20
#define DDR_FIX_RX_CMD_POS_EDGE 0x00
#define DDR_FIX_RX_CMD_14_DELAY 0x10
#define SD20_RX_POS_EDGE 0x00
#define SD20_RX_14_DELAY 0x08
#define SD20_RX_SEL_MASK 0x08
/* SD_PUSH_POINT_CTL */
#define DDR_FIX_TX_CMD_DAT 0x00
#define DDR_VAR_TX_CMD_DAT 0x80
#define DDR_FIX_TX_DAT_14_TSU 0x00
#define DDR_FIX_TX_DAT_12_TSU 0x40
#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
#define DDR_FIX_TX_CMD_14_AHEAD 0x20
#define SD20_TX_NEG_EDGE 0x00
#define SD20_TX_14_AHEAD 0x10
#define SD20_TX_SEL_MASK 0x10
#define DDR_VAR_SDCLK_POL_SWAP 0x01
/* SD_TRANSFER */
#define SD_TRANSFER_START 0x80
#define SD_TRANSFER_END 0x40
#define SD_STAT_IDLE 0x20
#define SD_TRANSFER_ERR 0x10
/* SD Transfer Mode definition */
#define SD_TM_NORMAL_WRITE 0x00
#define SD_TM_AUTO_WRITE_3 0x01
#define SD_TM_AUTO_WRITE_4 0x02
#define SD_TM_AUTO_READ_3 0x05
#define SD_TM_AUTO_READ_4 0x06
#define SD_TM_CMD_RSP 0x08
#define SD_TM_AUTO_WRITE_1 0x09
#define SD_TM_AUTO_WRITE_2 0x0A
#define SD_TM_NORMAL_READ 0x0C
#define SD_TM_AUTO_READ_1 0x0D
#define SD_TM_AUTO_READ_2 0x0E
#define SD_TM_AUTO_TUNING 0x0F
/* SD_VPTX_CTL / SD_VPRX_CTL */
#define PHASE_CHANGE 0x80
#define PHASE_NOT_RESET 0x40
/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
#define DCMPS_CHANGE 0x80
#define DCMPS_CHANGE_DONE 0x40
#define DCMPS_ERROR 0x20
#define DCMPS_CURRENT_PHASE 0x1F
/* SD Configure 1 Register */
#define SD_CLK_DIVIDE_0 0x00
#define SD_CLK_DIVIDE_256 0xC0
#define SD_CLK_DIVIDE_128 0x80
#define SD_BUS_WIDTH_1BIT 0x00
#define SD_BUS_WIDTH_4BIT 0x01
#define SD_BUS_WIDTH_8BIT 0x02
#define SD_ASYNC_FIFO_NOT_RST 0x10
#define SD_20_MODE 0x00
#define SD_DDR_MODE 0x04
#define SD_30_MODE 0x08
#define SD_CLK_DIVIDE_MASK 0xC0
/* SD_CMD_STATE */
#define SD_CMD_IDLE 0x80
/* SD_DATA_STATE */
#define SD_DATA_IDLE 0x80
/* DCM_DRP_CTL */
#define DCM_RESET 0x08
#define DCM_LOCKED 0x04
#define DCM_208M 0x00
#define DCM_TX 0x01
#define DCM_RX 0x02
/* DCM_DRP_TRIG */
#define DRP_START 0x80
#define DRP_DONE 0x40
/* DCM_DRP_CFG */
#define DRP_WRITE 0x80
#define DRP_READ 0x00
#define DCM_WRITE_ADDRESS_50 0x50
#define DCM_WRITE_ADDRESS_51 0x51
#define DCM_READ_ADDRESS_00 0x00
#define DCM_READ_ADDRESS_51 0x51
/* IRQSTAT0 */
#define DMA_DONE_INT 0x80
#define SUSPEND_INT 0x40
#define LINK_RDY_INT 0x20
#define LINK_DOWN_INT 0x10
/* DMACTL */
#define DMA_RST 0x80
#define DMA_BUSY 0x04
#define DMA_DIR_TO_CARD 0x00
#define DMA_DIR_FROM_CARD 0x02
#define DMA_EN 0x01
#define DMA_128 (0 << 4)
#define DMA_256 (1 << 4)
#define DMA_512 (2 << 4)
#define DMA_1024 (3 << 4)
#define DMA_PACK_SIZE_MASK 0x30
/* SSC_CTL1 */
#define SSC_RSTB 0x80
#define SSC_8X_EN 0x40
#define SSC_FIX_FRAC 0x20
#define SSC_SEL_1M 0x00
#define SSC_SEL_2M 0x08
#define SSC_SEL_4M 0x10
#define SSC_SEL_8M 0x18
/* SSC_CTL2 */
#define SSC_DEPTH_MASK 0x07
#define SSC_DEPTH_DISALBE 0x00
#define SSC_DEPTH_4M 0x01
#define SSC_DEPTH_2M 0x02
#define SSC_DEPTH_1M 0x03
#define SSC_DEPTH_500K 0x04
#define SSC_DEPTH_250K 0x05
/* System Clock Control Register */
#define CLK_LOW_FREQ 0x01
/* System Clock Divider Register */
#define CLK_DIV_1 0x01
#define CLK_DIV_2 0x02
#define CLK_DIV_4 0x03
#define CLK_DIV_8 0x04
/* MS_CFG */
#define SAMPLE_TIME_RISING 0x00
#define SAMPLE_TIME_FALLING 0x80
#define PUSH_TIME_DEFAULT 0x00
#define PUSH_TIME_ODD 0x40
#define NO_EXTEND_TOGGLE 0x00
#define EXTEND_TOGGLE_CHK 0x20
#define MS_BUS_WIDTH_1 0x00
#define MS_BUS_WIDTH_4 0x10
#define MS_BUS_WIDTH_8 0x18
#define MS_2K_SECTOR_MODE 0x04
#define MS_512_SECTOR_MODE 0x00
#define MS_TOGGLE_TIMEOUT_EN 0x00
#define MS_TOGGLE_TIMEOUT_DISEN 0x01
#define MS_NO_CHECK_INT 0x02
/* MS_TRANS_CFG */
#define WAIT_INT 0x80
#define NO_WAIT_INT 0x00
#define NO_AUTO_READ_INT_REG 0x00
#define AUTO_READ_INT_REG 0x40
#define MS_CRC16_ERR 0x20
#define MS_RDY_TIMEOUT 0x10
#define MS_INT_CMDNK 0x08
#define MS_INT_BREQ 0x04
#define MS_INT_ERR 0x02
#define MS_INT_CED 0x01
/* MS_TRANSFER */
#define MS_TRANSFER_START 0x80
#define MS_TRANSFER_END 0x40
#define MS_TRANSFER_ERR 0x20
#define MS_BS_STATE 0x10
#define MS_TM_READ_BYTES 0x00
#define MS_TM_NORMAL_READ 0x01
#define MS_TM_WRITE_BYTES 0x04
#define MS_TM_NORMAL_WRITE 0x05
#define MS_TM_AUTO_READ 0x08
#define MS_TM_AUTO_WRITE 0x0C
/* SD Configure 2 Register */
#define SD_CALCULATE_CRC7 0x00
#define SD_NO_CALCULATE_CRC7 0x80
#define SD_CHECK_CRC16 0x00
#define SD_NO_CHECK_CRC16 0x40
#define SD_NO_CHECK_WAIT_CRC_TO 0x20
#define SD_WAIT_BUSY_END 0x08
#define SD_NO_WAIT_BUSY_END 0x00
#define SD_CHECK_CRC7 0x00
#define SD_NO_CHECK_CRC7 0x04
#define SD_RSP_LEN_0 0x00
#define SD_RSP_LEN_6 0x01
#define SD_RSP_LEN_17 0x02
/* SD/MMC Response Type Definition */
#define SD_RSP_TYPE_R0 0x04
#define SD_RSP_TYPE_R1 0x01
#define SD_RSP_TYPE_R1b 0x09
#define SD_RSP_TYPE_R2 0x02
#define SD_RSP_TYPE_R3 0x05
#define SD_RSP_TYPE_R4 0x05
#define SD_RSP_TYPE_R5 0x01
#define SD_RSP_TYPE_R6 0x01
#define SD_RSP_TYPE_R7 0x01
/* SD_CONFIGURE3 */
#define SD_RSP_80CLK_TIMEOUT_EN 0x01
/* Card Transfer Reset Register */
#define SPI_STOP 0x01
#define XD_STOP 0x02
#define SD_STOP 0x04
#define MS_STOP 0x08
#define SPI_CLR_ERR 0x10
#define XD_CLR_ERR 0x20
#define SD_CLR_ERR 0x40
#define MS_CLR_ERR 0x80
/* Card Data Source Register */
#define PINGPONG_BUFFER 0x01
#define RING_BUFFER 0x00
/* Card Power Control Register */
#define PMOS_STRG_MASK 0x10
#define PMOS_STRG_800mA 0x10
#define PMOS_STRG_400mA 0x00
#define SD_POWER_OFF 0x03
#define SD_PARTIAL_POWER_ON 0x01
#define SD_POWER_ON 0x00
#define SD_POWER_MASK 0x03
#define MS_POWER_OFF 0x0C
#define MS_PARTIAL_POWER_ON 0x04
#define MS_POWER_ON 0x00
#define MS_POWER_MASK 0x0C
#define BPP_POWER_OFF 0x0F
#define BPP_POWER_5_PERCENT_ON 0x0E
#define BPP_POWER_10_PERCENT_ON 0x0C
#define BPP_POWER_15_PERCENT_ON 0x08
#define BPP_POWER_ON 0x00
#define BPP_POWER_MASK 0x0F
#define SD_VCC_PARTIAL_POWER_ON 0x02
#define SD_VCC_POWER_ON 0x00
/* PWR_GATE_CTRL */
#define PWR_GATE_EN 0x01
#define LDO3318_PWR_MASK 0x06
#define LDO_ON 0x00
#define LDO_SUSPEND 0x04
#define LDO_OFF 0x06
/* CARD_CLK_SOURCE */
#define CRC_FIX_CLK (0x00 << 0)
#define CRC_VAR_CLK0 (0x01 << 0)
#define CRC_VAR_CLK1 (0x02 << 0)
#define SD30_FIX_CLK (0x00 << 2)
#define SD30_VAR_CLK0 (0x01 << 2)
#define SD30_VAR_CLK1 (0x02 << 2)
#define SAMPLE_FIX_CLK (0x00 << 4)
#define SAMPLE_VAR_CLK0 (0x01 << 4)
#define SAMPLE_VAR_CLK1 (0x02 << 4)
/* HOST_SLEEP_STATE */
#define HOST_ENTER_S1 1
#define HOST_ENTER_S3 2
#define MS_CFG 0xFD40
#define MS_TPC 0xFD41
#define MS_TRANS_CFG 0xFD42
#define MS_TRANSFER 0xFD43
#define MS_INT_REG 0xFD44
#define MS_BYTE_CNT 0xFD45
#define MS_SECTOR_CNT_L 0xFD46
#define MS_SECTOR_CNT_H 0xFD47
#define MS_DBUS_H 0xFD48
#define SD_CFG1 0xFDA0
#define SD_CFG2 0xFDA1
#define SD_CFG3 0xFDA2
#define SD_STAT1 0xFDA3
#define SD_STAT2 0xFDA4
#define SD_BUS_STAT 0xFDA5
#define SD_PAD_CTL 0xFDA6
#define SD_SAMPLE_POINT_CTL 0xFDA7
#define SD_PUSH_POINT_CTL 0xFDA8
#define SD_CMD0 0xFDA9
#define SD_CMD1 0xFDAA
#define SD_CMD2 0xFDAB
#define SD_CMD3 0xFDAC
#define SD_CMD4 0xFDAD
#define SD_CMD5 0xFDAE
#define SD_BYTE_CNT_L 0xFDAF
#define SD_BYTE_CNT_H 0xFDB0
#define SD_BLOCK_CNT_L 0xFDB1
#define SD_BLOCK_CNT_H 0xFDB2
#define SD_TRANSFER 0xFDB3
#define SD_CMD_STATE 0xFDB5
#define SD_DATA_STATE 0xFDB6
#define SRCTL 0xFC13
#define DCM_DRP_CTL 0xFC23
#define DCM_DRP_TRIG 0xFC24
#define DCM_DRP_CFG 0xFC25
#define DCM_DRP_WR_DATA_L 0xFC26
#define DCM_DRP_WR_DATA_H 0xFC27
#define DCM_DRP_RD_DATA_L 0xFC28
#define DCM_DRP_RD_DATA_H 0xFC29
#define SD_VPCLK0_CTL 0xFC2A
#define SD_VPCLK1_CTL 0xFC2B
#define SD_DCMPS0_CTL 0xFC2C
#define SD_DCMPS1_CTL 0xFC2D
#define SD_VPTX_CTL SD_VPCLK0_CTL
#define SD_VPRX_CTL SD_VPCLK1_CTL
#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
#define CARD_CLK_SOURCE 0xFC2E
#define CARD_PWR_CTL 0xFD50
#define CARD_CLK_SWITCH 0xFD51
#define RTL8411B_PACKAGE_MODE 0xFD51
#define CARD_SHARE_MODE 0xFD52
#define CARD_DRIVE_SEL 0xFD53
#define CARD_STOP 0xFD54
#define CARD_OE 0xFD55
#define CARD_AUTO_BLINK 0xFD56
#define CARD_GPIO_DIR 0xFD57
#define CARD_GPIO 0xFD58
#define CARD_DATA_SOURCE 0xFD5B
#define SD30_CLK_DRIVE_SEL 0xFD5A
#define CARD_SELECT 0xFD5C
#define SD30_DRIVE_SEL 0xFD5E
#define SD30_CMD_DRIVE_SEL 0xFD5E
#define SD30_DAT_DRIVE_SEL 0xFD5F
#define CARD_CLK_EN 0xFD69
#define SDIO_CTRL 0xFD6B
#define CD_PAD_CTL 0xFD73
#define FPDCTL 0xFC00
#define PDINFO 0xFC01
#define CLK_CTL 0xFC02
#define CLK_DIV 0xFC03
#define CLK_SEL 0xFC04
#define SSC_DIV_N_0 0xFC0F
#define SSC_DIV_N_1 0xFC10
#define SSC_CTL1 0xFC11
#define SSC_CTL2 0xFC12
#define RCCTL 0xFC14
#define FPGA_PULL_CTL 0xFC1D
#define OLT_LED_CTL 0xFC1E
#define GPIO_CTL 0xFC1F
#define LDO_CTL 0xFC1E
#define SYS_VER 0xFC32
#define CARD_PULL_CTL1 0xFD60
#define CARD_PULL_CTL2 0xFD61
#define CARD_PULL_CTL3 0xFD62
#define CARD_PULL_CTL4 0xFD63
#define CARD_PULL_CTL5 0xFD64
#define CARD_PULL_CTL6 0xFD65
/* PCI Express Related Registers */
#define IRQEN0 0xFE20
#define IRQSTAT0 0xFE21
#define IRQEN1 0xFE22
#define IRQSTAT1 0xFE23
#define TLPRIEN 0xFE24
#define TLPRISTAT 0xFE25
#define TLPTIEN 0xFE26
#define TLPTISTAT 0xFE27
#define DMATC0 0xFE28
#define DMATC1 0xFE29
#define DMATC2 0xFE2A
#define DMATC3 0xFE2B
#define DMACTL 0xFE2C
#define BCTL 0xFE2D
#define RBBC0 0xFE2E
#define RBBC1 0xFE2F
#define RBDAT 0xFE30
#define RBCTL 0xFE34
#define CFGADDR0 0xFE35
#define CFGADDR1 0xFE36
#define CFGDATA0 0xFE37
#define CFGDATA1 0xFE38
#define CFGDATA2 0xFE39
#define CFGDATA3 0xFE3A
#define CFGRWCTL 0xFE3B
#define PHYRWCTL 0xFE3C
#define PHYDATA0 0xFE3D
#define PHYDATA1 0xFE3E
#define PHYADDR 0xFE3F
#define MSGRXDATA0 0xFE40
#define MSGRXDATA1 0xFE41
#define MSGRXDATA2 0xFE42
#define MSGRXDATA3 0xFE43
#define MSGTXDATA0 0xFE44
#define MSGTXDATA1 0xFE45
#define MSGTXDATA2 0xFE46
#define MSGTXDATA3 0xFE47
#define MSGTXCTL 0xFE48
#define PETXCFG 0xFE49
#define LTR_CTL 0xFE4A
#define OBFF_CFG 0xFE4C
#define CDRESUMECTL 0xFE52
#define WAKE_SEL_CTL 0xFE54
#define PME_FORCE_CTL 0xFE56
#define ASPM_FORCE_CTL 0xFE57
#define PM_CLK_FORCE_CTL 0xFE58
#define FUNC_FORCE_CTL 0xFE59
#define PERST_GLITCH_WIDTH 0xFE5C
#define CHANGE_LINK_STATE 0xFE5B
#define RESET_LOAD_REG 0xFE5E
#define EFUSE_CONTENT 0xFE5F
#define HOST_SLEEP_STATE 0xFE60
#define SDIO_CFG 0xFE70
#define NFTS_TX_CTRL 0xFE72
#define PWR_GATE_CTRL 0xFE75
#define PWD_SUSPEND_EN 0xFE76
#define LDO_PWR_SEL 0xFE78
#define DUMMY_REG_RESET_0 0xFE90
#define AUTOLOAD_CFG_BASE 0xFF00
#define PM_CTRL1 0xFF44
#define PM_CTRL2 0xFF45
#define PM_CTRL3 0xFF46
#define PM_CTRL4 0xFF47
/* Memory mapping */
#define SRAM_BASE 0xE600
#define RBUF_BASE 0xF400
#define PPBUF_BASE1 0xF800
#define PPBUF_BASE2 0xFA00
#define IMAGE_FLAG_ADDR0 0xCE80
#define IMAGE_FLAG_ADDR1 0xCE81
/* Phy register */
#define PHY_PCR 0x00
#define PHY_RCR0 0x01
#define PHY_RCR1 0x02
#define PHY_RCR2 0x03
#define PHY_RTCR 0x04
#define PHY_RDR 0x05
#define PHY_TCR0 0x06
#define PHY_TCR1 0x07
#define PHY_TUNE 0x08
#define PHY_IMR 0x09
#define PHY_BPCR 0x0A
#define PHY_BIST 0x0B
#define PHY_RAW_L 0x0C
#define PHY_RAW_H 0x0D
#define PHY_RAW_DATA 0x0E
#define PHY_HOST_CLK_CTRL 0x0F
#define PHY_DMR 0x10
#define PHY_BACR 0x11
#define PHY_IER 0x12
#define PHY_BCSR 0x13
#define PHY_BPR 0x14
#define PHY_BPNR2 0x15
#define PHY_BPNR 0x16
#define PHY_BRNR2 0x17
#define PHY_BENR 0x18
#define PHY_REG_REV 0x19
#define PHY_FLD0 0x1A
#define PHY_FLD1 0x1B
#define PHY_FLD2 0x1C
#define PHY_FLD3 0x1D
#define PHY_FLD4 0x1E
#define PHY_DUM_REG 0x1F
#define LCTLR 0x80
#define PCR_SETTING_REG1 0x724
#define PCR_SETTING_REG2 0x814
#define PCR_SETTING_REG3 0x747
#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
struct rtsx_pcr;
struct pcr_handle {
struct rtsx_pcr *pcr;
};
struct pcr_ops {
int (*extra_init_hw)(struct rtsx_pcr *pcr);
int (*optimize_phy)(struct rtsx_pcr *pcr);
int (*turn_on_led)(struct rtsx_pcr *pcr);
int (*turn_off_led)(struct rtsx_pcr *pcr);
int (*enable_auto_blink)(struct rtsx_pcr *pcr);
int (*disable_auto_blink)(struct rtsx_pcr *pcr);
int (*card_power_on)(struct rtsx_pcr *pcr, int card);
int (*card_power_off)(struct rtsx_pcr *pcr, int card);
int (*switch_output_voltage)(struct rtsx_pcr *pcr,
u8 voltage);
unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
int (*conv_clk_and_div_n)(int clk, int dir);
void (*init_settings)(struct rtsx_pcr *pcr);
void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
};
enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
struct rtsx_pcr {
struct pci_dev *pci;
unsigned int id;
/* pci resources */
unsigned long addr;
void __iomem *remap_addr;
int irq;
/* host reserved buffer */
void *rtsx_resv_buf;
dma_addr_t rtsx_resv_buf_addr;
void *host_cmds_ptr;
dma_addr_t host_cmds_addr;
int ci;
void *host_sg_tbl_ptr;
dma_addr_t host_sg_tbl_addr;
int sgi;
u32 bier;
char trans_result;
unsigned int card_inserted;
unsigned int card_removed;
unsigned int card_exist;
struct delayed_work carddet_work;
struct delayed_work idle_work;
spinlock_t lock;
struct mutex pcr_mutex;
struct completion *done;
struct completion *finish_me;
unsigned int cur_clock;
bool remove_pci;
bool msi_en;
#define EXTRA_CAPS_SD_SDR50 (1 << 0)
#define EXTRA_CAPS_SD_SDR104 (1 << 1)
#define EXTRA_CAPS_SD_DDR50 (1 << 2)
#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
#define EXTRA_CAPS_MMC_HS200 (1 << 4)
#define EXTRA_CAPS_MMC_8BIT (1 << 5)
u32 extra_caps;
#define IC_VER_A 0
#define IC_VER_B 1
#define IC_VER_C 2
#define IC_VER_D 3
u8 ic_version;
u8 sd30_drive_sel_1v8;
u8 sd30_drive_sel_3v3;
u8 card_drive_sel;
u8 aspm_en;
#define PCR_MS_PMOS (1 << 0)
#define PCR_REVERSE_SOCKET (1 << 1)
u32 flags;
const u32 *sd_pull_ctl_enable_tbl;
const u32 *sd_pull_ctl_disable_tbl;
const u32 *ms_pull_ctl_enable_tbl;
const u32 *ms_pull_ctl_disable_tbl;
const struct pcr_ops *ops;
enum PDEV_STAT state;
int num_slots;
struct rtsx_slot *slots;
};
#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
#define PCI_VID(pcr) ((pcr)->pci->vendor)
#define PCI_PID(pcr) ((pcr)->pci->device)
void rtsx_pci_start_run(struct rtsx_pcr *pcr);
int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
int num_sg, bool read, int timeout);
int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
{
return (u8 *)(pcr->host_cmds_ptr);
}
#endif

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/*
* core.h
*
* copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_CORE_H
#define __LINUX_MFD_SEC_CORE_H
#define NUM_IRQ_REGS 4
enum sec_device_type {
S5M8751X,
S5M8763X,
S5M8767X,
S2MPS11X,
};
/**
* struct sec_pmic_dev - s5m87xx master device for sub-drivers
* @dev: master device of the chip (can be used to access platform data)
* @pdata: pointer to private data used to pass platform data to child
* @i2c: i2c client private data for regulator
* @rtc: i2c client private data for rtc
* @iolock: mutex for serializing io access
* @irqlock: mutex for buslock
* @irq_base: base IRQ number for sec-pmic, required for IRQs
* @irq: generic IRQ number for s5m87xx
* @ono: power onoff IRQ number for s5m87xx
* @irq_masks_cur: currently active value
* @irq_masks_cache: cached hardware value
* @type: indicate which s5m87xx "variant" is used
*/
struct sec_pmic_dev {
struct device *dev;
struct sec_platform_data *pdata;
struct regmap *regmap;
struct i2c_client *i2c;
struct i2c_client *rtc;
struct mutex iolock;
struct mutex irqlock;
int device_type;
int irq_base;
int irq;
struct regmap_irq_chip_data *irq_data;
int ono;
u8 irq_masks_cur[NUM_IRQ_REGS];
u8 irq_masks_cache[NUM_IRQ_REGS];
int type;
bool wakeup;
};
int sec_irq_init(struct sec_pmic_dev *sec_pmic);
void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest);
extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value);
extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask);
struct sec_platform_data {
struct sec_regulator_data *regulators;
struct sec_opmode_data *opmode;
int device_type;
int num_regulators;
int irq_base;
int (*cfg_pmic_irq)(void);
int ono;
bool wakeup;
bool buck_voltage_lock;
int buck_gpios[3];
int buck_ds[3];
unsigned int buck2_voltage[8];
bool buck2_gpiodvs;
unsigned int buck3_voltage[8];
bool buck3_gpiodvs;
unsigned int buck4_voltage[8];
bool buck4_gpiodvs;
int buck_set1;
int buck_set2;
int buck_set3;
int buck2_enable;
int buck3_enable;
int buck4_enable;
int buck_default_idx;
int buck2_default_idx;
int buck3_default_idx;
int buck4_default_idx;
int buck_ramp_delay;
int buck2_ramp_delay;
int buck34_ramp_delay;
int buck5_ramp_delay;
int buck16_ramp_delay;
int buck7810_ramp_delay;
int buck9_ramp_delay;
bool buck2_ramp_enable;
bool buck3_ramp_enable;
bool buck4_ramp_enable;
bool buck6_ramp_enable;
int buck2_init;
int buck3_init;
int buck4_init;
};
/**
* sec_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct sec_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
struct sec_opmode_data {
int id;
unsigned int mode;
};
/*
* samsung regulator operation mode
* SEC_OPMODE_OFF Regulator always OFF
* SEC_OPMODE_ON Regulator always ON
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
* If PWREN is high, regulator is on
* If PWREN is low, regulator is off
*/
enum sec_opmode {
SEC_OPMODE_OFF,
SEC_OPMODE_ON,
SEC_OPMODE_LOWPOWER,
SEC_OPMODE_SUSPEND,
};
#endif /* __LINUX_MFD_SEC_CORE_H */

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/* irq.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_IRQ_H
#define __LINUX_MFD_SEC_IRQ_H
enum s2mps11_irq {
S2MPS11_IRQ_PWRONF,
S2MPS11_IRQ_PWRONR,
S2MPS11_IRQ_JIGONBF,
S2MPS11_IRQ_JIGONBR,
S2MPS11_IRQ_ACOKBF,
S2MPS11_IRQ_ACOKBR,
S2MPS11_IRQ_PWRON1S,
S2MPS11_IRQ_MRB,
S2MPS11_IRQ_RTC60S,
S2MPS11_IRQ_RTCA1,
S2MPS11_IRQ_RTCA2,
S2MPS11_IRQ_SMPL,
S2MPS11_IRQ_RTC1S,
S2MPS11_IRQ_WTSR,
S2MPS11_IRQ_INT120C,
S2MPS11_IRQ_INT140C,
S2MPS11_IRQ_NR,
};
#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS11_IRQ_MRB_MASK (1 << 7)
#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS11_IRQ_RTCA2_MASK (1 << 2)
#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
enum s5m8767_irq {
S5M8767_IRQ_PWRR,
S5M8767_IRQ_PWRF,
S5M8767_IRQ_PWR1S,
S5M8767_IRQ_JIGR,
S5M8767_IRQ_JIGF,
S5M8767_IRQ_LOWBAT2,
S5M8767_IRQ_LOWBAT1,
S5M8767_IRQ_MRB,
S5M8767_IRQ_DVSOK2,
S5M8767_IRQ_DVSOK3,
S5M8767_IRQ_DVSOK4,
S5M8767_IRQ_RTC60S,
S5M8767_IRQ_RTCA1,
S5M8767_IRQ_RTCA2,
S5M8767_IRQ_SMPL,
S5M8767_IRQ_RTC1S,
S5M8767_IRQ_WTSR,
S5M8767_IRQ_NR,
};
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
#define S5M8767_IRQ_MRB_MASK (1 << 2)
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
enum s5m8763_irq {
S5M8763_IRQ_DCINF,
S5M8763_IRQ_DCINR,
S5M8763_IRQ_JIGF,
S5M8763_IRQ_JIGR,
S5M8763_IRQ_PWRONF,
S5M8763_IRQ_PWRONR,
S5M8763_IRQ_WTSREVNT,
S5M8763_IRQ_SMPLEVNT,
S5M8763_IRQ_ALARM1,
S5M8763_IRQ_ALARM0,
S5M8763_IRQ_ONKEY1S,
S5M8763_IRQ_TOPOFFR,
S5M8763_IRQ_DCINOVPR,
S5M8763_IRQ_CHGRSTF,
S5M8763_IRQ_DONER,
S5M8763_IRQ_CHGFAULT,
S5M8763_IRQ_LOBAT1,
S5M8763_IRQ_LOBAT2,
S5M8763_IRQ_NR,
};
#define S5M8763_IRQ_DCINF_MASK (1 << 2)
#define S5M8763_IRQ_DCINR_MASK (1 << 3)
#define S5M8763_IRQ_JIGF_MASK (1 << 4)
#define S5M8763_IRQ_JIGR_MASK (1 << 5)
#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
#define S5M8763_IRQ_DONER_MASK (1 << 5)
#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
#define S5M8763_ENRAMP (1 << 4)
#endif /* __LINUX_MFD_SEC_IRQ_H */

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/* rtc.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_RTC_H
#define __LINUX_MFD_SEC_RTC_H
enum sec_rtc_reg {
SEC_RTC_SEC,
SEC_RTC_MIN,
SEC_RTC_HOUR,
SEC_RTC_WEEKDAY,
SEC_RTC_DATE,
SEC_RTC_MONTH,
SEC_RTC_YEAR1,
SEC_RTC_YEAR2,
SEC_ALARM0_SEC,
SEC_ALARM0_MIN,
SEC_ALARM0_HOUR,
SEC_ALARM0_WEEKDAY,
SEC_ALARM0_DATE,
SEC_ALARM0_MONTH,
SEC_ALARM0_YEAR1,
SEC_ALARM0_YEAR2,
SEC_ALARM1_SEC,
SEC_ALARM1_MIN,
SEC_ALARM1_HOUR,
SEC_ALARM1_WEEKDAY,
SEC_ALARM1_DATE,
SEC_ALARM1_MONTH,
SEC_ALARM1_YEAR1,
SEC_ALARM1_YEAR2,
SEC_ALARM0_CONF,
SEC_ALARM1_CONF,
SEC_RTC_STATUS,
SEC_WTSR_SMPL_CNTL,
SEC_RTC_UDR_CON,
};
#define RTC_I2C_ADDR (0x0C >> 1)
#define HOUR_12 (1 << 7)
#define HOUR_AMPM (1 << 6)
#define HOUR_PM (1 << 5)
#define ALARM0_STATUS (1 << 1)
#define ALARM1_STATUS (1 << 2)
#define UPDATE_AD (1 << 0)
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* RTC Update Register1 */
#define RTC_UDR_SHIFT 0
#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_DATE,
RTC_MONTH,
RTC_YEAR1,
RTC_YEAR2,
};
#endif /* __LINUX_MFD_SEC_RTC_H */

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include/linux/mfd/samsung/s2mps11.h Normal file
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/*
* s2mps11.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPS11_H
#define __LINUX_MFD_S2MPS11_H
/* S2MPS11 registers */
enum s2mps11_reg {
S2MPS11_REG_ID,
S2MPS11_REG_INT1,
S2MPS11_REG_INT2,
S2MPS11_REG_INT3,
S2MPS11_REG_INT1M,
S2MPS11_REG_INT2M,
S2MPS11_REG_INT3M,
S2MPS11_REG_ST1,
S2MPS11_REG_ST2,
S2MPS11_REG_OFFSRC,
S2MPS11_REG_PWRONSRC,
S2MPS11_REG_RTC_CTRL,
S2MPS11_REG_CTRL1,
S2MPS11_REG_ETC_TEST,
S2MPS11_REG_RSVD3,
S2MPS11_REG_BU_CHG,
S2MPS11_REG_RAMP,
S2MPS11_REG_RAMP_BUCK,
S2MPS11_REG_LDO1_8,
S2MPS11_REG_LDO9_16,
S2MPS11_REG_LDO17_24,
S2MPS11_REG_LDO25_32,
S2MPS11_REG_LDO33_38,
S2MPS11_REG_LDO1_8_1,
S2MPS11_REG_LDO9_16_1,
S2MPS11_REG_LDO17_24_1,
S2MPS11_REG_LDO25_32_1,
S2MPS11_REG_LDO33_38_1,
S2MPS11_REG_OTP_ADRL,
S2MPS11_REG_OTP_ADRH,
S2MPS11_REG_OTP_DATA,
S2MPS11_REG_MON1SEL,
S2MPS11_REG_MON2SEL,
S2MPS11_REG_LEE,
S2MPS11_REG_RSVD_NO,
S2MPS11_REG_UVLO,
S2MPS11_REG_LEE_NO,
S2MPS11_REG_B1CTRL1,
S2MPS11_REG_B1CTRL2,
S2MPS11_REG_B2CTRL1,
S2MPS11_REG_B2CTRL2,
S2MPS11_REG_B3CTRL1,
S2MPS11_REG_B3CTRL2,
S2MPS11_REG_B4CTRL1,
S2MPS11_REG_B4CTRL2,
S2MPS11_REG_B5CTRL1,
S2MPS11_REG_BUCK5_SW,
S2MPS11_REG_B5CTRL2,
S2MPS11_REG_B5CTRL3,
S2MPS11_REG_B5CTRL4,
S2MPS11_REG_B5CTRL5,
S2MPS11_REG_B6CTRL1,
S2MPS11_REG_B6CTRL2,
S2MPS11_REG_B7CTRL1,
S2MPS11_REG_B7CTRL2,
S2MPS11_REG_B8CTRL1,
S2MPS11_REG_B8CTRL2,
S2MPS11_REG_B9CTRL1,
S2MPS11_REG_B9CTRL2,
S2MPS11_REG_B10CTRL1,
S2MPS11_REG_B10CTRL2,
S2MPS11_REG_L1CTRL,
S2MPS11_REG_L2CTRL,
S2MPS11_REG_L3CTRL,
S2MPS11_REG_L4CTRL,
S2MPS11_REG_L5CTRL,
S2MPS11_REG_L6CTRL,
S2MPS11_REG_L7CTRL,
S2MPS11_REG_L8CTRL,
S2MPS11_REG_L9CTRL,
S2MPS11_REG_L10CTRL,
S2MPS11_REG_L11CTRL,
S2MPS11_REG_L12CTRL,
S2MPS11_REG_L13CTRL,
S2MPS11_REG_L14CTRL,
S2MPS11_REG_L15CTRL,
S2MPS11_REG_L16CTRL,
S2MPS11_REG_L17CTRL,
S2MPS11_REG_L18CTRL,
S2MPS11_REG_L19CTRL,
S2MPS11_REG_L20CTRL,
S2MPS11_REG_L21CTRL,
S2MPS11_REG_L22CTRL,
S2MPS11_REG_L23CTRL,
S2MPS11_REG_L24CTRL,
S2MPS11_REG_L25CTRL,
S2MPS11_REG_L26CTRL,
S2MPS11_REG_L27CTRL,
S2MPS11_REG_L28CTRL,
S2MPS11_REG_L29CTRL,
S2MPS11_REG_L30CTRL,
S2MPS11_REG_L31CTRL,
S2MPS11_REG_L32CTRL,
S2MPS11_REG_L33CTRL,
S2MPS11_REG_L34CTRL,
S2MPS11_REG_L35CTRL,
S2MPS11_REG_L36CTRL,
S2MPS11_REG_L37CTRL,
S2MPS11_REG_L38CTRL,
};
/* S2MPS11 regulator ids */
enum s2mps11_regulators {
S2MPS11_LDO1,
S2MPS11_LDO2,
S2MPS11_LDO3,
S2MPS11_LDO4,
S2MPS11_LDO5,
S2MPS11_LDO6,
S2MPS11_LDO7,
S2MPS11_LDO8,
S2MPS11_LDO9,
S2MPS11_LDO10,
S2MPS11_LDO11,
S2MPS11_LDO12,
S2MPS11_LDO13,
S2MPS11_LDO14,
S2MPS11_LDO15,
S2MPS11_LDO16,
S2MPS11_LDO17,
S2MPS11_LDO18,
S2MPS11_LDO19,
S2MPS11_LDO20,
S2MPS11_LDO21,
S2MPS11_LDO22,
S2MPS11_LDO23,
S2MPS11_LDO24,
S2MPS11_LDO25,
S2MPS11_LDO26,
S2MPS11_LDO27,
S2MPS11_LDO28,
S2MPS11_LDO29,
S2MPS11_LDO30,
S2MPS11_LDO31,
S2MPS11_LDO32,
S2MPS11_LDO33,
S2MPS11_LDO34,
S2MPS11_LDO35,
S2MPS11_LDO36,
S2MPS11_LDO37,
S2MPS11_LDO38,
S2MPS11_BUCK1,
S2MPS11_BUCK2,
S2MPS11_BUCK3,
S2MPS11_BUCK4,
S2MPS11_BUCK5,
S2MPS11_BUCK6,
S2MPS11_BUCK7,
S2MPS11_BUCK8,
S2MPS11_BUCK9,
S2MPS11_BUCK10,
S2MPS11_AP_EN32KHZ,
S2MPS11_CP_EN32KHZ,
S2MPS11_BT_EN32KHZ,
S2MPS11_REG_MAX,
};
#define S2MPS11_BUCK_MIN1 600000
#define S2MPS11_BUCK_MIN2 750000
#define S2MPS11_BUCK_MIN3 3000000
#define S2MPS11_LDO_MIN 800000
#define S2MPS11_BUCK_STEP1 6250
#define S2MPS11_BUCK_STEP2 12500
#define S2MPS11_BUCK_STEP3 25000
#define S2MPS11_LDO_STEP1 50000
#define S2MPS11_LDO_STEP2 25000
#define S2MPS11_LDO_VSEL_MASK 0x3F
#define S2MPS11_BUCK_VSEL_MASK 0xFF
#define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
#define S2MPS11_ENABLE_SHIFT 0x06
#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
#define S2MPS11_PMIC_EN_SHIFT 6
#define S2MPS11_REGULATOR_MAX (S2MPS11_REG_MAX - 3)
#endif /* __LINUX_MFD_S2MPS11_H */

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/* s5m8763.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M8763_H
#define __LINUX_MFD_S5M8763_H
/* S5M8763 registers */
enum s5m8763_reg {
S5M8763_REG_IRQ1,
S5M8763_REG_IRQ2,
S5M8763_REG_IRQ3,
S5M8763_REG_IRQ4,
S5M8763_REG_IRQM1,
S5M8763_REG_IRQM2,
S5M8763_REG_IRQM3,
S5M8763_REG_IRQM4,
S5M8763_REG_STATUS1,
S5M8763_REG_STATUS2,
S5M8763_REG_STATUSM1,
S5M8763_REG_STATUSM2,
S5M8763_REG_CHGR1,
S5M8763_REG_CHGR2,
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
S5M8763_REG_ONOFF1,
S5M8763_REG_ONOFF2,
S5M8763_REG_ONOFF3,
S5M8763_REG_ONOFF4,
S5M8763_REG_BUCK1_VOLTAGE1,
S5M8763_REG_BUCK1_VOLTAGE2,
S5M8763_REG_BUCK1_VOLTAGE3,
S5M8763_REG_BUCK1_VOLTAGE4,
S5M8763_REG_BUCK2_VOLTAGE1,
S5M8763_REG_BUCK2_VOLTAGE2,
S5M8763_REG_BUCK3,
S5M8763_REG_BUCK4,
S5M8763_REG_LDO1_LDO2,
S5M8763_REG_LDO3,
S5M8763_REG_LDO4,
S5M8763_REG_LDO5,
S5M8763_REG_LDO6,
S5M8763_REG_LDO7,
S5M8763_REG_LDO7_LDO8,
S5M8763_REG_LDO9_LDO10,
S5M8763_REG_LDO11,
S5M8763_REG_LDO12,
S5M8763_REG_LDO13,
S5M8763_REG_LDO14,
S5M8763_REG_LDO15,
S5M8763_REG_LDO16,
S5M8763_REG_BKCHR,
S5M8763_REG_LBCNFG1,
S5M8763_REG_LBCNFG2,
};
/* S5M8763 regulator ids */
enum s5m8763_regulators {
S5M8763_LDO1,
S5M8763_LDO2,
S5M8763_LDO3,
S5M8763_LDO4,
S5M8763_LDO5,
S5M8763_LDO6,
S5M8763_LDO7,
S5M8763_LDO8,
S5M8763_LDO9,
S5M8763_LDO10,
S5M8763_LDO11,
S5M8763_LDO12,
S5M8763_LDO13,
S5M8763_LDO14,
S5M8763_LDO15,
S5M8763_LDO16,
S5M8763_BUCK1,
S5M8763_BUCK2,
S5M8763_BUCK3,
S5M8763_BUCK4,
S5M8763_AP_EN32KHZ,
S5M8763_CP_EN32KHZ,
S5M8763_ENCHGVI,
S5M8763_ESAFEUSB1,
S5M8763_ESAFEUSB2,
};
#define S5M8763_ENRAMP (1 << 4)
#endif /* __LINUX_MFD_S5M8763_H */

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/* s5m8767.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M8767_H
#define __LINUX_MFD_S5M8767_H
/* S5M8767 registers */
enum s5m8767_reg {
S5M8767_REG_ID,
S5M8767_REG_INT1,
S5M8767_REG_INT2,
S5M8767_REG_INT3,
S5M8767_REG_INT1M,
S5M8767_REG_INT2M,
S5M8767_REG_INT3M,
S5M8767_REG_STATUS1,
S5M8767_REG_STATUS2,
S5M8767_REG_STATUS3,
S5M8767_REG_CTRL1,
S5M8767_REG_CTRL2,
S5M8767_REG_LOWBAT1,
S5M8767_REG_LOWBAT2,
S5M8767_REG_BUCHG,
S5M8767_REG_DVSRAMP,
S5M8767_REG_DVSTIMER2 = 0x10,
S5M8767_REG_DVSTIMER3,
S5M8767_REG_DVSTIMER4,
S5M8767_REG_LDO1,
S5M8767_REG_LDO2,
S5M8767_REG_LDO3,
S5M8767_REG_LDO4,
S5M8767_REG_LDO5,
S5M8767_REG_LDO6,
S5M8767_REG_LDO7,
S5M8767_REG_LDO8,
S5M8767_REG_LDO9,
S5M8767_REG_LDO10,
S5M8767_REG_LDO11,
S5M8767_REG_LDO12,
S5M8767_REG_LDO13,
S5M8767_REG_LDO14 = 0x20,
S5M8767_REG_LDO15,
S5M8767_REG_LDO16,
S5M8767_REG_LDO17,
S5M8767_REG_LDO18,
S5M8767_REG_LDO19,
S5M8767_REG_LDO20,
S5M8767_REG_LDO21,
S5M8767_REG_LDO22,
S5M8767_REG_LDO23,
S5M8767_REG_LDO24,
S5M8767_REG_LDO25,
S5M8767_REG_LDO26,
S5M8767_REG_LDO27,
S5M8767_REG_LDO28,
S5M8767_REG_UVLO = 0x31,
S5M8767_REG_BUCK1CTRL1,
S5M8767_REG_BUCK1CTRL2,
S5M8767_REG_BUCK2CTRL,
S5M8767_REG_BUCK2DVS1,
S5M8767_REG_BUCK2DVS2,
S5M8767_REG_BUCK2DVS3,
S5M8767_REG_BUCK2DVS4,
S5M8767_REG_BUCK2DVS5,
S5M8767_REG_BUCK2DVS6,
S5M8767_REG_BUCK2DVS7,
S5M8767_REG_BUCK2DVS8,
S5M8767_REG_BUCK3CTRL,
S5M8767_REG_BUCK3DVS1,
S5M8767_REG_BUCK3DVS2,
S5M8767_REG_BUCK3DVS3,
S5M8767_REG_BUCK3DVS4,
S5M8767_REG_BUCK3DVS5,
S5M8767_REG_BUCK3DVS6,
S5M8767_REG_BUCK3DVS7,
S5M8767_REG_BUCK3DVS8,
S5M8767_REG_BUCK4CTRL,
S5M8767_REG_BUCK4DVS1,
S5M8767_REG_BUCK4DVS2,
S5M8767_REG_BUCK4DVS3,
S5M8767_REG_BUCK4DVS4,
S5M8767_REG_BUCK4DVS5,
S5M8767_REG_BUCK4DVS6,
S5M8767_REG_BUCK4DVS7,
S5M8767_REG_BUCK4DVS8,
S5M8767_REG_BUCK5CTRL1,
S5M8767_REG_BUCK5CTRL2,
S5M8767_REG_BUCK5CTRL3,
S5M8767_REG_BUCK5CTRL4,
S5M8767_REG_BUCK5CTRL5,
S5M8767_REG_BUCK6CTRL1,
S5M8767_REG_BUCK6CTRL2,
S5M8767_REG_BUCK7CTRL1,
S5M8767_REG_BUCK7CTRL2,
S5M8767_REG_BUCK8CTRL1,
S5M8767_REG_BUCK8CTRL2,
S5M8767_REG_BUCK9CTRL1,
S5M8767_REG_BUCK9CTRL2,
S5M8767_REG_LDO1CTRL,
S5M8767_REG_LDO2_1CTRL,
S5M8767_REG_LDO2_2CTRL,
S5M8767_REG_LDO2_3CTRL,
S5M8767_REG_LDO2_4CTRL,
S5M8767_REG_LDO3CTRL,
S5M8767_REG_LDO4CTRL,
S5M8767_REG_LDO5CTRL,
S5M8767_REG_LDO6CTRL,
S5M8767_REG_LDO7CTRL,
S5M8767_REG_LDO8CTRL,
S5M8767_REG_LDO9CTRL,
S5M8767_REG_LDO10CTRL,
S5M8767_REG_LDO11CTRL,
S5M8767_REG_LDO12CTRL,
S5M8767_REG_LDO13CTRL,
S5M8767_REG_LDO14CTRL,
S5M8767_REG_LDO15CTRL,
S5M8767_REG_LDO16CTRL,
S5M8767_REG_LDO17CTRL,
S5M8767_REG_LDO18CTRL,
S5M8767_REG_LDO19CTRL,
S5M8767_REG_LDO20CTRL,
S5M8767_REG_LDO21CTRL,
S5M8767_REG_LDO22CTRL,
S5M8767_REG_LDO23CTRL,
S5M8767_REG_LDO24CTRL,
S5M8767_REG_LDO25CTRL,
S5M8767_REG_LDO26CTRL,
S5M8767_REG_LDO27CTRL,
S5M8767_REG_LDO28CTRL,
};
/* S5M8767 regulator ids */
enum s5m8767_regulators {
S5M8767_LDO1,
S5M8767_LDO2,
S5M8767_LDO3,
S5M8767_LDO4,
S5M8767_LDO5,
S5M8767_LDO6,
S5M8767_LDO7,
S5M8767_LDO8,
S5M8767_LDO9,
S5M8767_LDO10,
S5M8767_LDO11,
S5M8767_LDO12,
S5M8767_LDO13,
S5M8767_LDO14,
S5M8767_LDO15,
S5M8767_LDO16,
S5M8767_LDO17,
S5M8767_LDO18,
S5M8767_LDO19,
S5M8767_LDO20,
S5M8767_LDO21,
S5M8767_LDO22,
S5M8767_LDO23,
S5M8767_LDO24,
S5M8767_LDO25,
S5M8767_LDO26,
S5M8767_LDO27,
S5M8767_LDO28,
S5M8767_BUCK1,
S5M8767_BUCK2,
S5M8767_BUCK3,
S5M8767_BUCK4,
S5M8767_BUCK5,
S5M8767_BUCK6,
S5M8767_BUCK7,
S5M8767_BUCK8,
S5M8767_BUCK9,
S5M8767_AP_EN32KHZ,
S5M8767_CP_EN32KHZ,
S5M8767_REG_MAX,
};
#define S5M8767_ENCTRL_SHIFT 6
#endif /* __LINUX_MFD_S5M8767_H */

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include/linux/mfd/si476x-core.h Normal file
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/*
* include/media/si476x-core.h -- Common definitions for si476x core
* device
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef SI476X_CORE_H
#define SI476X_CORE_H
#include <linux/kfifo.h>
#include <linux/atomic.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/videodev2.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/si476x-platform.h>
#include <linux/mfd/si476x-reports.h>
/* Command Timeouts */
#define SI476X_DEFAULT_TIMEOUT 100000
#define SI476X_TIMEOUT_TUNE 700000
#define SI476X_TIMEOUT_POWER_UP 330000
#define SI476X_STATUS_POLL_US 0
/* -------------------- si476x-i2c.c ----------------------- */
enum si476x_freq_supported_chips {
SI476X_CHIP_SI4761 = 1,
SI476X_CHIP_SI4764,
SI476X_CHIP_SI4768,
};
enum si476x_part_revisions {
SI476X_REVISION_A10 = 0,
SI476X_REVISION_A20 = 1,
SI476X_REVISION_A30 = 2,
};
enum si476x_mfd_cells {
SI476X_RADIO_CELL = 0,
SI476X_CODEC_CELL,
SI476X_MFD_CELLS,
};
/**
* enum si476x_power_state - possible power state of the si476x
* device.
*
* @SI476X_POWER_DOWN: In this state all regulators are turned off
* and the reset line is pulled low. The device is completely
* inactive.
* @SI476X_POWER_UP_FULL: In this state all the power regualtors are
* turned on, reset line pulled high, IRQ line is enabled(polling is
* active for polling use scenario) and device is turned on with
* POWER_UP command. The device is ready to be used.
* @SI476X_POWER_INCONSISTENT: This state indicates that previous
* power down was inconsistent, meaning some of the regulators were
* not turned down and thus use of the device, without power-cycling
* is impossible.
*/
enum si476x_power_state {
SI476X_POWER_DOWN = 0,
SI476X_POWER_UP_FULL = 1,
SI476X_POWER_INCONSISTENT = 2,
};
/**
* struct si476x_core - internal data structure representing the
* underlying "core" device which all the MFD cell-devices use.
*
* @client: Actual I2C client used to transfer commands to the chip.
* @chip_id: Last digit of the chip model(E.g. "1" for SI4761)
* @cells: MFD cell devices created by this driver.
* @cmd_lock: Mutex used to serialize all the requests to the core
* device. This filed should not be used directly. Instead
* si476x_core_lock()/si476x_core_unlock() should be used to get
* exclusive access to the "core" device.
* @users: Active users counter(Used by the radio cell)
* @rds_read_queue: Wait queue used to wait for RDS data.
* @rds_fifo: FIFO in which all the RDS data received from the chip is
* placed.
* @rds_fifo_drainer: Worker that drains on-chip RDS FIFO.
* @rds_drainer_is_working: Flag used for launching only one instance
* of the @rds_fifo_drainer.
* @rds_drainer_status_lock: Lock used to guard access to the
* @rds_drainer_is_working variable.
* @command: Wait queue for wainting on the command comapletion.
* @cts: Clear To Send flag set upon receiving first status with CTS
* set.
* @tuning: Wait queue used for wainting for tune/seek comand
* completion.
* @stc: Similar to @cts, but for the STC bit of the status value.
* @power_up_parameters: Parameters used as argument for POWER_UP
* command when the device is started.
* @state: Current power state of the device.
* @supplues: Structure containing handles to all power supplies used
* by the device (NULL ones are ignored).
* @gpio_reset: GPIO pin connectet to the RSTB pin of the chip.
* @pinmux: Chip's configurable pins configuration.
* @diversity_mode: Chips role when functioning in diversity mode.
* @status_monitor: Polling worker used in polling use case scenarion
* (when IRQ is not avalible).
* @revision: Chip's running firmware revision number(Used for correct
* command set support).
*/
struct si476x_core {
struct i2c_client *client;
struct regmap *regmap;
int chip_id;
struct mfd_cell cells[SI476X_MFD_CELLS];
struct mutex cmd_lock; /* for serializing fm radio operations */
atomic_t users;
wait_queue_head_t rds_read_queue;
struct kfifo rds_fifo;
struct work_struct rds_fifo_drainer;
bool rds_drainer_is_working;
struct mutex rds_drainer_status_lock;
wait_queue_head_t command;
atomic_t cts;
wait_queue_head_t tuning;
atomic_t stc;
struct si476x_power_up_args power_up_parameters;
enum si476x_power_state power_state;
struct regulator_bulk_data supplies[4];
int gpio_reset;
struct si476x_pinmux pinmux;
enum si476x_phase_diversity_mode diversity_mode;
atomic_t is_alive;
struct delayed_work status_monitor;
#define SI476X_WORK_TO_CORE(w) container_of(to_delayed_work(w), \
struct si476x_core, \
status_monitor)
int revision;
int rds_fifo_depth;
};
static inline struct si476x_core *i2c_mfd_cell_to_core(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev->parent);
return i2c_get_clientdata(client);
}
/**
* si476x_core_lock() - lock the core device to get an exclusive access
* to it.
*/
static inline void si476x_core_lock(struct si476x_core *core)
{
mutex_lock(&core->cmd_lock);
}
/**
* si476x_core_unlock() - unlock the core device to relinquish an
* exclusive access to it.
*/
static inline void si476x_core_unlock(struct si476x_core *core)
{
mutex_unlock(&core->cmd_lock);
}
/* *_TUNE_FREQ family of commands accept frequency in multiples of
10kHz */
static inline u16 hz_to_si476x(struct si476x_core *core, int freq)
{
u16 result;
switch (core->power_up_parameters.func) {
default:
case SI476X_FUNC_FM_RECEIVER:
result = freq / 10000;
break;
case SI476X_FUNC_AM_RECEIVER:
result = freq / 1000;
break;
}
return result;
}
static inline int si476x_to_hz(struct si476x_core *core, u16 freq)
{
int result;
switch (core->power_up_parameters.func) {
default:
case SI476X_FUNC_FM_RECEIVER:
result = freq * 10000;
break;
case SI476X_FUNC_AM_RECEIVER:
result = freq * 1000;
break;
}
return result;
}
/* Since the V4L2_TUNER_CAP_LOW flag is supplied, V4L2 subsystem
* mesures frequency in 62.5 Hz units */
static inline int hz_to_v4l2(int freq)
{
return (freq * 10) / 625;
}
static inline int v4l2_to_hz(int freq)
{
return (freq * 625) / 10;
}
static inline u16 v4l2_to_si476x(struct si476x_core *core, int freq)
{
return hz_to_si476x(core, v4l2_to_hz(freq));
}
static inline int si476x_to_v4l2(struct si476x_core *core, u16 freq)
{
return hz_to_v4l2(si476x_to_hz(core, freq));
}
/**
* struct si476x_func_info - structure containing result of the
* FUNC_INFO command.
*
* @firmware.major: Firmware major number.
* @firmware.minor[...]: Firmware minor numbers.
* @patch_id:
* @func: Mode tuner is working in.
*/
struct si476x_func_info {
struct {
u8 major, minor[2];
} firmware;
u16 patch_id;
enum si476x_func func;
};
/**
* struct si476x_power_down_args - structure used to pass parameters
* to POWER_DOWN command
*
* @xosc: true - Power down, but leav oscillator running.
* false - Full power down.
*/
struct si476x_power_down_args {
bool xosc;
};
/**
* enum si476x_tunemode - enum representing possible tune modes for
* the chip.
* @SI476X_TM_VALIDATED_NORMAL_TUNE: Unconditionally stay on the new
* channel after tune, tune status is valid.
* @SI476X_TM_INVALIDATED_FAST_TUNE: Unconditionally stay in the new
* channel after tune, tune status invalid.
* @SI476X_TM_VALIDATED_AF_TUNE: Jump back to previous channel if
* metric thresholds are not met.
* @SI476X_TM_VALIDATED_AF_CHECK: Unconditionally jump back to the
* previous channel.
*/
enum si476x_tunemode {
SI476X_TM_VALIDATED_NORMAL_TUNE = 0,
SI476X_TM_INVALIDATED_FAST_TUNE = 1,
SI476X_TM_VALIDATED_AF_TUNE = 2,
SI476X_TM_VALIDATED_AF_CHECK = 3,
};
/**
* enum si476x_smoothmetrics - enum containing the possible setting fo
* audio transitioning of the chip
* @SI476X_SM_INITIALIZE_AUDIO: Initialize audio state to match this
* new channel
* @SI476X_SM_TRANSITION_AUDIO: Transition audio state from previous
* channel values to the new values
*/
enum si476x_smoothmetrics {
SI476X_SM_INITIALIZE_AUDIO = 0,
SI476X_SM_TRANSITION_AUDIO = 1,
};
/**
* struct si476x_rds_status_report - the structure representing the
* response to 'FM_RD_STATUS' command
* @rdstpptyint: Traffic program flag(TP) and/or program type(PTY)
* code has changed.
* @rdspiint: Program identification(PI) code has changed.
* @rdssyncint: RDS synchronization has changed.
* @rdsfifoint: RDS was received and the RDS FIFO has at least
* 'FM_RDS_INTERRUPT_FIFO_COUNT' elements in it.
* @tpptyvalid: TP flag and PTY code are valid falg.
* @pivalid: PI code is valid flag.
* @rdssync: RDS is currently synchronized.
* @rdsfifolost: On or more RDS groups have been lost/discarded flag.
* @tp: Current channel's TP flag.
* @pty: Current channel's PTY code.
* @pi: Current channel's PI code.
* @rdsfifoused: Number of blocks remaining in the RDS FIFO (0 if
* empty).
*/
struct si476x_rds_status_report {
bool rdstpptyint, rdspiint, rdssyncint, rdsfifoint;
bool tpptyvalid, pivalid, rdssync, rdsfifolost;
bool tp;
u8 pty;
u16 pi;
u8 rdsfifoused;
u8 ble[4];
struct v4l2_rds_data rds[4];
};
struct si476x_rsq_status_args {
bool primary;
bool rsqack;
bool attune;
bool cancel;
bool stcack;
};
enum si476x_injside {
SI476X_INJSIDE_AUTO = 0,
SI476X_INJSIDE_LOW = 1,
SI476X_INJSIDE_HIGH = 2,
};
struct si476x_tune_freq_args {
bool zifsr;
bool hd;
enum si476x_injside injside;
int freq;
enum si476x_tunemode tunemode;
enum si476x_smoothmetrics smoothmetrics;
int antcap;
};
int si476x_core_stop(struct si476x_core *, bool);
int si476x_core_start(struct si476x_core *, bool);
int si476x_core_set_power_state(struct si476x_core *, enum si476x_power_state);
bool si476x_core_has_am(struct si476x_core *);
bool si476x_core_has_diversity(struct si476x_core *);
bool si476x_core_is_a_secondary_tuner(struct si476x_core *);
bool si476x_core_is_a_primary_tuner(struct si476x_core *);
bool si476x_core_is_in_am_receiver_mode(struct si476x_core *core);
bool si476x_core_is_powered_up(struct si476x_core *core);
enum si476x_i2c_type {
SI476X_I2C_SEND,
SI476X_I2C_RECV
};
int si476x_core_i2c_xfer(struct si476x_core *,
enum si476x_i2c_type,
char *, int);
/* -------------------- si476x-cmd.c ----------------------- */
int si476x_core_cmd_func_info(struct si476x_core *, struct si476x_func_info *);
int si476x_core_cmd_set_property(struct si476x_core *, u16, u16);
int si476x_core_cmd_get_property(struct si476x_core *, u16);
int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *,
enum si476x_dclk_config,
enum si476x_dfs_config,
enum si476x_dout_config,
enum si476x_xout_config);
int si476x_core_cmd_zif_pin_cfg(struct si476x_core *,
enum si476x_iqclk_config,
enum si476x_iqfs_config,
enum si476x_iout_config,
enum si476x_qout_config);
int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *,
enum si476x_icin_config,
enum si476x_icip_config,
enum si476x_icon_config,
enum si476x_icop_config);
int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *,
enum si476x_lrout_config);
int si476x_core_cmd_intb_pin_cfg(struct si476x_core *, enum si476x_intb_config,
enum si476x_a1_config);
int si476x_core_cmd_fm_seek_start(struct si476x_core *, bool, bool);
int si476x_core_cmd_am_seek_start(struct si476x_core *, bool, bool);
int si476x_core_cmd_fm_rds_status(struct si476x_core *, bool, bool, bool,
struct si476x_rds_status_report *);
int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *, bool,
struct si476x_rds_blockcount_report *);
int si476x_core_cmd_fm_tune_freq(struct si476x_core *,
struct si476x_tune_freq_args *);
int si476x_core_cmd_am_tune_freq(struct si476x_core *,
struct si476x_tune_freq_args *);
int si476x_core_cmd_am_rsq_status(struct si476x_core *,
struct si476x_rsq_status_args *,
struct si476x_rsq_status_report *);
int si476x_core_cmd_fm_rsq_status(struct si476x_core *,
struct si476x_rsq_status_args *,
struct si476x_rsq_status_report *);
int si476x_core_cmd_power_up(struct si476x_core *,
struct si476x_power_up_args *);
int si476x_core_cmd_power_down(struct si476x_core *,
struct si476x_power_down_args *);
int si476x_core_cmd_fm_phase_div_status(struct si476x_core *);
int si476x_core_cmd_fm_phase_diversity(struct si476x_core *,
enum si476x_phase_diversity_mode);
int si476x_core_cmd_fm_acf_status(struct si476x_core *,
struct si476x_acf_status_report *);
int si476x_core_cmd_am_acf_status(struct si476x_core *,
struct si476x_acf_status_report *);
int si476x_core_cmd_agc_status(struct si476x_core *,
struct si476x_agc_status_report *);
enum si476x_power_grid_type {
SI476X_POWER_GRID_50HZ = 0,
SI476X_POWER_GRID_60HZ,
};
/* Properties */
enum si476x_interrupt_flags {
SI476X_STCIEN = (1 << 0),
SI476X_ACFIEN = (1 << 1),
SI476X_RDSIEN = (1 << 2),
SI476X_RSQIEN = (1 << 3),
SI476X_ERRIEN = (1 << 6),
SI476X_CTSIEN = (1 << 7),
SI476X_STCREP = (1 << 8),
SI476X_ACFREP = (1 << 9),
SI476X_RDSREP = (1 << 10),
SI476X_RSQREP = (1 << 11),
};
enum si476x_rdsint_sources {
SI476X_RDSTPPTY = (1 << 4),
SI476X_RDSPI = (1 << 3),
SI476X_RDSSYNC = (1 << 1),
SI476X_RDSRECV = (1 << 0),
};
enum si476x_status_response_bits {
SI476X_CTS = (1 << 7),
SI476X_ERR = (1 << 6),
/* Status response for WB receiver */
SI476X_WB_ASQ_INT = (1 << 4),
SI476X_RSQ_INT = (1 << 3),
/* Status response for FM receiver */
SI476X_FM_RDS_INT = (1 << 2),
SI476X_ACF_INT = (1 << 1),
SI476X_STC_INT = (1 << 0),
};
/* -------------------- si476x-prop.c ----------------------- */
enum si476x_common_receiver_properties {
SI476X_PROP_INT_CTL_ENABLE = 0x0000,
SI476X_PROP_DIGITAL_IO_INPUT_SAMPLE_RATE = 0x0200,
SI476X_PROP_DIGITAL_IO_INPUT_FORMAT = 0x0201,
SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100,
SI476X_PROP_SEEK_BAND_TOP = 0x1101,
SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102,
SI476X_PROP_VALID_MAX_TUNE_ERROR = 0x2000,
SI476X_PROP_VALID_SNR_THRESHOLD = 0x2003,
SI476X_PROP_VALID_RSSI_THRESHOLD = 0x2004,
};
enum si476x_am_receiver_properties {
SI476X_PROP_AUDIO_PWR_LINE_FILTER = 0x0303,
};
enum si476x_fm_receiver_properties {
SI476X_PROP_AUDIO_DEEMPHASIS = 0x0302,
SI476X_PROP_FM_RDS_INTERRUPT_SOURCE = 0x4000,
SI476X_PROP_FM_RDS_INTERRUPT_FIFO_COUNT = 0x4001,
SI476X_PROP_FM_RDS_CONFIG = 0x4002,
};
enum si476x_prop_audio_pwr_line_filter_bits {
SI476X_PROP_PWR_HARMONICS_MASK = 0x001f,
SI476X_PROP_PWR_GRID_MASK = 0x0100,
SI476X_PROP_PWR_ENABLE_MASK = 0x0200,
SI476X_PROP_PWR_GRID_50HZ = 0x0000,
SI476X_PROP_PWR_GRID_60HZ = 0x0100,
};
enum si476x_prop_fm_rds_config_bits {
SI476X_PROP_RDSEN_MASK = 0x1,
SI476X_PROP_RDSEN = 0x1,
};
struct regmap *devm_regmap_init_si476x(struct si476x_core *);
#endif /* SI476X_CORE_H */

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/*
* include/media/si476x-platform.h -- Platform data specific definitions
*
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef __SI476X_PLATFORM_H__
#define __SI476X_PLATFORM_H__
/* It is possible to select one of the four adresses using pins A0
* and A1 on SI476x */
#define SI476X_I2C_ADDR_1 0x60
#define SI476X_I2C_ADDR_2 0x61
#define SI476X_I2C_ADDR_3 0x62
#define SI476X_I2C_ADDR_4 0x63
enum si476x_iqclk_config {
SI476X_IQCLK_NOOP = 0,
SI476X_IQCLK_TRISTATE = 1,
SI476X_IQCLK_IQ = 21,
};
enum si476x_iqfs_config {
SI476X_IQFS_NOOP = 0,
SI476X_IQFS_TRISTATE = 1,
SI476X_IQFS_IQ = 21,
};
enum si476x_iout_config {
SI476X_IOUT_NOOP = 0,
SI476X_IOUT_TRISTATE = 1,
SI476X_IOUT_OUTPUT = 22,
};
enum si476x_qout_config {
SI476X_QOUT_NOOP = 0,
SI476X_QOUT_TRISTATE = 1,
SI476X_QOUT_OUTPUT = 22,
};
enum si476x_dclk_config {
SI476X_DCLK_NOOP = 0,
SI476X_DCLK_TRISTATE = 1,
SI476X_DCLK_DAUDIO = 10,
};
enum si476x_dfs_config {
SI476X_DFS_NOOP = 0,
SI476X_DFS_TRISTATE = 1,
SI476X_DFS_DAUDIO = 10,
};
enum si476x_dout_config {
SI476X_DOUT_NOOP = 0,
SI476X_DOUT_TRISTATE = 1,
SI476X_DOUT_I2S_OUTPUT = 12,
SI476X_DOUT_I2S_INPUT = 13,
};
enum si476x_xout_config {
SI476X_XOUT_NOOP = 0,
SI476X_XOUT_TRISTATE = 1,
SI476X_XOUT_I2S_INPUT = 13,
SI476X_XOUT_MODE_SELECT = 23,
};
enum si476x_icin_config {
SI476X_ICIN_NOOP = 0,
SI476X_ICIN_TRISTATE = 1,
SI476X_ICIN_GPO1_HIGH = 2,
SI476X_ICIN_GPO1_LOW = 3,
SI476X_ICIN_IC_LINK = 30,
};
enum si476x_icip_config {
SI476X_ICIP_NOOP = 0,
SI476X_ICIP_TRISTATE = 1,
SI476X_ICIP_GPO2_HIGH = 2,
SI476X_ICIP_GPO2_LOW = 3,
SI476X_ICIP_IC_LINK = 30,
};
enum si476x_icon_config {
SI476X_ICON_NOOP = 0,
SI476X_ICON_TRISTATE = 1,
SI476X_ICON_I2S = 10,
SI476X_ICON_IC_LINK = 30,
};
enum si476x_icop_config {
SI476X_ICOP_NOOP = 0,
SI476X_ICOP_TRISTATE = 1,
SI476X_ICOP_I2S = 10,
SI476X_ICOP_IC_LINK = 30,
};
enum si476x_lrout_config {
SI476X_LROUT_NOOP = 0,
SI476X_LROUT_TRISTATE = 1,
SI476X_LROUT_AUDIO = 2,
SI476X_LROUT_MPX = 3,
};
enum si476x_intb_config {
SI476X_INTB_NOOP = 0,
SI476X_INTB_TRISTATE = 1,
SI476X_INTB_DAUDIO = 10,
SI476X_INTB_IRQ = 40,
};
enum si476x_a1_config {
SI476X_A1_NOOP = 0,
SI476X_A1_TRISTATE = 1,
SI476X_A1_IRQ = 40,
};
struct si476x_pinmux {
enum si476x_dclk_config dclk;
enum si476x_dfs_config dfs;
enum si476x_dout_config dout;
enum si476x_xout_config xout;
enum si476x_iqclk_config iqclk;
enum si476x_iqfs_config iqfs;
enum si476x_iout_config iout;
enum si476x_qout_config qout;
enum si476x_icin_config icin;
enum si476x_icip_config icip;
enum si476x_icon_config icon;
enum si476x_icop_config icop;
enum si476x_lrout_config lrout;
enum si476x_intb_config intb;
enum si476x_a1_config a1;
};
enum si476x_ibias6x {
SI476X_IBIAS6X_OTHER = 0,
SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK = 1,
};
enum si476x_xstart {
SI476X_XSTART_MULTIPLE_TUNER = 0x11,
SI476X_XSTART_NORMAL = 0x77,
};
enum si476x_freq {
SI476X_FREQ_4_MHZ = 0,
SI476X_FREQ_37P209375_MHZ = 1,
SI476X_FREQ_36P4_MHZ = 2,
SI476X_FREQ_37P8_MHZ = 3,
};
enum si476x_xmode {
SI476X_XMODE_CRYSTAL_RCVR1 = 1,
SI476X_XMODE_EXT_CLOCK = 2,
SI476X_XMODE_CRYSTAL_RCVR2_3 = 3,
};
enum si476x_xbiashc {
SI476X_XBIASHC_SINGLE_RECEIVER = 0,
SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
};
enum si476x_xbias {
SI476X_XBIAS_RCVR2_3 = 0,
SI476X_XBIAS_4MHZ_RCVR1 = 3,
SI476X_XBIAS_RCVR1 = 7,
};
enum si476x_func {
SI476X_FUNC_BOOTLOADER = 0,
SI476X_FUNC_FM_RECEIVER = 1,
SI476X_FUNC_AM_RECEIVER = 2,
SI476X_FUNC_WB_RECEIVER = 3,
};
/**
* @xcload: Selects the amount of additional on-chip capacitance to
* be connected between XTAL1 and gnd and between XTAL2 and
* GND. One half of the capacitance value shown here is the
* additional load capacitance presented to the xtal. The
* minimum step size is 0.277 pF. Recommended value is 0x28
* but it will be layout dependent. Range is 0–0x3F i.e.
* (0–16.33 pF)
* @ctsien: enable CTSINT(interrupt request when CTS condition
* arises) when set
* @intsel: when set A1 pin becomes the interrupt pin; otherwise,
* INTB is the interrupt pin
* @func: selects the boot function of the device. I.e.
* SI476X_BOOTLOADER - Boot loader
* SI476X_FM_RECEIVER - FM receiver
* SI476X_AM_RECEIVER - AM receiver
* SI476X_WB_RECEIVER - Weatherband receiver
* @freq: oscillator's crystal frequency:
* SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
* SI476X_XTAL_36P4_MHZ - 36.4 Mhz
* SI476X_XTAL_37P8_MHZ - 37.8 Mhz
*/
struct si476x_power_up_args {
enum si476x_ibias6x ibias6x;
enum si476x_xstart xstart;
u8 xcload;
bool fastboot;
enum si476x_xbiashc xbiashc;
enum si476x_xbias xbias;
enum si476x_func func;
enum si476x_freq freq;
enum si476x_xmode xmode;
};
/**
* enum si476x_phase_diversity_mode - possbile phase diversity modes
* for SI4764/5/6/7 chips.
*
* @SI476X_PHDIV_DISABLED: Phase diversity feature is
* disabled.
* @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
* in combination with a
* secondary one.
* @SI476X_PHDIV_PRIMARY_ANTENNA: Tuner works as a primary tuner
* using only its own antenna.
* @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
* usning seconary tuner's antenna.
* @SI476X_PHDIV_SECONDARY_COMBINING: Tuner works as a secondary
* tuner in combination with the
* primary one.
*/
enum si476x_phase_diversity_mode {
SI476X_PHDIV_DISABLED = 0,
SI476X_PHDIV_PRIMARY_COMBINING = 1,
SI476X_PHDIV_PRIMARY_ANTENNA = 2,
SI476X_PHDIV_SECONDARY_ANTENNA = 3,
SI476X_PHDIV_SECONDARY_COMBINING = 5,
};
/*
* Platform dependent definition
*/
struct si476x_platform_data {
int gpio_reset; /* < 0 if not used */
struct si476x_power_up_args power_up_parameters;
enum si476x_phase_diversity_mode diversity_mode;
struct si476x_pinmux pinmux;
};
#endif /* __SI476X_PLATFORM_H__ */

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/*
* include/media/si476x-platform.h -- Definitions of the data formats
* returned by debugfs hooks
*
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef __SI476X_REPORTS_H__
#define __SI476X_REPORTS_H__
/**
* struct si476x_rsq_status - structure containing received signal
* quality
* @multhint: Multipath Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_MULTIPATH_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_MULTIPATH_HIGH_THRESHOLD
* @multlint: Multipath Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_MULTIPATH_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_MULTIPATH_LOW_THRESHOLD
* @snrhint: SNR Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_SNR_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_SNR_HIGH_THRESHOLD
* @snrlint: SNR Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_SNR_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_SNR_LOW_THRESHOLD
* @rssihint: RSSI Detect High.
* true - Indicatedes that the value is below
* FM_RSQ_RSSI_HIGH_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_RSSI_HIGH_THRESHOLD
* @rssilint: RSSI Detect Low.
* true - Indicatedes that the value is below
* FM_RSQ_RSSI_LOW_THRESHOLD
* false - Indicatedes that the value is above
* FM_RSQ_RSSI_LOW_THRESHOLD
* @bltf: Band Limit.
* Set if seek command hits the band limit or wrapped to
* the original frequency.
* @snr_ready: SNR measurement in progress.
* @rssiready: RSSI measurement in progress.
* @afcrl: Set if FREQOFF >= MAX_TUNE_ERROR
* @valid: Set if the channel is valid
* rssi < FM_VALID_RSSI_THRESHOLD
* snr < FM_VALID_SNR_THRESHOLD
* tune_error < FM_VALID_MAX_TUNE_ERROR
* @readfreq: Current tuned frequency.
* @freqoff: Signed frequency offset.
* @rssi: Received Signal Strength Indicator(dBuV).
* @snr: RF SNR Indicator(dB).
* @lassi:
* @hassi: Low/High side Adjacent(100 kHz) Channel Strength Indicator
* @mult: Multipath indicator
* @dev: Who knows? But values may vary.
* @readantcap: Antenna tuning capacity value.
* @assi: Adjacent Channel(+/- 200kHz) Strength Indicator
* @usn: Ultrasonic Noise Inticator in -DBFS
*/
struct si476x_rsq_status_report {
__u8 multhint, multlint;
__u8 snrhint, snrlint;
__u8 rssihint, rssilint;
__u8 bltf;
__u8 snr_ready;
__u8 rssiready;
__u8 injside;
__u8 afcrl;
__u8 valid;
__u16 readfreq;
__s8 freqoff;
__s8 rssi;
__s8 snr;
__s8 issi;
__s8 lassi, hassi;
__s8 mult;
__u8 dev;
__u16 readantcap;
__s8 assi;
__s8 usn;
__u8 pilotdev;
__u8 rdsdev;
__u8 assidev;
__u8 strongdev;
__u16 rdspi;
} __packed;
/**
* si476x_acf_status_report - ACF report results
*
* @blend_int: If set, indicates that stereo separation has crossed
* below the blend threshold as set by FM_ACF_BLEND_THRESHOLD
* @hblend_int: If set, indicates that HiBlend cutoff frequency is
* lower than threshold as set by FM_ACF_HBLEND_THRESHOLD
* @hicut_int: If set, indicates that HiCut cutoff frequency is lower
* than the threshold set by ACF_
*/
struct si476x_acf_status_report {
__u8 blend_int;
__u8 hblend_int;
__u8 hicut_int;
__u8 chbw_int;
__u8 softmute_int;
__u8 smute;
__u8 smattn;
__u8 chbw;
__u8 hicut;
__u8 hiblend;
__u8 pilot;
__u8 stblend;
} __packed;
enum si476x_fmagc {
SI476X_FMAGC_10K_OHM = 0,
SI476X_FMAGC_800_OHM = 1,
SI476X_FMAGC_400_OHM = 2,
SI476X_FMAGC_200_OHM = 4,
SI476X_FMAGC_100_OHM = 8,
SI476X_FMAGC_50_OHM = 16,
SI476X_FMAGC_25_OHM = 32,
SI476X_FMAGC_12P5_OHM = 64,
SI476X_FMAGC_6P25_OHM = 128,
};
struct si476x_agc_status_report {
__u8 mxhi;
__u8 mxlo;
__u8 lnahi;
__u8 lnalo;
__u8 fmagc1;
__u8 fmagc2;
__u8 pgagain;
__u8 fmwblang;
} __packed;
struct si476x_rds_blockcount_report {
__u16 expected;
__u16 received;
__u16 uncorrectable;
} __packed;
#endif /* __SI476X_REPORTS_H__ */

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/*
* SMSC ECE1099
*
* Copyright 2012 Texas Instruments Inc.
*
* Author: Sourav Poddar <sourav.poddar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SMSC_H
#define __LINUX_MFD_SMSC_H
#include <linux/regmap.h>
#define SMSC_ID_ECE1099 1
#define SMSC_NUM_CLIENTS 2
#define SMSC_BASE_ADDR 0x38
#define OMAP_GPIO_SMSC_IRQ 151
#define SMSC_MAXGPIO 32
#define SMSC_BANK(offs) ((offs) >> 3)
#define SMSC_BIT(offs) (1u << ((offs) & 0x7))
struct smsc {
struct device *dev;
struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS];
struct regmap *regmap;
int clk;
/* Stored chip id */
int id;
};
struct smsc_gpio;
struct smsc_keypad;
static inline int smsc_read(struct device *child, unsigned int reg,
unsigned int *dest)
{
struct smsc *smsc = dev_get_drvdata(child->parent);
return regmap_read(smsc->regmap, reg, dest);
}
static inline int smsc_write(struct device *child, unsigned int reg,
unsigned int value)
{
struct smsc *smsc = dev_get_drvdata(child->parent);
return regmap_write(smsc->regmap, reg, value);
}
/* Registers for SMSC */
#define SMSC_RESET 0xF5
#define SMSC_GRP_INT 0xF9
#define SMSC_CLK_CTRL 0xFA
#define SMSC_WKUP_CTRL 0xFB
#define SMSC_DEV_ID 0xFC
#define SMSC_DEV_REV 0xFD
#define SMSC_VEN_ID_L 0xFE
#define SMSC_VEN_ID_H 0xFF
/* CLK VALUE */
#define SMSC_CLK_VALUE 0x13
/* Registers for function GPIO INPUT */
#define SMSC_GPIO_DATA_IN_START 0x00
/* Registers for function GPIO OUPUT */
#define SMSC_GPIO_DATA_OUT_START 0x05
/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/
#define SMSC_GPIO_INPUT_LOW 0x01
#define SMSC_GPIO_INPUT_RISING 0x09
#define SMSC_GPIO_INPUT_FALLING 0x11
#define SMSC_GPIO_INPUT_BOTH_EDGE 0x19
#define SMSC_GPIO_OUTPUT_PP 0x21
#define SMSC_GPIO_OUTPUT_OP 0x31
#define GRP_INT_STAT 0xf9
#define SMSC_GPI_INT 0x0f
#define SMSC_CFG_START 0x0A
/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/
#define SMSC_GPIO_INT_STAT_START 0x32
/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/
#define SMSC_GPIO_INT_MASK_START 0x37
/* Registers for SMSC function KEYPAD*/
#define SMSC_KP_OUT 0x40
#define SMSC_KP_IN 0x41
#define SMSC_KP_INT_STAT 0x42
#define SMSC_KP_INT_MASK 0x43
/* Definitions for keypad */
#define SMSC_KP_KSO 0x70
#define SMSC_KP_KSI 0x51
#define SMSC_KSO_ALL_LOW 0x20
#define SMSC_KP_SET_LOW_PWR 0x0B
#define SMSC_KP_SET_HIGH 0xFF
#define SMSC_KSO_EVAL 0x00
#endif /* __LINUX_MFD_SMSC_H */

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include/linux/mfd/sta2x11-mfd.h Normal file
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/*
* Copyright (c) 2009-2011 Wind River Systems, Inc.
* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
* functions in one PCI endpoint functions. This driver simply
* registers the platform devices in this iomemregion and exports a few
* functions to access common registers
*/
#ifndef __STA2X11_MFD_H
#define __STA2X11_MFD_H
#include <linux/types.h>
#include <linux/pci.h>
enum sta2x11_mfd_plat_dev {
sta2x11_sctl = 0,
sta2x11_gpio,
sta2x11_scr,
sta2x11_time,
sta2x11_apbreg,
sta2x11_apb_soc_regs,
sta2x11_vic,
sta2x11_n_mfd_plat_devs,
};
#define STA2X11_MFD_SCTL_NAME "sta2x11-sctl"
#define STA2X11_MFD_GPIO_NAME "sta2x11-gpio"
#define STA2X11_MFD_SCR_NAME "sta2x11-scr"
#define STA2X11_MFD_TIME_NAME "sta2x11-time"
#define STA2X11_MFD_APBREG_NAME "sta2x11-apbreg"
#define STA2X11_MFD_APB_SOC_REGS_NAME "sta2x11-apb-soc-regs"
#define STA2X11_MFD_VIC_NAME "sta2x11-vic"
extern u32
__sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
/*
* The MFD PCI block includes the GPIO peripherals and other register blocks.
* For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
*/
#define GSTA_GPIO_PER_BLOCK 32
#define GSTA_NR_BLOCKS 4
#define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
struct sta2x11_gpio_pdata {
unsigned pinconfig[GSTA_NR_GPIO];
};
/* Macros below lifted from sh_pfc.h, with minor differences */
#define PINMUX_TYPE_NONE 0
#define PINMUX_TYPE_FUNCTION 1
#define PINMUX_TYPE_OUTPUT_LOW 2
#define PINMUX_TYPE_OUTPUT_HIGH 3
#define PINMUX_TYPE_INPUT 4
#define PINMUX_TYPE_INPUT_PULLUP 5
#define PINMUX_TYPE_INPUT_PULLDOWN 6
/* Give names to GPIO pins, like PXA does, taken from the manual */
#define STA2X11_GPIO0 0
#define STA2X11_GPIO1 1
#define STA2X11_GPIO2 2
#define STA2X11_GPIO3 3
#define STA2X11_GPIO4 4
#define STA2X11_GPIO5 5
#define STA2X11_GPIO6 6
#define STA2X11_GPIO7 7
#define STA2X11_GPIO8_RGBOUT_RED7 8
#define STA2X11_GPIO9_RGBOUT_RED6 9
#define STA2X11_GPIO10_RGBOUT_RED5 10
#define STA2X11_GPIO11_RGBOUT_RED4 11
#define STA2X11_GPIO12_RGBOUT_RED3 12
#define STA2X11_GPIO13_RGBOUT_RED2 13
#define STA2X11_GPIO14_RGBOUT_RED1 14
#define STA2X11_GPIO15_RGBOUT_RED0 15
#define STA2X11_GPIO16_RGBOUT_GREEN7 16
#define STA2X11_GPIO17_RGBOUT_GREEN6 17
#define STA2X11_GPIO18_RGBOUT_GREEN5 18
#define STA2X11_GPIO19_RGBOUT_GREEN4 19
#define STA2X11_GPIO20_RGBOUT_GREEN3 20
#define STA2X11_GPIO21_RGBOUT_GREEN2 21
#define STA2X11_GPIO22_RGBOUT_GREEN1 22
#define STA2X11_GPIO23_RGBOUT_GREEN0 23
#define STA2X11_GPIO24_RGBOUT_BLUE7 24
#define STA2X11_GPIO25_RGBOUT_BLUE6 25
#define STA2X11_GPIO26_RGBOUT_BLUE5 26
#define STA2X11_GPIO27_RGBOUT_BLUE4 27
#define STA2X11_GPIO28_RGBOUT_BLUE3 28
#define STA2X11_GPIO29_RGBOUT_BLUE2 29
#define STA2X11_GPIO30_RGBOUT_BLUE1 30
#define STA2X11_GPIO31_RGBOUT_BLUE0 31
#define STA2X11_GPIO32_RGBOUT_VSYNCH 32
#define STA2X11_GPIO33_RGBOUT_HSYNCH 33
#define STA2X11_GPIO34_RGBOUT_DEN 34
#define STA2X11_GPIO35_ETH_CRS_DV 35
#define STA2X11_GPIO36_ETH_TXD1 36
#define STA2X11_GPIO37_ETH_TXD0 37
#define STA2X11_GPIO38_ETH_TX_EN 38
#define STA2X11_GPIO39_MDIO 39
#define STA2X11_GPIO40_ETH_REF_CLK 40
#define STA2X11_GPIO41_ETH_RXD1 41
#define STA2X11_GPIO42_ETH_RXD0 42
#define STA2X11_GPIO43_MDC 43
#define STA2X11_GPIO44_CAN_TX 44
#define STA2X11_GPIO45_CAN_RX 45
#define STA2X11_GPIO46_MLB_DAT 46
#define STA2X11_GPIO47_MLB_SIG 47
#define STA2X11_GPIO48_SPI0_CLK 48
#define STA2X11_GPIO49_SPI0_TXD 49
#define STA2X11_GPIO50_SPI0_RXD 50
#define STA2X11_GPIO51_SPI0_FRM 51
#define STA2X11_GPIO52_SPI1_CLK 52
#define STA2X11_GPIO53_SPI1_TXD 53
#define STA2X11_GPIO54_SPI1_RXD 54
#define STA2X11_GPIO55_SPI1_FRM 55
#define STA2X11_GPIO56_SPI2_CLK 56
#define STA2X11_GPIO57_SPI2_TXD 57
#define STA2X11_GPIO58_SPI2_RXD 58
#define STA2X11_GPIO59_SPI2_FRM 59
#define STA2X11_GPIO60_I2C0_SCL 60
#define STA2X11_GPIO61_I2C0_SDA 61
#define STA2X11_GPIO62_I2C1_SCL 62
#define STA2X11_GPIO63_I2C1_SDA 63
#define STA2X11_GPIO64_I2C2_SCL 64
#define STA2X11_GPIO65_I2C2_SDA 65
#define STA2X11_GPIO66_I2C3_SCL 66
#define STA2X11_GPIO67_I2C3_SDA 67
#define STA2X11_GPIO68_MSP0_RCK 68
#define STA2X11_GPIO69_MSP0_RXD 69
#define STA2X11_GPIO70_MSP0_RFS 70
#define STA2X11_GPIO71_MSP0_TCK 71
#define STA2X11_GPIO72_MSP0_TXD 72
#define STA2X11_GPIO73_MSP0_TFS 73
#define STA2X11_GPIO74_MSP0_SCK 74
#define STA2X11_GPIO75_MSP1_CK 75
#define STA2X11_GPIO76_MSP1_RXD 76
#define STA2X11_GPIO77_MSP1_FS 77
#define STA2X11_GPIO78_MSP1_TXD 78
#define STA2X11_GPIO79_MSP2_CK 79
#define STA2X11_GPIO80_MSP2_RXD 80
#define STA2X11_GPIO81_MSP2_FS 81
#define STA2X11_GPIO82_MSP2_TXD 82
#define STA2X11_GPIO83_MSP3_CK 83
#define STA2X11_GPIO84_MSP3_RXD 84
#define STA2X11_GPIO85_MSP3_FS 85
#define STA2X11_GPIO86_MSP3_TXD 86
#define STA2X11_GPIO87_MSP4_CK 87
#define STA2X11_GPIO88_MSP4_RXD 88
#define STA2X11_GPIO89_MSP4_FS 89
#define STA2X11_GPIO90_MSP4_TXD 90
#define STA2X11_GPIO91_MSP5_CK 91
#define STA2X11_GPIO92_MSP5_RXD 92
#define STA2X11_GPIO93_MSP5_FS 93
#define STA2X11_GPIO94_MSP5_TXD 94
#define STA2X11_GPIO95_SDIO3_DAT3 95
#define STA2X11_GPIO96_SDIO3_DAT2 96
#define STA2X11_GPIO97_SDIO3_DAT1 97
#define STA2X11_GPIO98_SDIO3_DAT0 98
#define STA2X11_GPIO99_SDIO3_CLK 99
#define STA2X11_GPIO100_SDIO3_CMD 100
#define STA2X11_GPIO101 101
#define STA2X11_GPIO102 102
#define STA2X11_GPIO103 103
#define STA2X11_GPIO104 104
#define STA2X11_GPIO105_SDIO2_DAT3 105
#define STA2X11_GPIO106_SDIO2_DAT2 106
#define STA2X11_GPIO107_SDIO2_DAT1 107
#define STA2X11_GPIO108_SDIO2_DAT0 108
#define STA2X11_GPIO109_SDIO2_CLK 109
#define STA2X11_GPIO110_SDIO2_CMD 110
#define STA2X11_GPIO111 111
#define STA2X11_GPIO112 112
#define STA2X11_GPIO113 113
#define STA2X11_GPIO114 114
#define STA2X11_GPIO115_SDIO1_DAT3 115
#define STA2X11_GPIO116_SDIO1_DAT2 116
#define STA2X11_GPIO117_SDIO1_DAT1 117
#define STA2X11_GPIO118_SDIO1_DAT0 118
#define STA2X11_GPIO119_SDIO1_CLK 119
#define STA2X11_GPIO120_SDIO1_CMD 120
#define STA2X11_GPIO121 121
#define STA2X11_GPIO122 122
#define STA2X11_GPIO123 123
#define STA2X11_GPIO124 124
#define STA2X11_GPIO125_UART2_TXD 125
#define STA2X11_GPIO126_UART2_RXD 126
#define STA2X11_GPIO127_UART3_TXD 127
/*
* The APB bridge has its own registers, needed by our users as well.
* They are accessed with the following read/mask/write function.
*/
static inline u32
sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
{
return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
}
/* CAN and MLB */
#define APBREG_BSR 0x00 /* Bridge Status Reg */
#define APBREG_PAER 0x08 /* Peripherals Address Error Reg */
#define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
#define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
#define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
#define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
#define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
#define APBREG_CAN (1 << 1)
#define APBREG_MLB (1 << 3)
/* SARAC */
#define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */
#define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */
#define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
#define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
#define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
#define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
#define APBREG_SARAC (1 << 2)
/*
* The system controller has its own registers. Some of these are accessed
* by out users as well, using the following read/mask/write/function
*/
static inline
u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
{
return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
}
#define SCTL_SCCTL 0x00 /* System controller control register */
#define SCTL_ARMCFG 0x04 /* ARM configuration register */
#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
#define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1)
#define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3)
#define SCTL_SCPLLCTL_STRB_BYPASS BIT(6)
#define SCTL_SCPLLCTL_STRB_INPUT BIT(8)
#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff
#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT 10
#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK 7
#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT 21
#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK 7
#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT 18
#define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03
#define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT 4
#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
#define SCTL_SCRESFRACT_MASK 0x0000ffff
#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
#define SCTL_SCGRST 0x28 /* Peripheral global reset */
#define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */
#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
#define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */
#define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */
#define SCTL_SCINTREN 0x44 /* Interrupt enable */
#define SCTL_SCRISR 0x48 /* RAW interrupt status */
#define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
#define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
#define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */
#define SCTL_SCRSTSTA 0x58 /* Reset status register */
#define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0)
#define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
#define SCTL_SCRESCTRL1_USB_HRST (1 << 2)
#define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3)
#define SCTL_SCRESCTRL1_SATAII (1 << 4)
#define SCTL_SCRESCTRL1_VIP (1 << 5)
#define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6)
#define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7)
#define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8)
#define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9)
#define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10)
#define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11)
#define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12)
#define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13)
#define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14)
#define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15)
#define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16)
#define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17)
#define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18)
#define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19)
#define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20)
#define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21)
#define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22)
#define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23)
#define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24)
#define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25)
#define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26)
#define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27)
#define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
#define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29)
#define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30)
#define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31)
#define SCTL_SCPEREN0_UART0 (1 << 0)
#define SCTL_SCPEREN0_UART1 (1 << 1)
#define SCTL_SCPEREN0_UART2 (1 << 2)
#define SCTL_SCPEREN0_UART3 (1 << 3)
#define SCTL_SCPEREN0_MSP0 (1 << 4)
#define SCTL_SCPEREN0_MSP1 (1 << 5)
#define SCTL_SCPEREN0_MSP2 (1 << 6)
#define SCTL_SCPEREN0_MSP3 (1 << 7)
#define SCTL_SCPEREN0_MSP4 (1 << 8)
#define SCTL_SCPEREN0_MSP5 (1 << 9)
#define SCTL_SCPEREN0_SPI0 (1 << 10)
#define SCTL_SCPEREN0_SPI1 (1 << 11)
#define SCTL_SCPEREN0_SPI2 (1 << 12)
#define SCTL_SCPEREN0_I2C0 (1 << 13)
#define SCTL_SCPEREN0_I2C1 (1 << 14)
#define SCTL_SCPEREN0_I2C2 (1 << 15)
#define SCTL_SCPEREN0_I2C3 (1 << 16)
#define SCTL_SCPEREN0_SVDO_LVDS (1 << 17)
#define SCTL_SCPEREN0_USB_HOST (1 << 18)
#define SCTL_SCPEREN0_USB_OTG (1 << 19)
#define SCTL_SCPEREN0_MCI0 (1 << 20)
#define SCTL_SCPEREN0_MCI1 (1 << 21)
#define SCTL_SCPEREN0_MCI2 (1 << 22)
#define SCTL_SCPEREN0_MCI3 (1 << 23)
#define SCTL_SCPEREN0_SATA (1 << 24)
#define SCTL_SCPEREN0_ETHERNET (1 << 25)
#define SCTL_SCPEREN0_VIC (1 << 26)
#define SCTL_SCPEREN0_DMA_AUDIO (1 << 27)
#define SCTL_SCPEREN0_DMA_SOC (1 << 28)
#define SCTL_SCPEREN0_RAM (1 << 29)
#define SCTL_SCPEREN0_VIP (1 << 30)
#define SCTL_SCPEREN0_ARM (1 << 31)
#define SCTL_SCPEREN1_UART0 (1 << 0)
#define SCTL_SCPEREN1_UART1 (1 << 1)
#define SCTL_SCPEREN1_UART2 (1 << 2)
#define SCTL_SCPEREN1_UART3 (1 << 3)
#define SCTL_SCPEREN1_MSP0 (1 << 4)
#define SCTL_SCPEREN1_MSP1 (1 << 5)
#define SCTL_SCPEREN1_MSP2 (1 << 6)
#define SCTL_SCPEREN1_MSP3 (1 << 7)
#define SCTL_SCPEREN1_MSP4 (1 << 8)
#define SCTL_SCPEREN1_MSP5 (1 << 9)
#define SCTL_SCPEREN1_SPI0 (1 << 10)
#define SCTL_SCPEREN1_SPI1 (1 << 11)
#define SCTL_SCPEREN1_SPI2 (1 << 12)
#define SCTL_SCPEREN1_I2C0 (1 << 13)
#define SCTL_SCPEREN1_I2C1 (1 << 14)
#define SCTL_SCPEREN1_I2C2 (1 << 15)
#define SCTL_SCPEREN1_I2C3 (1 << 16)
#define SCTL_SCPEREN1_USB_PHY (1 << 17)
/*
* APB-SOC registers
*/
static inline
u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
{
return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
}
#define PCIE_EP1_FUNC3_0_INTR_REG 0x000
#define PCIE_EP1_FUNC7_4_INTR_REG 0x004
#define PCIE_EP2_FUNC3_0_INTR_REG 0x008
#define PCIE_EP2_FUNC7_4_INTR_REG 0x00c
#define PCIE_EP3_FUNC3_0_INTR_REG 0x010
#define PCIE_EP3_FUNC7_4_INTR_REG 0x014
#define PCIE_EP4_FUNC3_0_INTR_REG 0x018
#define PCIE_EP4_FUNC7_4_INTR_REG 0x01c
#define PCIE_INTR_ENABLE0_REG 0x020
#define PCIE_INTR_ENABLE1_REG 0x024
#define PCIE_EP1_FUNC_TC_REG 0x028
#define PCIE_EP2_FUNC_TC_REG 0x02c
#define PCIE_EP3_FUNC_TC_REG 0x030
#define PCIE_EP4_FUNC_TC_REG 0x034
#define PCIE_EP1_FUNC_F_REG 0x038
#define PCIE_EP2_FUNC_F_REG 0x03c
#define PCIE_EP3_FUNC_F_REG 0x040
#define PCIE_EP4_FUNC_F_REG 0x044
#define PCIE_PAB_AMBA_SW_RST_REG 0x048
#define PCIE_PM_STATUS_0_PORT_0_4 0x04c
#define PCIE_PM_STATUS_7_0_EP1 0x050
#define PCIE_PM_STATUS_7_0_EP2 0x054
#define PCIE_PM_STATUS_7_0_EP3 0x058
#define PCIE_PM_STATUS_7_0_EP4 0x05c
#define PCIE_DEV_ID_0_EP1_REG 0x060
#define PCIE_CC_REV_ID_0_EP1_REG 0x064
#define PCIE_DEV_ID_1_EP1_REG 0x068
#define PCIE_CC_REV_ID_1_EP1_REG 0x06c
#define PCIE_DEV_ID_2_EP1_REG 0x070
#define PCIE_CC_REV_ID_2_EP1_REG 0x074
#define PCIE_DEV_ID_3_EP1_REG 0x078
#define PCIE_CC_REV_ID_3_EP1_REG 0x07c
#define PCIE_DEV_ID_4_EP1_REG 0x080
#define PCIE_CC_REV_ID_4_EP1_REG 0x084
#define PCIE_DEV_ID_5_EP1_REG 0x088
#define PCIE_CC_REV_ID_5_EP1_REG 0x08c
#define PCIE_DEV_ID_6_EP1_REG 0x090
#define PCIE_CC_REV_ID_6_EP1_REG 0x094
#define PCIE_DEV_ID_7_EP1_REG 0x098
#define PCIE_CC_REV_ID_7_EP1_REG 0x09c
#define PCIE_DEV_ID_0_EP2_REG 0x0a0
#define PCIE_CC_REV_ID_0_EP2_REG 0x0a4
#define PCIE_DEV_ID_1_EP2_REG 0x0a8
#define PCIE_CC_REV_ID_1_EP2_REG 0x0ac
#define PCIE_DEV_ID_2_EP2_REG 0x0b0
#define PCIE_CC_REV_ID_2_EP2_REG 0x0b4
#define PCIE_DEV_ID_3_EP2_REG 0x0b8
#define PCIE_CC_REV_ID_3_EP2_REG 0x0bc
#define PCIE_DEV_ID_4_EP2_REG 0x0c0
#define PCIE_CC_REV_ID_4_EP2_REG 0x0c4
#define PCIE_DEV_ID_5_EP2_REG 0x0c8
#define PCIE_CC_REV_ID_5_EP2_REG 0x0cc
#define PCIE_DEV_ID_6_EP2_REG 0x0d0
#define PCIE_CC_REV_ID_6_EP2_REG 0x0d4
#define PCIE_DEV_ID_7_EP2_REG 0x0d8
#define PCIE_CC_REV_ID_7_EP2_REG 0x0dC
#define PCIE_DEV_ID_0_EP3_REG 0x0e0
#define PCIE_CC_REV_ID_0_EP3_REG 0x0e4
#define PCIE_DEV_ID_1_EP3_REG 0x0e8
#define PCIE_CC_REV_ID_1_EP3_REG 0x0ec
#define PCIE_DEV_ID_2_EP3_REG 0x0f0
#define PCIE_CC_REV_ID_2_EP3_REG 0x0f4
#define PCIE_DEV_ID_3_EP3_REG 0x0f8
#define PCIE_CC_REV_ID_3_EP3_REG 0x0fc
#define PCIE_DEV_ID_4_EP3_REG 0x100
#define PCIE_CC_REV_ID_4_EP3_REG 0x104
#define PCIE_DEV_ID_5_EP3_REG 0x108
#define PCIE_CC_REV_ID_5_EP3_REG 0x10c
#define PCIE_DEV_ID_6_EP3_REG 0x110
#define PCIE_CC_REV_ID_6_EP3_REG 0x114
#define PCIE_DEV_ID_7_EP3_REG 0x118
#define PCIE_CC_REV_ID_7_EP3_REG 0x11c
#define PCIE_DEV_ID_0_EP4_REG 0x120
#define PCIE_CC_REV_ID_0_EP4_REG 0x124
#define PCIE_DEV_ID_1_EP4_REG 0x128
#define PCIE_CC_REV_ID_1_EP4_REG 0x12c
#define PCIE_DEV_ID_2_EP4_REG 0x130
#define PCIE_CC_REV_ID_2_EP4_REG 0x134
#define PCIE_DEV_ID_3_EP4_REG 0x138
#define PCIE_CC_REV_ID_3_EP4_REG 0x13c
#define PCIE_DEV_ID_4_EP4_REG 0x140
#define PCIE_CC_REV_ID_4_EP4_REG 0x144
#define PCIE_DEV_ID_5_EP4_REG 0x148
#define PCIE_CC_REV_ID_5_EP4_REG 0x14c
#define PCIE_DEV_ID_6_EP4_REG 0x150
#define PCIE_CC_REV_ID_6_EP4_REG 0x154
#define PCIE_DEV_ID_7_EP4_REG 0x158
#define PCIE_CC_REV_ID_7_EP4_REG 0x15c
#define PCIE_SUBSYS_VEN_ID_REG 0x160
#define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164
#define PCIE_MIPHYP_SSC_EN_REG 0x168
#define PCIE_MIPHYP_ADDR_REG 0x16c
#define PCIE_L1_ASPM_READY_REG 0x170
#define PCIE_EXT_CFG_RDY_REG 0x174
#define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
#define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
#define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
#define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
#define DMA_IP_CTRL_REG 0x324
#define DISP_BRIDGE_PU_PD_CTRL_REG 0x328
#define VIP_PU_PD_CTRL_REG 0x32c
#define USB_MLB_PU_PD_CTRL_REG 0x330
#define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334
#define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338
#define UART_PU_PD_CTRL_REG 0x33c
#define ARM_Lock 0x340
#define SYS_IO_CHAR_REG1 0x344
#define SYS_IO_CHAR_REG2 0x348
#define SATA_CORE_ID_REG 0x34c
#define SATA_CTRL_REG 0x350
#define I2C_HSFIX_MISC_REG 0x354
#define SPARE2_RESERVED 0x358
#define SPARE3_RESERVED 0x35c
#define MASTER_LOCK_REG 0x368
#define SYSTEM_CONFIG_STATUS_REG 0x36c
#define MSP_CLK_CTRL_REG 0x39c
#define COMPENSATION_REG1 0x3c4
#define COMPENSATION_REG2 0x3c8
#define COMPENSATION_REG3 0x3cc
#define TEST_CTL_REG 0x3d0
/*
* SECR (OTP) registers
*/
#define STA2X11_SECR_CR 0x00
#define STA2X11_SECR_FVR0 0x10
#define STA2X11_SECR_FVR1 0x14
extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev,
enum sta2x11_mfd_plat_dev index,
void __iomem **regs,
spinlock_t **lock);
#endif /* __STA2X11_MFD_H */

228
include/linux/mfd/stmpe.h Normal file
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
*/
#ifndef __LINUX_MFD_STMPE_H
#define __LINUX_MFD_STMPE_H
#include <linux/mutex.h>
struct device;
enum stmpe_block {
STMPE_BLOCK_GPIO = 1 << 0,
STMPE_BLOCK_KEYPAD = 1 << 1,
STMPE_BLOCK_TOUCHSCREEN = 1 << 2,
STMPE_BLOCK_ADC = 1 << 3,
STMPE_BLOCK_PWM = 1 << 4,
STMPE_BLOCK_ROTATOR = 1 << 5,
};
enum stmpe_partnum {
STMPE610,
STMPE801,
STMPE811,
STMPE1601,
STMPE1801,
STMPE2401,
STMPE2403,
STMPE_NBR_PARTS
};
/*
* For registers whose locations differ on variants, the correct address is
* obtained by indexing stmpe->regs with one of the following.
*/
enum {
STMPE_IDX_CHIP_ID,
STMPE_IDX_ICR_LSB,
STMPE_IDX_IER_LSB,
STMPE_IDX_ISR_LSB,
STMPE_IDX_ISR_MSB,
STMPE_IDX_GPMR_LSB,
STMPE_IDX_GPSR_LSB,
STMPE_IDX_GPCR_LSB,
STMPE_IDX_GPDR_LSB,
STMPE_IDX_GPEDR_MSB,
STMPE_IDX_GPRER_LSB,
STMPE_IDX_GPFER_LSB,
STMPE_IDX_GPAFR_U_MSB,
STMPE_IDX_IEGPIOR_LSB,
STMPE_IDX_ISGPIOR_LSB,
STMPE_IDX_ISGPIOR_MSB,
STMPE_IDX_MAX,
};
struct stmpe_variant_info;
struct stmpe_client_info;
/**
* struct stmpe - STMPE MFD structure
* @lock: lock protecting I/O operations
* @irq_lock: IRQ bus lock
* @dev: device, mostly for dev_dbg()
* @irq_domain: IRQ domain
* @client: client - i2c or spi
* @ci: client specific information
* @partnum: part number
* @variant: the detected STMPE model number
* @regs: list of addresses of registers which are at different addresses on
* different variants. Indexed by one of STMPE_IDX_*.
* @irq: irq number for stmpe
* @irq_base: starting IRQ number for internal IRQs
* @num_gpios: number of gpios, differs for variants
* @ier: cache of IER registers for bus_lock
* @oldier: cache of IER registers for bus_lock
* @pdata: platform data
*/
struct stmpe {
struct mutex lock;
struct mutex irq_lock;
struct device *dev;
struct irq_domain *domain;
void *client;
struct stmpe_client_info *ci;
enum stmpe_partnum partnum;
struct stmpe_variant_info *variant;
const u8 *regs;
int irq;
int irq_base;
int num_gpios;
u8 ier[2];
u8 oldier[2];
struct stmpe_platform_data *pdata;
};
extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data);
extern int stmpe_reg_read(struct stmpe *stmpe, u8 reg);
extern int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
u8 *values);
extern int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values);
extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val);
extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins,
enum stmpe_block block);
extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks);
extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks);
struct matrix_keymap_data;
/**
* struct stmpe_keypad_platform_data - STMPE keypad platform data
* @keymap_data: key map table and size
* @debounce_ms: debounce interval, in ms. Maximum is
* %STMPE_KEYPAD_MAX_DEBOUNCE.
* @scan_count: number of key scanning cycles to confirm key data.
* Maximum is %STMPE_KEYPAD_MAX_SCAN_COUNT.
* @no_autorepeat: disable key autorepeat
*/
struct stmpe_keypad_platform_data {
const struct matrix_keymap_data *keymap_data;
unsigned int debounce_ms;
unsigned int scan_count;
bool no_autorepeat;
};
#define STMPE_GPIO_NOREQ_811_TOUCH (0xf0)
/**
* struct stmpe_gpio_platform_data - STMPE GPIO platform data
* @gpio_base: first gpio number assigned. A maximum of
* %STMPE_NR_GPIOS GPIOs will be allocated.
* @norequest_mask: bitmask specifying which GPIOs should _not_ be
* requestable due to different usage (e.g. touch, keypad)
* STMPE_GPIO_NOREQ_* macros can be used here.
* @setup: board specific setup callback.
* @remove: board specific remove callback
*/
struct stmpe_gpio_platform_data {
int gpio_base;
unsigned norequest_mask;
void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
};
/**
* struct stmpe_ts_platform_data - stmpe811 touch screen controller platform
* data
* @sample_time: ADC converstion time in number of clock.
* (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks,
* 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks),
* recommended is 4.
* @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
* @ref_sel: ADC reference source
* (0 -> internal reference, 1 -> external reference)
* @adc_freq: ADC Clock speed
* (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
* @ave_ctrl: Sample average control
* (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
* @touch_det_delay: Touch detect interrupt delay
* (0 -> 10 us, 1 -> 50 us, 2 -> 100 us, 3 -> 500 us,
* 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms)
* recommended is 3
* @settling: Panel driver settling time
* (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 -> 1 ms,
* 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms)
* recommended is 2
* @fraction_z: Length of the fractional part in z
* (fraction_z ([0..7]) = Count of the fractional part)
* recommended is 7
* @i_drive: current limit value of the touchscreen drivers
* (0 -> 20 mA typical 35 mA max, 1 -> 50 mA typical 80 mA max)
*
* */
struct stmpe_ts_platform_data {
u8 sample_time;
u8 mod_12b;
u8 ref_sel;
u8 adc_freq;
u8 ave_ctrl;
u8 touch_det_delay;
u8 settling;
u8 fraction_z;
u8 i_drive;
};
/**
* struct stmpe_platform_data - STMPE platform data
* @id: device id to distinguish between multiple STMPEs on the same board
* @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
* @irq_trigger: IRQ trigger to use for the interrupt to the host
* @autosleep: bool to enable/disable stmpe autosleep
* @autosleep_timeout: inactivity timeout in milliseconds for autosleep
* @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
* %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
* @irq_over_gpio: true if gpio is used to get irq
* @irq_gpio: gpio number over which irq will be requested (significant only if
* irq_over_gpio is true)
* @gpio: GPIO-specific platform data
* @keypad: keypad-specific platform data
* @ts: touchscreen-specific platform data
*/
struct stmpe_platform_data {
int id;
unsigned int blocks;
int irq_base;
unsigned int irq_trigger;
bool autosleep;
bool irq_over_gpio;
int irq_gpio;
int autosleep_timeout;
struct stmpe_gpio_platform_data *gpio;
struct stmpe_keypad_platform_data *keypad;
struct stmpe_ts_platform_data *ts;
};
#define STMPE_NR_INTERNAL_IRQS 9
#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
#define STMPE_NR_GPIOS 24
#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
#endif

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include/linux/mfd/syscon.h Normal file
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/*
* System Control Driver
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __LINUX_MFD_SYSCON_H__
#define __LINUX_MFD_SYSCON_H__
struct device_node;
extern struct regmap *syscon_node_to_regmap(struct device_node *np);
extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s);
extern struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
const char *property);
#endif /* __LINUX_MFD_SYSCON_H__ */

319
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h Normal file
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/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
#define __LINUX_IMX6Q_IOMUXC_GPR_H
#include <linux/bitops.h>
#define IOMUXC_GPR0 0x00
#define IOMUXC_GPR1 0x04
#define IOMUXC_GPR2 0x08
#define IOMUXC_GPR3 0x0c
#define IOMUXC_GPR4 0x10
#define IOMUXC_GPR5 0x14
#define IOMUXC_GPR6 0x18
#define IOMUXC_GPR7 0x1c
#define IOMUXC_GPR8 0x20
#define IOMUXC_GPR9 0x24
#define IOMUXC_GPR10 0x28
#define IOMUXC_GPR11 0x2c
#define IOMUXC_GPR12 0x30
#define IOMUXC_GPR13 0x34
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
#define IMX6Q_GPR1_DPI_OFF BIT(24)
#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
#define IMX6Q_GPR1_PCIE_INT BIT(14)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
#define IMX6Q_GPR1_GINT BIT(12)
#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
#define IMX6Q_GPR1_ACT_CS3 BIT(9)
#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7)
#define IMX6Q_GPR1_ACT_CS2 BIT(6)
#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4)
#define IMX6Q_GPR1_ACT_CS1 BIT(3)
#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1)
#define IMX6Q_GPR1_ACT_CS0 BIT(0)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16)
#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0
#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0
#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0
#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0
#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0
#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0
#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0
#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2)
#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2)
#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2)
#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2)
#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0)
#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0)
#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0)
#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0)
#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29)
#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29)
#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29)
#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21)
#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17)
#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2)
#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8)
#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8
#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21)
#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18)
#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16)
#define IMX6Q_GPR10_DBG_EN BIT(13)
#define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0
#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

34
include/linux/mfd/t7l66xb.h Normal file
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/*
* This file contains the definitions for the T7L66XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_T7L66XB_H
#define MFD_T7L66XB_H
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
struct t7l66xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* The base for subdevice irqs */
struct tmio_nand_data *nand_data;
};
#define IRQ_T7L66XB_MMC (1)
#define IRQ_T7L66XB_NAND (3)
#define T7L66XB_NR_IRQS 8
#endif

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include/linux/mfd/tc3589x.h Normal file
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
*/
#ifndef __LINUX_MFD_TC3589x_H
#define __LINUX_MFD_TC3589x_H
struct device;
enum tx3589x_block {
TC3589x_BLOCK_GPIO = 1 << 0,
TC3589x_BLOCK_KEYPAD = 1 << 1,
};
#define TC3589x_RSTCTRL_IRQRST (1 << 4)
#define TC3589x_RSTCTRL_TIMRST (1 << 3)
#define TC3589x_RSTCTRL_ROTRST (1 << 2)
#define TC3589x_RSTCTRL_KBDRST (1 << 1)
#define TC3589x_RSTCTRL_GPIRST (1 << 0)
/* Keyboard Configuration Registers */
#define TC3589x_KBDSETTLE_REG 0x01
#define TC3589x_KBDBOUNCE 0x02
#define TC3589x_KBDSIZE 0x03
#define TC3589x_KBCFG_LSB 0x04
#define TC3589x_KBCFG_MSB 0x05
#define TC3589x_KBDIC 0x08
#define TC3589x_KBDMSK 0x09
#define TC3589x_EVTCODE_FIFO 0x10
#define TC3589x_KBDMFS 0x8F
#define TC3589x_IRQST 0x91
#define TC3589x_MANFCODE_MAGIC 0x03
#define TC3589x_MANFCODE 0x80
#define TC3589x_VERSION 0x81
#define TC3589x_IOCFG 0xA7
#define TC3589x_CLKMODE 0x88
#define TC3589x_CLKCFG 0x89
#define TC3589x_CLKEN 0x8A
#define TC3589x_RSTCTRL 0x82
#define TC3589x_EXTRSTN 0x83
#define TC3589x_RSTINTCLR 0x84
/* Pull up/down configuration registers */
#define TC3589x_IOCFG 0xA7
#define TC3589x_IOPULLCFG0_LSB 0xAA
#define TC3589x_IOPULLCFG0_MSB 0xAB
#define TC3589x_IOPULLCFG1_LSB 0xAC
#define TC3589x_IOPULLCFG1_MSB 0xAD
#define TC3589x_IOPULLCFG2_LSB 0xAE
#define TC3589x_GPIOIS0 0xC9
#define TC3589x_GPIOIS1 0xCA
#define TC3589x_GPIOIS2 0xCB
#define TC3589x_GPIOIBE0 0xCC
#define TC3589x_GPIOIBE1 0xCD
#define TC3589x_GPIOIBE2 0xCE
#define TC3589x_GPIOIEV0 0xCF
#define TC3589x_GPIOIEV1 0xD0
#define TC3589x_GPIOIEV2 0xD1
#define TC3589x_GPIOIE0 0xD2
#define TC3589x_GPIOIE1 0xD3
#define TC3589x_GPIOIE2 0xD4
#define TC3589x_GPIORIS0 0xD6
#define TC3589x_GPIORIS1 0xD7
#define TC3589x_GPIORIS2 0xD8
#define TC3589x_GPIOMIS0 0xD9
#define TC3589x_GPIOMIS1 0xDA
#define TC3589x_GPIOMIS2 0xDB
#define TC3589x_GPIOIC0 0xDC
#define TC3589x_GPIOIC1 0xDD
#define TC3589x_GPIOIC2 0xDE
#define TC3589x_GPIODATA0 0xC0
#define TC3589x_GPIOMASK0 0xc1
#define TC3589x_GPIODATA1 0xC2
#define TC3589x_GPIOMASK1 0xc3
#define TC3589x_GPIODATA2 0xC4
#define TC3589x_GPIOMASK2 0xC5
#define TC3589x_GPIODIR0 0xC6
#define TC3589x_GPIODIR1 0xC7
#define TC3589x_GPIODIR2 0xC8
#define TC3589x_GPIOSYNC0 0xE6
#define TC3589x_GPIOSYNC1 0xE7
#define TC3589x_GPIOSYNC2 0xE8
#define TC3589x_GPIOWAKE0 0xE9
#define TC3589x_GPIOWAKE1 0xEA
#define TC3589x_GPIOWAKE2 0xEB
#define TC3589x_GPIOODM0 0xE0
#define TC3589x_GPIOODE0 0xE1
#define TC3589x_GPIOODM1 0xE2
#define TC3589x_GPIOODE1 0xE3
#define TC3589x_GPIOODM2 0xE4
#define TC3589x_GPIOODE2 0xE5
#define TC3589x_INT_GPIIRQ 0
#define TC3589x_INT_TI0IRQ 1
#define TC3589x_INT_TI1IRQ 2
#define TC3589x_INT_TI2IRQ 3
#define TC3589x_INT_ROTIRQ 5
#define TC3589x_INT_KBDIRQ 6
#define TC3589x_INT_PORIRQ 7
#define TC3589x_NR_INTERNAL_IRQS 8
#define TC3589x_INT_GPIO(x) (TC3589x_NR_INTERNAL_IRQS + (x))
struct tc3589x {
struct mutex lock;
struct device *dev;
struct i2c_client *i2c;
struct irq_domain *domain;
int irq_base;
int num_gpio;
struct tc3589x_platform_data *pdata;
};
extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data);
extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg);
extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length,
u8 *values);
extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
const u8 *values);
extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val);
/*
* Keypad related platform specific constants
* These values may be modified for fine tuning
*/
#define TC_KPD_ROWS 0x8
#define TC_KPD_COLUMNS 0x8
#define TC_KPD_DEBOUNCE_PERIOD 0xA3
#define TC_KPD_SETTLE_TIME 0xA3
/**
* struct tc35893_platform_data - data structure for platform specific data
* @keymap_data: matrix scan code table for keycodes
* @krow: mask for available rows, value is 0xFF
* @kcol: mask for available columns, value is 0xFF
* @debounce_period: platform specific debounce time
* @settle_time: platform specific settle down time
* @irqtype: type of interrupt, falling or rising edge
* @enable_wakeup: specifies if keypad event can wake up system from sleep
* @no_autorepeat: flag for auto repetition
*/
struct tc3589x_keypad_platform_data {
const struct matrix_keymap_data *keymap_data;
u8 krow;
u8 kcol;
u8 debounce_period;
u8 settle_time;
unsigned long irqtype;
bool enable_wakeup;
bool no_autorepeat;
};
/**
* struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
* @gpio_base: first gpio number assigned to TC3589x. A maximum of
* %TC3589x_NR_GPIOS GPIOs will be allocated.
* @setup: callback for board-specific initialization
* @remove: callback for board-specific teardown
*/
struct tc3589x_gpio_platform_data {
int gpio_base;
void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
};
/**
* struct tc3589x_platform_data - TC3589x platform data
* @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
* @irq_base: base IRQ number. %TC3589x_NR_IRQS irqs will be used.
* @gpio: GPIO-specific platform data
* @keypad: keypad-specific platform data
*/
struct tc3589x_platform_data {
unsigned int block;
int irq_base;
struct tc3589x_gpio_platform_data *gpio;
const struct tc3589x_keypad_platform_data *keypad;
};
#define TC3589x_NR_GPIOS 24
#define TC3589x_NR_IRQS TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
#endif

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/*
* This file contains the definitions for the TC6387XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef MFD_TC6387XB_H
#define MFD_TC6387XB_H
struct tc6387xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
};
#endif

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/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MFD_TC6393XB_H
#define MFD_TC6393XB_H
#include <linux/fb.h>
/* Also one should provide the CK3P6MI clock */
struct tc6393xb_platform_data {
u16 scr_pll2cr; /* PLL2 Control */
u16 scr_gper; /* GP Enable */
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* base for subdevice irqs */
int gpio_base;
int (*setup)(struct platform_device *dev);
void (*teardown)(struct platform_device *dev);
struct tmio_nand_data *nand_data;
struct tmio_fb_data *fb_data;
unsigned resume_restore : 1; /* make special actions
to preserve the state
on suspend/resume */
};
extern int tc6393xb_lcd_mode(struct platform_device *fb,
const struct fb_videomode *mode);
extern int tc6393xb_lcd_set_power(struct platform_device *fb, bool on);
/*
* Relative to irq_base
*/
#define IRQ_TC6393_NAND 0
#define IRQ_TC6393_MMC 1
#define IRQ_TC6393_OHCI 2
#define IRQ_TC6393_FB 4
#define TC6393XB_NR_IRQS 8
#endif

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#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
#define __LINUX_TI_AM335X_TSCADC_MFD_H
/*
* TI Touch Screen / ADC MFD driver
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mfd/core.h>
#define REG_RAWIRQSTATUS 0x024
#define REG_IRQSTATUS 0x028
#define REG_IRQENABLE 0x02C
#define REG_IRQCLR 0x030
#define REG_IRQWAKEUP 0x034
#define REG_CTRL 0x040
#define REG_ADCFSM 0x044
#define REG_CLKDIV 0x04C
#define REG_SE 0x054
#define REG_IDLECONFIG 0x058
#define REG_CHARGECONFIG 0x05C
#define REG_CHARGEDELAY 0x060
#define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8))
#define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8))
#define REG_FIFO0CNT 0xE4
#define REG_FIFO0THR 0xE8
#define REG_FIFO1CNT 0xF0
#define REG_FIFO1THR 0xF4
#define REG_FIFO0 0x100
#define REG_FIFO1 0x200
/* Register Bitfields */
/* IRQ wakeup enable */
#define IRQWKUP_ENB BIT(0)
/* Step Enable */
#define STEPENB_MASK (0x1FFFF << 0)
#define STEPENB(val) ((val) << 0)
#define STPENB_STEPENB STEPENB(0x1FFFF)
#define STPENB_STEPENB_TC STEPENB(0x1FFF)
/* IRQ enable */
#define IRQENB_HW_PEN BIT(0)
#define IRQENB_FIFO0THRES BIT(2)
#define IRQENB_FIFO1THRES BIT(5)
#define IRQENB_PENUP BIT(9)
/* Step Configuration */
#define STEPCONFIG_MODE_MASK (3 << 0)
#define STEPCONFIG_MODE(val) ((val) << 0)
#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
#define STEPCONFIG_AVG_MASK (7 << 2)
#define STEPCONFIG_AVG(val) ((val) << 2)
#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
#define STEPCONFIG_XPP BIT(5)
#define STEPCONFIG_XNN BIT(6)
#define STEPCONFIG_YPP BIT(7)
#define STEPCONFIG_YNN BIT(8)
#define STEPCONFIG_XNP BIT(9)
#define STEPCONFIG_YPN BIT(10)
#define STEPCONFIG_INM_MASK (0xF << 15)
#define STEPCONFIG_INM(val) ((val) << 15)
#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
#define STEPCONFIG_INP_MASK (0xF << 19)
#define STEPCONFIG_INP(val) ((val) << 19)
#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
#define STEPCONFIG_FIFO1 BIT(26)
/* Delay register */
#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
#define STEPDELAY_OPEN(val) ((val) << 0)
#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
#define STEPDELAY_SAMPLE(val) ((val) << 24)
#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
/* Charge Config */
#define STEPCHARGE_RFP_MASK (7 << 12)
#define STEPCHARGE_RFP(val) ((val) << 12)
#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
#define STEPCHARGE_INM_MASK (0xF << 15)
#define STEPCHARGE_INM(val) ((val) << 15)
#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
#define STEPCHARGE_INP_MASK (0xF << 19)
#define STEPCHARGE_INP(val) ((val) << 19)
#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
#define STEPCHARGE_RFM_MASK (3 << 23)
#define STEPCHARGE_RFM(val) ((val) << 23)
#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
/* Charge delay */
#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
#define CHARGEDLY_OPEN(val) ((val) << 0)
#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1)
/* Control register */
#define CNTRLREG_TSCSSENB BIT(0)
#define CNTRLREG_STEPID BIT(1)
#define CNTRLREG_STEPCONFIGWRT BIT(2)
#define CNTRLREG_POWERDOWN BIT(4)
#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
#define CNTRLREG_TSCENB BIT(7)
#define ADC_CLK 3000000
#define MAX_CLK_DIV 7
#define TOTAL_STEPS 16
#define TOTAL_CHANNELS 8
#define TSCADC_CELLS 2
enum tscadc_cells {
TSC_CELL,
ADC_CELL,
};
struct mfd_tscadc_board {
struct tsc_data *tsc_init;
struct adc_data *adc_init;
};
struct ti_tscadc_dev {
struct device *dev;
struct regmap *regmap_tscadc;
void __iomem *tscadc_base;
int irq;
struct mfd_cell cells[TSCADC_CELLS];
/* tsc device */
struct titsc *tsc;
/* adc device */
struct adc_device *adc;
};
#endif

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/*
* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TI_SSP_H__
#define __TI_SSP_H__
struct ti_ssp_dev_data {
const char *dev_name;
void *pdata;
size_t pdata_size;
};
struct ti_ssp_data {
unsigned long out_clock;
struct ti_ssp_dev_data dev_data[2];
};
struct ti_ssp_spi_data {
unsigned long iosel;
int num_cs;
void (*select)(int cs);
};
/*
* Sequencer port IO pin configuration bits. These do not correlate 1-1 with
* the hardware. The iosel field in the port data combines iosel1 and iosel2,
* and is therefore not a direct map to register space. It is best to use the
* macros below to construct iosel values.
*
* least significant 16 bits --> iosel1
* most significant 16 bits --> iosel2
*/
#define SSP_IN 0x0000
#define SSP_DATA 0x0001
#define SSP_CLOCK 0x0002
#define SSP_CHIPSEL 0x0003
#define SSP_OUT 0x0004
#define SSP_PIN_SEL(pin, v) ((v) << ((pin) * 3))
#define SSP_PIN_MASK(pin) SSP_PIN_SEL(pin, 0x7)
#define SSP_INPUT_SEL(pin) ((pin) << 16)
/* Sequencer port config bits */
#define SSP_EARLY_DIN BIT(8)
#define SSP_DELAY_DOUT BIT(9)
/* Sequence map definitions */
#define SSP_CLK_HIGH BIT(0)
#define SSP_CLK_LOW 0
#define SSP_DATA_HIGH BIT(1)
#define SSP_DATA_LOW 0
#define SSP_CS_HIGH BIT(2)
#define SSP_CS_LOW 0
#define SSP_OUT_MODE BIT(3)
#define SSP_IN_MODE 0
#define SSP_DATA_REG BIT(4)
#define SSP_ADDR_REG 0
#define SSP_OPCODE_DIRECT ((0x0) << 5)
#define SSP_OPCODE_TOGGLE ((0x1) << 5)
#define SSP_OPCODE_SHIFT ((0x2) << 5)
#define SSP_OPCODE_BRANCH0 ((0x4) << 5)
#define SSP_OPCODE_BRANCH1 ((0x5) << 5)
#define SSP_OPCODE_BRANCH ((0x6) << 5)
#define SSP_OPCODE_STOP ((0x7) << 5)
#define SSP_BRANCH(addr) ((addr) << 8)
#define SSP_COUNT(cycles) ((cycles) << 8)
int ti_ssp_raw_read(struct device *dev);
int ti_ssp_raw_write(struct device *dev, u32 val);
int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
int ti_ssp_set_mode(struct device *dev, int mode);
int ti_ssp_set_iosel(struct device *dev, u32 iosel);
#endif /* __TI_SSP_H__ */

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#ifndef MFD_TMIO_H
#define MFD_TMIO_H
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
#define tmio_ioread32(addr) \
(((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
#define tmio_iowrite8(val, addr) writeb((val), (addr))
#define tmio_iowrite16(val, addr) writew((val), (addr))
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
#define tmio_iowrite32(val, addr) \
do { \
writew((val), (addr)); \
writew((val) >> 16, (addr) + 2); \
} while (0)
#define CNF_CMD 0x04
#define CNF_CTL_BASE 0x10
#define CNF_INT_PIN 0x3d
#define CNF_STOP_CLK_CTL 0x40
#define CNF_GCLK_CTL 0x41
#define CNF_SD_CLK_MODE 0x42
#define CNF_PIN_STATUS 0x44
#define CNF_PWR_CTL_1 0x48
#define CNF_PWR_CTL_2 0x49
#define CNF_PWR_CTL_3 0x4a
#define CNF_CARD_DETECT_MODE 0x4c
#define CNF_SD_SLOT 0x50
#define CNF_EXT_GCLK_CTL_1 0xf0
#define CNF_EXT_GCLK_CTL_2 0xf1
#define CNF_EXT_GCLK_CTL_3 0xf9
#define CNF_SD_LED_EN_1 0xfa
#define CNF_SD_LED_EN_2 0xfe
#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
#define sd_config_write8(base, shift, reg, val) \
tmio_iowrite8((val), (base) + ((reg) << (shift)))
#define sd_config_write16(base, shift, reg, val) \
tmio_iowrite16((val), (base) + ((reg) << (shift)))
#define sd_config_write32(base, shift, reg, val) \
do { \
tmio_iowrite16((val), (base) + ((reg) << (shift))); \
tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
} while (0)
/* tmio MMC platform flags */
#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
/*
* Some controllers can support a 2-byte block size when the bus width
* is configured in 4-bit mode.
*/
#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
/*
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ (1 << 2)
/*
* Some controllers require waiting for the SD bus to become
* idle before writing to some registers.
*/
#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
/*
* A GPIO is used for card hotplug detection. We need an extra flag for this,
* because 0 is a valid GPIO number too, and requiring users to specify
* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
*/
#define TMIO_MMC_USE_GPIO_CD (1 << 5)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
struct tmio_mmc_dma {
void *chan_priv_tx;
void *chan_priv_rx;
int alignment_shift;
};
struct tmio_mmc_host;
/*
* data for the MMC controller
*/
struct tmio_mmc_data {
unsigned int hclk;
unsigned long capabilities;
unsigned long capabilities2;
unsigned long flags;
u32 ocr_mask; /* available voltages */
struct tmio_mmc_dma *dma;
struct device *dev;
unsigned int cd_gpio;
void (*set_pwr)(struct platform_device *host, int state);
void (*set_clk_div)(struct platform_device *host, int state);
int (*get_cd)(struct platform_device *host);
int (*write16_hook)(struct tmio_mmc_host *host, int addr);
/* clock management callbacks */
int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
void (*clk_disable)(struct platform_device *pdev);
};
/*
* data for the NAND controller
*/
struct tmio_nand_data {
struct nand_bbt_descr *badblock_pattern;
struct mtd_partition *partition;
unsigned int num_partitions;
};
#define FBIO_TMIO_ACC_WRITE 0x7C639300
#define FBIO_TMIO_ACC_SYNC 0x7C639301
struct tmio_fb_data {
int (*lcd_set_power)(struct platform_device *fb_dev,
bool on);
int (*lcd_mode)(struct platform_device *fb_dev,
const struct fb_videomode *mode);
int num_modes;
struct fb_videomode *modes;
/* in mm: size of screen */
int height;
int width;
};
#endif

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/*
* Copyright (C) 2011 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <linus.walleij@linaro.org>
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef MFD_TPS6105X_H
#define MFD_TPS6105X_H
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
/*
* Register definitions to all subdrivers
*/
#define TPS6105X_REG_0 0x00
#define TPS6105X_REG0_MODE_SHIFT 6
#define TPS6105X_REG0_MODE_MASK (0x03<<6)
/* These defines for both reg0 and reg1 */
#define TPS6105X_REG0_MODE_SHUTDOWN 0x00
#define TPS6105X_REG0_MODE_TORCH 0x01
#define TPS6105X_REG0_MODE_TORCH_FLASH 0x02
#define TPS6105X_REG0_MODE_VOLTAGE 0x03
#define TPS6105X_REG0_VOLTAGE_SHIFT 4
#define TPS6105X_REG0_VOLTAGE_MASK (3<<4)
#define TPS6105X_REG0_VOLTAGE_450 0
#define TPS6105X_REG0_VOLTAGE_500 1
#define TPS6105X_REG0_VOLTAGE_525 2
#define TPS6105X_REG0_VOLTAGE_500_2 3
#define TPS6105X_REG0_DIMMING_SHIFT 3
#define TPS6105X_REG0_TORCHC_SHIFT 0
#define TPS6105X_REG0_TORCHC_MASK (7<<0)
#define TPS6105X_REG0_TORCHC_0 0x00
#define TPS6105X_REG0_TORCHC_50 0x01
#define TPS6105X_REG0_TORCHC_75 0x02
#define TPS6105X_REG0_TORCHC_100 0x03
#define TPS6105X_REG0_TORCHC_150 0x04
#define TPS6105X_REG0_TORCHC_200 0x05
#define TPS6105X_REG0_TORCHC_250_400 0x06
#define TPS6105X_REG0_TORCHC_250_500 0x07
#define TPS6105X_REG_1 0x01
#define TPS6105X_REG1_MODE_SHIFT 6
#define TPS6105X_REG1_MODE_MASK (0x03<<6)
#define TPS6105X_REG1_MODE_SHUTDOWN 0x00
#define TPS6105X_REG1_MODE_TORCH 0x01
#define TPS6105X_REG1_MODE_TORCH_FLASH 0x02
#define TPS6105X_REG1_MODE_VOLTAGE 0x03
#define TPS6105X_REG_2 0x02
#define TPS6105X_REG_3 0x03
/**
* enum tps6105x_mode - desired mode for the TPS6105x
* @TPS6105X_MODE_SHUTDOWN: this instance is inactive, not used for anything
* @TPS61905X_MODE_TORCH: this instance is used as a LED, usually a while
* LED, for example as backlight or flashlight. If this is set, the
* TPS6105X will register to the LED framework
* @TPS6105X_MODE_TORCH_FLASH: this instance is used as a flashgun, usually
* in a camera
* @TPS6105X_MODE_VOLTAGE: this instance is used as a voltage regulator and
* will register to the regulator framework
*/
enum tps6105x_mode {
TPS6105X_MODE_SHUTDOWN,
TPS6105X_MODE_TORCH,
TPS6105X_MODE_TORCH_FLASH,
TPS6105X_MODE_VOLTAGE,
};
/**
* struct tps6105x_platform_data - TPS61905x platform data
* @mode: what mode this instance shall be operated in,
* this is not selectable at runtime
* @regulator_data: initialization data for the voltage
* regulator if used as a voltage source
*/
struct tps6105x_platform_data {
enum tps6105x_mode mode;
struct regulator_init_data *regulator_data;
};
/**
* struct tps6105x - state holder for the TPS6105x drivers
* @mutex: mutex to serialize I2C accesses
* @i2c_client: corresponding I2C client
* @regulator: regulator device if used in voltage mode
*/
struct tps6105x {
struct tps6105x_platform_data *pdata;
struct mutex lock;
struct i2c_client *client;
struct regulator_dev *regulator;
};
extern int tps6105x_set(struct tps6105x *tps6105x, u8 reg, u8 value);
extern int tps6105x_get(struct tps6105x *tps6105x, u8 reg, u8 *buf);
extern int tps6105x_mask_and_set(struct tps6105x *tps6105x, u8 reg,
u8 bitmask, u8 bitvalues);
#endif

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/* linux/mfd/tps6507x.h
*
* Functions to access TPS65070 power management chip.
*
* Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
*
*
* For licencing details see kernel-base/COPYING
*/
#ifndef __LINUX_MFD_TPS6507X_H
#define __LINUX_MFD_TPS6507X_H
/*
* ----------------------------------------------------------------------------
* Registers, all 8 bits
* ----------------------------------------------------------------------------
*/
/* Register definitions */
#define TPS6507X_REG_PPATH1 0X01
#define TPS6507X_CHG_USB BIT(7)
#define TPS6507X_CHG_AC BIT(6)
#define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
#define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
#define TPS6507X_CHG_AC_CURRENT BIT(2)
#define TPS6507X_CHG_USB_CURRENT BIT(0)
#define TPS6507X_REG_INT 0X02
#define TPS6507X_REG_MASK_AC_USB BIT(7)
#define TPS6507X_REG_MASK_TSC BIT(6)
#define TPS6507X_REG_MASK_PB_IN BIT(5)
#define TPS6507X_REG_TSC_INT BIT(3)
#define TPS6507X_REG_PB_IN_INT BIT(2)
#define TPS6507X_REG_AC_USB_APPLIED BIT(1)
#define TPS6507X_REG_AC_USB_REMOVED BIT(0)
#define TPS6507X_REG_CHGCONFIG0 0X03
#define TPS6507X_REG_CHGCONFIG1 0X04
#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
#define TPS6507X_REG_CHGCONFIG2 0X05
#define TPS6507X_REG_CHGCONFIG3 0X06
#define TPS6507X_REG_ADCONFIG 0X07
#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7)
#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6)
#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5)
#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4)
#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0
#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1
#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2
#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3
#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4
#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5
#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6
#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7
#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8
#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9
#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10
#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11
#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12
#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14
#define TPS6507X_ADCONFIG_INPUT_TSC 15
#define TPS6507X_REG_TSCMODE 0X08
#define TPS6507X_TSCMODE_X_POSITION 0
#define TPS6507X_TSCMODE_Y_POSITION 1
#define TPS6507X_TSCMODE_PRESSURE 2
#define TPS6507X_TSCMODE_X_PLATE 3
#define TPS6507X_TSCMODE_Y_PLATE 4
#define TPS6507X_TSCMODE_STANDBY 5
#define TPS6507X_TSCMODE_ADC_INPUT 6
#define TPS6507X_TSCMODE_DISABLE 7
#define TPS6507X_REG_ADRESULT_1 0X09
#define TPS6507X_REG_ADRESULT_2 0X0A
#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0))
#define TPS6507X_REG_PGOOD 0X0B
#define TPS6507X_REG_PGOODMASK 0X0C
#define TPS6507X_REG_CON_CTRL1 0X0D
#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
#define TPS6507X_REG_CON_CTRL2 0X0E
#define TPS6507X_REG_CON_CTRL3 0X0F
#define TPS6507X_REG_DEFDCDC1 0X10
#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7)
#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F
#define TPS6507X_REG_DEFDCDC2_LOW 0X11
#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F
#define TPS6507X_REG_DEFDCDC2_HIGH 0X12
#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F
#define TPS6507X_REG_DEFDCDC3_LOW 0X13
#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F
#define TPS6507X_REG_DEFDCDC3_HIGH 0X14
#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F
#define TPS6507X_REG_DEFSLEW 0X15
#define TPS6507X_REG_LDO_CTRL1 0X16
#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F
#define TPS6507X_REG_DEFLDO2 0X17
#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F
#define TPS6507X_REG_WLED_CTRL1 0X18
#define TPS6507X_REG_WLED_CTRL2 0X19
/* VDCDC MASK */
#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F
#define TPS6507X_MAX_REGISTER 0X19
/**
* struct tps6507x_board - packages regulator and touchscreen init data
* @tps6507x_regulator_data: regulator initialization values
*
* Board data may be used to initialize regulator and touchscreen.
*/
struct tps6507x_board {
struct regulator_init_data *tps6507x_pmic_init_data;
struct touchscreen_init_data *tps6507x_ts_init_data;
};
/**
* struct tps6507x_dev - tps6507x sub-driver chip access routines
* @read_dev() - I2C register read function
* @write_dev() - I2C register write function
*
* Device data may be used to access the TPS6507x chip
*/
struct tps6507x_dev {
struct device *dev;
struct i2c_client *i2c_client;
int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
void *dest);
int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
void *src);
/* Client devices */
struct tps6507x_pmic *pmic;
struct tps6507x_ts *ts;
};
#endif /* __LINUX_MFD_TPS6507X_H */

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/*
* Core driver interface for TI TPS65090 PMIC family
*
* Copyright (C) 2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
#ifndef __LINUX_MFD_TPS65090_H
#define __LINUX_MFD_TPS65090_H
#include <linux/irq.h>
#include <linux/regmap.h>
/* TPS65090 IRQs */
enum {
TPS65090_IRQ_INTERRUPT,
TPS65090_IRQ_VAC_STATUS_CHANGE,
TPS65090_IRQ_VSYS_STATUS_CHANGE,
TPS65090_IRQ_BAT_STATUS_CHANGE,
TPS65090_IRQ_CHARGING_STATUS_CHANGE,
TPS65090_IRQ_CHARGING_COMPLETE,
TPS65090_IRQ_OVERLOAD_DCDC1,
TPS65090_IRQ_OVERLOAD_DCDC2,
TPS65090_IRQ_OVERLOAD_DCDC3,
TPS65090_IRQ_OVERLOAD_FET1,
TPS65090_IRQ_OVERLOAD_FET2,
TPS65090_IRQ_OVERLOAD_FET3,
TPS65090_IRQ_OVERLOAD_FET4,
TPS65090_IRQ_OVERLOAD_FET5,
TPS65090_IRQ_OVERLOAD_FET6,
TPS65090_IRQ_OVERLOAD_FET7,
};
/* TPS65090 Regulator ID */
enum {
TPS65090_REGULATOR_DCDC1,
TPS65090_REGULATOR_DCDC2,
TPS65090_REGULATOR_DCDC3,
TPS65090_REGULATOR_FET1,
TPS65090_REGULATOR_FET2,
TPS65090_REGULATOR_FET3,
TPS65090_REGULATOR_FET4,
TPS65090_REGULATOR_FET5,
TPS65090_REGULATOR_FET6,
TPS65090_REGULATOR_FET7,
TPS65090_REGULATOR_LDO1,
TPS65090_REGULATOR_LDO2,
/* Last entry for maximum ID */
TPS65090_REGULATOR_MAX,
};
struct tps65090 {
struct device *dev;
struct regmap *rmap;
struct regmap_irq_chip_data *irq_data;
};
/*
* struct tps65090_regulator_plat_data
*
* @reg_init_data: The regulator init data.
* @enable_ext_control: Enable extrenal control or not. Only available for
* DCDC1, DCDC2 and DCDC3.
* @gpio: Gpio number if external control is enabled and controlled through
* gpio.
*/
struct tps65090_regulator_plat_data {
struct regulator_init_data *reg_init_data;
bool enable_ext_control;
int gpio;
};
struct tps65090_platform_data {
int irq_base;
char **supplied_to;
size_t num_supplicants;
int enable_low_current_chrg;
struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
};
/*
* NOTE: the functions below are not intended for use outside
* of the TPS65090 sub-device drivers
*/
static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
{
struct tps65090 *tps = dev_get_drvdata(dev);
return regmap_write(tps->rmap, reg, val);
}
static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
{
struct tps65090 *tps = dev_get_drvdata(dev);
unsigned int temp_val;
int ret;
ret = regmap_read(tps->rmap, reg, &temp_val);
if (!ret)
*val = temp_val;
return ret;
}
static inline int tps65090_set_bits(struct device *dev, int reg,
uint8_t bit_num)
{
struct tps65090 *tps = dev_get_drvdata(dev);
return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
}
static inline int tps65090_clr_bits(struct device *dev, int reg,
uint8_t bit_num)
{
struct tps65090 *tps = dev_get_drvdata(dev);
return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
}
#endif /*__LINUX_MFD_TPS65090_H */

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/*
* linux/mfd/tps65217.h
*
* Functions to access TPS65217 power management chip.
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_MFD_TPS65217_H
#define __LINUX_MFD_TPS65217_H
#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
/* TPS chip id list */
#define TPS65217 0xF0
/* I2C ID for TPS65217 part */
#define TPS65217_I2C_ID 0x24
/* All register addresses */
#define TPS65217_REG_CHIPID 0X00
#define TPS65217_REG_PPATH 0X01
#define TPS65217_REG_INT 0X02
#define TPS65217_REG_CHGCONFIG0 0X03
#define TPS65217_REG_CHGCONFIG1 0X04
#define TPS65217_REG_CHGCONFIG2 0X05
#define TPS65217_REG_CHGCONFIG3 0X06
#define TPS65217_REG_WLEDCTRL1 0X07
#define TPS65217_REG_WLEDCTRL2 0X08
#define TPS65217_REG_MUXCTRL 0X09
#define TPS65217_REG_STATUS 0X0A
#define TPS65217_REG_PASSWORD 0X0B
#define TPS65217_REG_PGOOD 0X0C
#define TPS65217_REG_DEFPG 0X0D
#define TPS65217_REG_DEFDCDC1 0X0E
#define TPS65217_REG_DEFDCDC2 0X0F
#define TPS65217_REG_DEFDCDC3 0X10
#define TPS65217_REG_DEFSLEW 0X11
#define TPS65217_REG_DEFLDO1 0X12
#define TPS65217_REG_DEFLDO2 0X13
#define TPS65217_REG_DEFLS1 0X14
#define TPS65217_REG_DEFLS2 0X15
#define TPS65217_REG_ENABLE 0X16
#define TPS65217_REG_DEFUVLO 0X18
#define TPS65217_REG_SEQ1 0X19
#define TPS65217_REG_SEQ2 0X1A
#define TPS65217_REG_SEQ3 0X1B
#define TPS65217_REG_SEQ4 0X1C
#define TPS65217_REG_SEQ5 0X1D
#define TPS65217_REG_SEQ6 0X1E
/* Register field definitions */
#define TPS65217_CHIPID_CHIP_MASK 0xF0
#define TPS65217_CHIPID_REV_MASK 0x0F
#define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
#define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
#define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
#define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
#define TPS65217_INT_PBM BIT(6)
#define TPS65217_INT_ACM BIT(5)
#define TPS65217_INT_USBM BIT(4)
#define TPS65217_INT_PBI BIT(2)
#define TPS65217_INT_ACI BIT(1)
#define TPS65217_INT_USBI BIT(0)
#define TPS65217_CHGCONFIG0_TREG BIT(7)
#define TPS65217_CHGCONFIG0_DPPM BIT(6)
#define TPS65217_CHGCONFIG0_TSUSP BIT(5)
#define TPS65217_CHGCONFIG0_TERMI BIT(4)
#define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
#define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
#define TPS65217_CHGCONFIG1_RESET BIT(3)
#define TPS65217_CHGCONFIG1_TERM BIT(2)
#define TPS65217_CHGCONFIG1_SUSP BIT(1)
#define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
#define TPS65217_CHGCONFIG2_TERMIF 0x06
#define TPS65217_CHGCONFIG2_TRANGE BIT(0)
#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
#define TPS65217_WLEDCTRL1_ISEL BIT(2)
#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
#define TPS65217_MUXCTRL_MUX_MASK 0x07
#define TPS65217_STATUS_OFF BIT(7)
#define TPS65217_STATUS_ACPWR BIT(3)
#define TPS65217_STATUS_USBPWR BIT(2)
#define TPS65217_STATUS_PB BIT(0)
#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
#define TPS65217_PGOOD_LDO3_PG BIT(6)
#define TPS65217_PGOOD_LDO4_PG BIT(5)
#define TPS65217_PGOOD_DC1_PG BIT(4)
#define TPS65217_PGOOD_DC2_PG BIT(3)
#define TPS65217_PGOOD_DC3_PG BIT(2)
#define TPS65217_PGOOD_LDO1_PG BIT(1)
#define TPS65217_PGOOD_LDO2_PG BIT(0)
#define TPS65217_DEFPG_LDO1PGM BIT(3)
#define TPS65217_DEFPG_LDO2PGM BIT(2)
#define TPS65217_DEFPG_PGDLY_MASK 0x03
#define TPS65217_DEFDCDCX_XADJX BIT(7)
#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
#define TPS65217_DEFSLEW_GO BIT(7)
#define TPS65217_DEFSLEW_GODSBL BIT(6)
#define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
#define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
#define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
#define TPS65217_DEFSLEW_SLEW_MASK 0x07
#define TPS65217_DEFLDO1_LDO1_MASK 0x0F
#define TPS65217_DEFLDO2_TRACK BIT(6)
#define TPS65217_DEFLDO2_LDO2_MASK 0x3F
#define TPS65217_DEFLDO3_LDO3_EN BIT(5)
#define TPS65217_DEFLDO3_LDO3_MASK 0x1F
#define TPS65217_DEFLDO4_LDO4_EN BIT(5)
#define TPS65217_DEFLDO4_LDO4_MASK 0x1F
#define TPS65217_ENABLE_LS1_EN BIT(6)
#define TPS65217_ENABLE_LS2_EN BIT(5)
#define TPS65217_ENABLE_DC1_EN BIT(4)
#define TPS65217_ENABLE_DC2_EN BIT(3)
#define TPS65217_ENABLE_DC3_EN BIT(2)
#define TPS65217_ENABLE_LDO1_EN BIT(1)
#define TPS65217_ENABLE_LDO2_EN BIT(0)
#define TPS65217_DEFUVLO_UVLOHYS BIT(2)
#define TPS65217_DEFUVLO_UVLO_MASK 0x03
#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
#define TPS65217_SEQ5_DLY1_MASK 0xC0
#define TPS65217_SEQ5_DLY2_MASK 0x30
#define TPS65217_SEQ5_DLY3_MASK 0x0C
#define TPS65217_SEQ5_DLY4_MASK 0x03
#define TPS65217_SEQ6_DLY5_MASK 0xC0
#define TPS65217_SEQ6_DLY6_MASK 0x30
#define TPS65217_SEQ6_SEQUP BIT(2)
#define TPS65217_SEQ6_SEQDWN BIT(1)
#define TPS65217_SEQ6_INSTDWN BIT(0)
#define TPS65217_MAX_REGISTER 0x1E
#define TPS65217_PROTECT_NONE 0
#define TPS65217_PROTECT_L1 1
#define TPS65217_PROTECT_L2 2
enum tps65217_regulator_id {
/* DCDC's */
TPS65217_DCDC_1,
TPS65217_DCDC_2,
TPS65217_DCDC_3,
/* LDOs */
TPS65217_LDO_1,
TPS65217_LDO_2,
TPS65217_LDO_3,
TPS65217_LDO_4,
};
#define TPS65217_MAX_REG_ID TPS65217_LDO_4
/* Number of step-down converters available */
#define TPS65217_NUM_DCDC 3
/* Number of LDO voltage regulators available */
#define TPS65217_NUM_LDO 4
/* Number of total regulators available */
#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
enum tps65217_bl_isel {
TPS65217_BL_ISET1 = 1,
TPS65217_BL_ISET2,
};
enum tps65217_bl_fdim {
TPS65217_BL_FDIM_100HZ,
TPS65217_BL_FDIM_200HZ,
TPS65217_BL_FDIM_500HZ,
TPS65217_BL_FDIM_1000HZ,
};
struct tps65217_bl_pdata {
enum tps65217_bl_isel isel;
enum tps65217_bl_fdim fdim;
int dft_brightness;
};
/**
* struct tps65217_board - packages regulator init data
* @tps65217_regulator_data: regulator initialization values
*
* Board data may be used to initialize regulator.
*/
struct tps65217_board {
struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
struct device_node *of_node[TPS65217_NUM_REGULATOR];
struct tps65217_bl_pdata *bl_pdata;
};
/**
* struct tps_info - packages regulator constraints
* @name: Voltage regulator name
* @min_uV: minimum micro volts
* @max_uV: minimum micro volts
* @vsel_to_uv: Function pointer to get voltage from selector
* @uv_to_vsel: Function pointer to get selector from voltage
*
* This data is used to check the regualtor voltage limits while setting.
*/
struct tps_info {
const char *name;
int min_uV;
int max_uV;
int (*vsel_to_uv)(unsigned int vsel);
int (*uv_to_vsel)(int uV, unsigned int *vsel);
};
/**
* struct tps65217 - tps65217 sub-driver chip access routines
*
* Device data may be used to access the TPS65217 chip
*/
struct tps65217 {
struct device *dev;
struct tps65217_board *pdata;
unsigned int id;
struct regulator_desc desc[TPS65217_NUM_REGULATOR];
struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
struct tps_info *info[TPS65217_NUM_REGULATOR];
struct regmap *regmap;
};
static inline struct tps65217 *dev_to_tps65217(struct device *dev)
{
return dev_get_drvdata(dev);
}
static inline int tps65217_chip_id(struct tps65217 *tps65217)
{
return tps65217->id;
}
int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
unsigned int *val);
int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
unsigned int val, unsigned int level);
int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level);
int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int level);
#endif /* __LINUX_MFD_TPS65217_H */

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#ifndef __LINUX_MFD_TPS6586X_H
#define __LINUX_MFD_TPS6586X_H
#define TPS6586X_SLEW_RATE_INSTANTLY 0x00
#define TPS6586X_SLEW_RATE_110UV 0x01
#define TPS6586X_SLEW_RATE_220UV 0x02
#define TPS6586X_SLEW_RATE_440UV 0x03
#define TPS6586X_SLEW_RATE_880UV 0x04
#define TPS6586X_SLEW_RATE_1760UV 0x05
#define TPS6586X_SLEW_RATE_3520UV 0x06
#define TPS6586X_SLEW_RATE_7040UV 0x07
#define TPS6586X_SLEW_RATE_SET 0x08
#define TPS6586X_SLEW_RATE_MASK 0x07
enum {
TPS6586X_ID_SYS,
TPS6586X_ID_SM_0,
TPS6586X_ID_SM_1,
TPS6586X_ID_SM_2,
TPS6586X_ID_LDO_0,
TPS6586X_ID_LDO_1,
TPS6586X_ID_LDO_2,
TPS6586X_ID_LDO_3,
TPS6586X_ID_LDO_4,
TPS6586X_ID_LDO_5,
TPS6586X_ID_LDO_6,
TPS6586X_ID_LDO_7,
TPS6586X_ID_LDO_8,
TPS6586X_ID_LDO_9,
TPS6586X_ID_LDO_RTC,
TPS6586X_ID_MAX_REGULATOR,
};
enum {
TPS6586X_INT_PLDO_0,
TPS6586X_INT_PLDO_1,
TPS6586X_INT_PLDO_2,
TPS6586X_INT_PLDO_3,
TPS6586X_INT_PLDO_4,
TPS6586X_INT_PLDO_5,
TPS6586X_INT_PLDO_6,
TPS6586X_INT_PLDO_7,
TPS6586X_INT_COMP_DET,
TPS6586X_INT_ADC,
TPS6586X_INT_PLDO_8,
TPS6586X_INT_PLDO_9,
TPS6586X_INT_PSM_0,
TPS6586X_INT_PSM_1,
TPS6586X_INT_PSM_2,
TPS6586X_INT_PSM_3,
TPS6586X_INT_RTC_ALM1,
TPS6586X_INT_ACUSB_OVP,
TPS6586X_INT_USB_DET,
TPS6586X_INT_AC_DET,
TPS6586X_INT_BAT_DET,
TPS6586X_INT_CHG_STAT,
TPS6586X_INT_CHG_TEMP,
TPS6586X_INT_PP,
TPS6586X_INT_RESUME,
TPS6586X_INT_LOW_SYS,
TPS6586X_INT_RTC_ALM2,
};
struct tps6586x_settings {
int slew_rate;
};
struct tps6586x_subdev_info {
int id;
const char *name;
void *platform_data;
struct device_node *of_node;
};
struct tps6586x_platform_data {
int num_subdevs;
struct tps6586x_subdev_info *subdevs;
int gpio_base;
int irq_base;
bool pm_off;
struct regulator_init_data *reg_init_data[TPS6586X_ID_MAX_REGULATOR];
};
/*
* NOTE: the functions below are not intended for use outside
* of the TPS6586X sub-device drivers
*/
extern int tps6586x_write(struct device *dev, int reg, uint8_t val);
extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int tps6586x_read(struct device *dev, int reg, uint8_t *val);
extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
uint8_t mask);
extern int tps6586x_irq_get_virq(struct device *dev, int irq);
#endif /*__LINUX_MFD_TPS6586X_H */

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