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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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14
drivers/staging/slicoss/Kconfig Normal file
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config SLICOSS
tristate "Alacritech Gigabit IS-NIC support"
depends on PCI && X86 && NET
default n
help
This driver supports Alacritech's IS-NIC gigabit ethernet cards.
This includes the following devices:
Mojave cards (single port PCI Gigabit) both copper and fiber
Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
To compile this driver as a module, choose M here: the module
will be called slicoss.

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drivers/staging/slicoss/Makefile Normal file
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obj-$(CONFIG_SLICOSS) += slicoss.o

48
drivers/staging/slicoss/README Normal file
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This driver is supposed to support:
Mojave cards (single port PCI Gigabit) both copper and fiber
Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
The driver was actually tested on Oasis and Kalahari cards.
TODO:
- move firmware loading to request_firmware()
- remove direct memory access of structures
- any remaining sparse and checkpatch.pl warnings
- use net_device_ops
- use dev->stats rather than adapter->stats
- don't cast netdev_priv it is already void
- use compare_ether_addr
- GET RID OF MACROS
- work on all architectures
- without CONFIG_X86_64 confusion
- do 64 bit correctly
- don't depend on order of union
- get rid of ASSERT(), use BUG() instead but only where necessary
looks like most aren't really useful
- no new SIOCDEVPRIVATE ioctl allowed
- don't use module_param for configuring interrupt mitigation
use ethtool instead
- reorder code to elminate use of forward declarations
- don't keep private linked list of drivers.
- remove all the gratiutous debug infrastructure
- use PCI_DEVICE()
- do ethtool correctly using ethtool_ops
- NAPI?
- wasted overhead of extra stats
- state variables for things that are
easily available and shouldn't be kept in card structure, cardnum, ...
slotnumber, events, ...
- get rid of slic_spinlock wrapper
- volatile == bad design => bad code
- locking too fine grained, not designed just throw more locks
at problem
Please send patches to:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
and Cc: Lior Dotan <liodot@gmail.com> and Christopher Harrer
<charrer@alacritech.com> as well as they are also able to test out any
changes.

537
drivers/staging/slicoss/slic.h Normal file
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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slic.h
*
* This is the base set of header definitions for the SLICOSS driver.
*/
#ifndef __SLIC_DRIVER_H__
#define __SLIC_DRIVER_H__
/* firmware stuff */
#define OASIS_UCODE_VERS_STRING "1.2"
#define OASIS_UCODE_VERS_DATE "2006/03/27 15:10:37"
#define OASIS_UCODE_HOSTIF_ID 3
#define MOJAVE_UCODE_VERS_STRING "1.2"
#define MOJAVE_UCODE_VERS_DATE "2006/03/27 15:12:22"
#define MOJAVE_UCODE_HOSTIF_ID 3
#define GB_RCVUCODE_VERS_STRING "1.2"
#define GB_RCVUCODE_VERS_DATE "2006/03/27 15:12:15"
static u32 OasisRcvUCodeLen = 512;
static u32 GBRcvUCodeLen = 512;
#define SECTION_SIZE 65536
struct slic_spinlock {
spinlock_t lock;
unsigned long flags;
};
#define SLIC_RSPQ_PAGES_GB 10
#define SLIC_RSPQ_BUFSINPAGE (PAGE_SIZE / SLIC_RSPBUF_SIZE)
struct slic_rspqueue {
u32 offset;
u32 pageindex;
u32 num_pages;
struct slic_rspbuf *rspbuf;
u32 *vaddr[SLIC_RSPQ_PAGES_GB];
dma_addr_t paddr[SLIC_RSPQ_PAGES_GB];
};
#define SLIC_RCVQ_EXPANSION 1
#define SLIC_RCVQ_ENTRIES (256 * SLIC_RCVQ_EXPANSION)
#define SLIC_RCVQ_MINENTRIES (SLIC_RCVQ_ENTRIES / 2)
#define SLIC_RCVQ_MAX_PROCESS_ISR ((SLIC_RCVQ_ENTRIES * 4))
#define SLIC_RCVQ_RCVBUFSIZE 2048
#define SLIC_RCVQ_FILLENTRIES (16 * SLIC_RCVQ_EXPANSION)
#define SLIC_RCVQ_FILLTHRESH (SLIC_RCVQ_ENTRIES - SLIC_RCVQ_FILLENTRIES)
struct slic_rcvqueue {
struct sk_buff *head;
struct sk_buff *tail;
u32 count;
u32 size;
u32 errors;
};
struct slic_rcvbuf_info {
u32 id;
u32 starttime;
u32 stoptime;
u32 slicworld;
u32 lasttime;
u32 lastid;
};
/*
SLIC Handle structure. Used to restrict handle values to
32 bits by using an index rather than an address.
Simplifies ucode in 64-bit systems
*/
struct slic_handle_word {
union {
struct {
ushort index;
ushort bottombits; /* to denote num bufs to card */
} parts;
u32 whole;
} handle;
};
struct slic_handle {
struct slic_handle_word token; /* token passed between host and card*/
ushort type;
void *address; /* actual address of the object*/
ushort offset;
struct slic_handle *other_handle;
struct slic_handle *next;
};
#define SLIC_HANDLE_FREE 0x0000
#define SLIC_HANDLE_DATA 0x0001
#define SLIC_HANDLE_CMD 0x0002
#define SLIC_HANDLE_CONTEXT 0x0003
#define SLIC_HANDLE_TEAM 0x0004
#define handle_index handle.parts.index
#define handle_bottom handle.parts.bottombits
#define handle_token handle.whole
#define SLIC_HOSTCMD_SIZE 512
struct slic_hostcmd {
struct slic_host64_cmd cmd64;
u32 type;
struct sk_buff *skb;
u32 paddrl;
u32 paddrh;
u32 busy;
u32 cmdsize;
ushort numbufs;
struct slic_handle *pslic_handle;/* handle associated with command */
struct slic_hostcmd *next;
struct slic_hostcmd *next_all;
};
#define SLIC_CMDQ_CMDSINPAGE (PAGE_SIZE / SLIC_HOSTCMD_SIZE)
#define SLIC_CMD_DUMB 3
#define SLIC_CMDQ_INITCMDS 256
#define SLIC_CMDQ_MAXCMDS 256
#define SLIC_CMDQ_MAXOUTSTAND SLIC_CMDQ_MAXCMDS
#define SLIC_CMDQ_MAXPAGES (SLIC_CMDQ_MAXCMDS / SLIC_CMDQ_CMDSINPAGE)
#define SLIC_CMDQ_INITPAGES (SLIC_CMDQ_INITCMDS / SLIC_CMDQ_CMDSINPAGE)
struct slic_cmdqmem {
int pagecnt;
u32 *pages[SLIC_CMDQ_MAXPAGES];
dma_addr_t dma_pages[SLIC_CMDQ_MAXPAGES];
};
struct slic_cmdqueue {
struct slic_hostcmd *head;
struct slic_hostcmd *tail;
int count;
struct slic_spinlock lock;
};
#define SLIC_MAX_CARDS 32
#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
struct mcast_address {
unsigned char address[6];
struct mcast_address *next;
};
#define CARD_DOWN 0x00000000
#define CARD_UP 0x00000001
#define CARD_FAIL 0x00000002
#define CARD_DIAG 0x00000003
#define CARD_SLEEP 0x00000004
#define ADAPT_DOWN 0x00
#define ADAPT_UP 0x01
#define ADAPT_FAIL 0x02
#define ADAPT_RESET 0x03
#define ADAPT_SLEEP 0x04
#define ADAPT_FLAGS_BOOTTIME 0x0001
#define ADAPT_FLAGS_IS64BIT 0x0002
#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
#define ADAPT_FLAGS_FIBERMEDIA 0x0008
#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
#define ADAPT_FLAGS_INT_REGISTERED 0x0020
#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
#define LINK_DOWN 0x00
#define LINK_CONFIG 0x01
#define LINK_UP 0x02
#define LINK_10MB 0x00
#define LINK_100MB 0x01
#define LINK_AUTOSPEED 0x02
#define LINK_1000MB 0x03
#define LINK_10000MB 0x04
#define LINK_HALFD 0x00
#define LINK_FULLD 0x01
#define LINK_AUTOD 0x02
#define MAC_DIRECTED 0x00000001
#define MAC_BCAST 0x00000002
#define MAC_MCAST 0x00000004
#define MAC_PROMISC 0x00000008
#define MAC_LOOPBACK 0x00000010
#define MAC_ALLMCAST 0x00000020
#define SLIC_DUPLEX(x) ((x == LINK_FULLD) ? "FDX" : "HDX")
#define SLIC_SPEED(x) ((x == LINK_100MB) ? "100Mb" : ((x == LINK_1000MB) ?\
"1000Mb" : " 10Mb"))
#define SLIC_LINKSTATE(x) ((x == LINK_DOWN) ? "Down" : "Up ")
#define SLIC_ADAPTER_STATE(x) ((x == ADAPT_UP) ? "UP" : "Down")
#define SLIC_CARD_STATE(x) ((x == CARD_UP) ? "UP" : "Down")
struct slic_iface_stats {
/*
* Stats
*/
u64 xmt_bytes;
u64 xmt_ucast;
u64 xmt_mcast;
u64 xmt_bcast;
u64 xmt_errors;
u64 xmt_discards;
u64 xmit_collisions;
u64 xmit_excess_xmit_collisions;
u64 rcv_bytes;
u64 rcv_ucast;
u64 rcv_mcast;
u64 rcv_bcast;
u64 rcv_errors;
u64 rcv_discards;
};
struct sliccp_stats {
u64 xmit_tcp_segs;
u64 xmit_tcp_bytes;
u64 rcv_tcp_segs;
u64 rcv_tcp_bytes;
};
struct slicnet_stats {
struct sliccp_stats tcp;
struct slic_iface_stats iface;
};
#define SLIC_LOADTIMER_PERIOD 1
#define SLIC_INTAGG_DEFAULT 200
#define SLIC_LOAD_0 0
#define SLIC_INTAGG_0 0
#define SLIC_LOAD_1 8000
#define SLIC_LOAD_2 10000
#define SLIC_LOAD_3 12000
#define SLIC_LOAD_4 14000
#define SLIC_LOAD_5 16000
#define SLIC_INTAGG_1 50
#define SLIC_INTAGG_2 100
#define SLIC_INTAGG_3 150
#define SLIC_INTAGG_4 200
#define SLIC_INTAGG_5 250
#define SLIC_LOAD_1GB 3000
#define SLIC_LOAD_2GB 6000
#define SLIC_LOAD_3GB 12000
#define SLIC_LOAD_4GB 24000
#define SLIC_LOAD_5GB 48000
#define SLIC_INTAGG_1GB 50
#define SLIC_INTAGG_2GB 75
#define SLIC_INTAGG_3GB 100
#define SLIC_INTAGG_4GB 100
#define SLIC_INTAGG_5GB 100
struct ether_header {
unsigned char ether_dhost[6];
unsigned char ether_shost[6];
ushort ether_type;
};
struct sliccard {
uint busnumber;
uint slotnumber;
uint state;
uint cardnum;
uint card_size;
uint adapters_activated;
uint adapters_allocated;
uint adapters_sleeping;
uint gennumber;
u32 events;
u32 loadlevel_current;
u32 load;
uint reset_in_progress;
u32 pingstatus;
u32 bad_pingstatus;
struct timer_list loadtimer;
u32 loadtimerset;
uint config_set;
struct slic_config config;
struct dentry *debugfs_dir;
struct dentry *debugfs_cardinfo;
struct adapter *master;
struct adapter *adapter[SLIC_MAX_PORTS];
struct sliccard *next;
u32 error_interrupts;
u32 error_rmiss_interrupts;
u32 rcv_interrupts;
u32 xmit_interrupts;
u32 num_isrs;
u32 false_interrupts;
u32 max_isr_rcvs;
u32 max_isr_xmits;
u32 rcv_interrupt_yields;
u32 tx_packets;
u32 debug_ix;
ushort reg_type[32];
ushort reg_offset[32];
u32 reg_value[32];
u32 reg_valueh[32];
};
#define NUM_CFG_SPACES 2
#define NUM_CFG_REGS 64
#define NUM_CFG_REG_ULONGS (NUM_CFG_REGS / sizeof(u32))
struct physcard {
struct adapter *adapter[SLIC_MAX_PORTS];
struct physcard *next;
uint adapters_allocd;
/* the following is not currently needed
u32 bridge_busnum;
u32 bridge_cfg[NUM_CFG_SPACES][NUM_CFG_REG_ULONGS];
*/
};
struct base_driver {
struct slic_spinlock driver_lock;
u32 num_slic_cards;
u32 num_slic_ports;
u32 num_slic_ports_active;
u32 dynamic_intagg;
struct sliccard *slic_card;
struct physcard *phys_card;
uint cardnuminuse[SLIC_MAX_CARDS];
};
struct slic_shmem {
volatile u32 isr;
volatile u32 linkstatus;
volatile struct slic_stats inicstats;
};
struct slic_reg_params {
u32 linkspeed;
u32 linkduplex;
u32 fail_on_bad_eeprom;
};
struct slic_upr {
uint adapter;
u32 upr_request;
u32 upr_data;
u32 upr_data_h;
u32 upr_buffer;
u32 upr_buffer_h;
struct slic_upr *next;
};
struct slic_ifevents {
uint oflow802;
uint uflow802;
uint Tprtoflow;
uint rcvearly;
uint Bufov;
uint Carre;
uint Longe;
uint Invp;
uint Crc;
uint Drbl;
uint Code;
uint IpHlen;
uint IpLen;
uint IpCsum;
uint TpCsum;
uint TpHlen;
};
struct adapter {
void *ifp;
struct sliccard *card;
uint port;
struct physcard *physcard;
uint physport;
uint cardindex;
uint card_size;
uint chipid;
struct net_device *netdev;
struct net_device *next_netdevice;
struct slic_spinlock adapter_lock;
struct slic_spinlock reset_lock;
struct pci_dev *pcidev;
uint busnumber;
uint slotnumber;
uint functionnumber;
ushort vendid;
ushort devid;
ushort subsysid;
u32 irq;
void __iomem *memorybase;
u32 memorylength;
u32 drambase;
u32 dramlength;
uint queues_initialized;
uint allocated;
uint activated;
u32 intrregistered;
uint isp_initialized;
uint gennumber;
u32 curaddrupper;
struct slic_shmem *pshmem;
dma_addr_t phys_shmem;
u32 isrcopy;
__iomem struct slic_regs *slic_regs;
unsigned char state;
unsigned char linkstate;
unsigned char linkspeed;
unsigned char linkduplex;
uint flags;
unsigned char macaddr[6];
unsigned char currmacaddr[6];
u32 macopts;
ushort devflags_prev;
u64 mcastmask;
struct mcast_address *mcastaddrs;
struct slic_upr *upr_list;
uint upr_busy;
struct timer_list pingtimer;
u32 pingtimerset;
struct timer_list loadtimer;
u32 loadtimerset;
struct dentry *debugfs_entry;
struct slic_spinlock upr_lock;
struct slic_spinlock bit64reglock;
struct slic_rspqueue rspqueue;
struct slic_rcvqueue rcvqueue;
struct slic_cmdqueue cmdq_free;
struct slic_cmdqueue cmdq_done;
struct slic_cmdqueue cmdq_all;
struct slic_cmdqmem cmdqmem;
/*
* SLIC Handles
*/
struct slic_handle slic_handles[SLIC_CMDQ_MAXCMDS+1]; /* Object handles*/
struct slic_handle *pfree_slic_handles; /* Free object handles*/
struct slic_spinlock handle_lock; /* Object handle list lock*/
ushort slic_handle_ix;
u32 xmitq_full;
u32 all_reg_writes;
u32 icr_reg_writes;
u32 isr_reg_writes;
u32 error_interrupts;
u32 error_rmiss_interrupts;
u32 rx_errors;
u32 rcv_drops;
u32 rcv_interrupts;
u32 xmit_interrupts;
u32 linkevent_interrupts;
u32 upr_interrupts;
u32 num_isrs;
u32 false_interrupts;
u32 tx_packets;
u32 xmit_completes;
u32 tx_drops;
u32 rcv_broadcasts;
u32 rcv_multicasts;
u32 rcv_unicasts;
u32 max_isr_rcvs;
u32 max_isr_xmits;
u32 rcv_interrupt_yields;
u32 intagg_period;
struct inicpm_state *inicpm_info;
void *pinicpm_info;
struct slic_reg_params reg_params;
struct slic_ifevents if_events;
struct slic_stats inicstats_prev;
struct slicnet_stats slic_stats;
};
#define UPDATE_STATS(largestat, newstat, oldstat) \
{ \
if ((newstat) < (oldstat)) \
(largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
else \
(largestat) += ((newstat) - (oldstat)); \
}
#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
{ \
(largestat) += ((newstat) - (oldstat)); \
}
#if BITS_PER_LONG == 64
#define SLIC_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & \
0x00000000FFFFFFFF)
#define SLIC_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & \
0x00000000FFFFFFFF)
#elif BITS_PER_LONG == 32
#define SLIC_GET_ADDR_LOW(_addr) (u32)(_addr)
#define SLIC_GET_ADDR_HIGH(_addr) (u32)0
#else
#error BITS_PER_LONG must be 32 or 64
#endif
#define FLUSH true
#define DONT_FLUSH false
#define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
#define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
#define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
#endif /* __SLIC_DRIVER_H__ */

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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slichw.h
*
* This header file contains definitions that are common to our hardware.
*/
#ifndef __SLICHW_H__
#define __SLICHW_H__
#define PCI_VENDOR_ID_ALACRITECH 0x139A
#define SLIC_1GB_DEVICE_ID 0x0005
#define SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */
#define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
#define SLIC_NBR_MACS 4
#define SLIC_RCVBUF_SIZE 2048
#define SLIC_RCVBUF_HEADSIZE 34
#define SLIC_RCVBUF_TAILSIZE 0
#define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - \
(SLIC_RCVBUF_HEADSIZE + \
SLIC_RCVBUF_TAILSIZE))
#define VGBSTAT_XPERR 0x40000000
#define VGBSTAT_XERRSHFT 25
#define VGBSTAT_XCSERR 0x23
#define VGBSTAT_XUFLOW 0x22
#define VGBSTAT_XHLEN 0x20
#define VGBSTAT_NETERR 0x01000000
#define VGBSTAT_NERRSHFT 16
#define VGBSTAT_NERRMSK 0x1ff
#define VGBSTAT_NCSERR 0x103
#define VGBSTAT_NUFLOW 0x102
#define VGBSTAT_NHLEN 0x100
#define VGBSTAT_LNKERR 0x00000080
#define VGBSTAT_LERRMSK 0xff
#define VGBSTAT_LDEARLY 0x86
#define VGBSTAT_LBOFLO 0x85
#define VGBSTAT_LCODERR 0x84
#define VGBSTAT_LDBLNBL 0x83
#define VGBSTAT_LCRCERR 0x82
#define VGBSTAT_LOFLO 0x81
#define VGBSTAT_LUFLO 0x80
#define IRHDDR_FLEN_MSK 0x0000ffff
#define IRHDDR_SVALID 0x80000000
#define IRHDDR_ERR 0x10000000
#define VRHSTAT_802OE 0x80000000
#define VRHSTAT_TPOFLO 0x10000000
#define VRHSTATB_802UE 0x80000000
#define VRHSTATB_RCVE 0x40000000
#define VRHSTATB_BUFF 0x20000000
#define VRHSTATB_CARRE 0x08000000
#define VRHSTATB_LONGE 0x02000000
#define VRHSTATB_PREA 0x01000000
#define VRHSTATB_CRC 0x00800000
#define VRHSTATB_DRBL 0x00400000
#define VRHSTATB_CODE 0x00200000
#define VRHSTATB_TPCSUM 0x00100000
#define VRHSTATB_TPHLEN 0x00080000
#define VRHSTATB_IPCSUM 0x00040000
#define VRHSTATB_IPLERR 0x00020000
#define VRHSTATB_IPHERR 0x00010000
#define SLIC_MAX64_BCNT 23
#define SLIC_MAX32_BCNT 26
#define IHCMD_XMT_REQ 0x01
#define IHFLG_IFSHFT 2
#define SLIC_RSPBUF_SIZE 32
#define SLIC_RESET_MAGIC 0xDEAD
#define ICR_INT_OFF 0
#define ICR_INT_ON 1
#define ICR_INT_MASK 2
#define ISR_ERR 0x80000000
#define ISR_RCV 0x40000000
#define ISR_CMD 0x20000000
#define ISR_IO 0x60000000
#define ISR_UPC 0x10000000
#define ISR_LEVENT 0x08000000
#define ISR_RMISS 0x02000000
#define ISR_UPCERR 0x01000000
#define ISR_XDROP 0x00800000
#define ISR_UPCBSY 0x00020000
#define ISR_EVMSK 0xffff0000
#define ISR_PINGMASK 0x00700000
#define ISR_PINGDSMASK 0x00710000
#define ISR_UPCMASK 0x11000000
#define SLIC_WCS_START 0x80000000
#define SLIC_WCS_COMPARE 0x40000000
#define SLIC_RCVWCS_BEGIN 0x40000000
#define SLIC_RCVWCS_FINISH 0x80000000
#define SLIC_PM_MAXPATTERNS 6
#define SLIC_PM_PATTERNSIZE 128
#define SLIC_PMCAPS_WAKEONLAN 0x00000001
#define MIICR_REG_PCR 0x00000000
#define MIICR_REG_4 0x00040000
#define MIICR_REG_9 0x00090000
#define MIICR_REG_16 0x00100000
#define PCR_RESET 0x8000
#define PCR_POWERDOWN 0x0800
#define PCR_SPEED_100 0x2000
#define PCR_SPEED_1000 0x0040
#define PCR_AUTONEG 0x1000
#define PCR_AUTONEG_RST 0x0200
#define PCR_DUPLEX_FULL 0x0100
#define PSR_LINKUP 0x0004
#define PAR_ADV100FD 0x0100
#define PAR_ADV100HD 0x0080
#define PAR_ADV10FD 0x0040
#define PAR_ADV10HD 0x0020
#define PAR_ASYMPAUSE 0x0C00
#define PAR_802_3 0x0001
#define PAR_ADV1000XFD 0x0020
#define PAR_ADV1000XHD 0x0040
#define PAR_ASYMPAUSE_FIBER 0x0180
#define PGC_ADV1000FD 0x0200
#define PGC_ADV1000HD 0x0100
#define SEEQ_LINKFAIL 0x4000
#define SEEQ_SPEED 0x0080
#define SEEQ_DUPLEX 0x0040
#define TDK_DUPLEX 0x0800
#define TDK_SPEED 0x0400
#define MRV_REG16_XOVERON 0x0068
#define MRV_REG16_XOVEROFF 0x0008
#define MRV_SPEED_1000 0x8000
#define MRV_SPEED_100 0x4000
#define MRV_SPEED_10 0x0000
#define MRV_FULLDUPLEX 0x2000
#define MRV_LINKUP 0x0400
#define GIG_LINKUP 0x0001
#define GIG_FULLDUPLEX 0x0002
#define GIG_SPEED_MASK 0x000C
#define GIG_SPEED_1000 0x0008
#define GIG_SPEED_100 0x0004
#define GIG_SPEED_10 0x0000
#define MCR_RESET 0x80000000
#define MCR_CRCEN 0x40000000
#define MCR_FULLD 0x10000000
#define MCR_PAD 0x02000000
#define MCR_RETRYLATE 0x01000000
#define MCR_BOL_SHIFT 21
#define MCR_IPG1_SHIFT 14
#define MCR_IPG2_SHIFT 7
#define MCR_IPG3_SHIFT 0
#define GMCR_RESET 0x80000000
#define GMCR_GBIT 0x20000000
#define GMCR_FULLD 0x10000000
#define GMCR_GAPBB_SHIFT 14
#define GMCR_GAPR1_SHIFT 7
#define GMCR_GAPR2_SHIFT 0
#define GMCR_GAPBB_1000 0x60
#define GMCR_GAPR1_1000 0x2C
#define GMCR_GAPR2_1000 0x40
#define GMCR_GAPBB_100 0x70
#define GMCR_GAPR1_100 0x2C
#define GMCR_GAPR2_100 0x40
#define XCR_RESET 0x80000000
#define XCR_XMTEN 0x40000000
#define XCR_PAUSEEN 0x20000000
#define XCR_LOADRNG 0x10000000
#define RCR_RESET 0x80000000
#define RCR_RCVEN 0x40000000
#define RCR_RCVALL 0x20000000
#define RCR_RCVBAD 0x10000000
#define RCR_CTLEN 0x08000000
#define RCR_ADDRAEN 0x02000000
#define GXCR_RESET 0x80000000
#define GXCR_XMTEN 0x40000000
#define GXCR_PAUSEEN 0x20000000
#define GRCR_RESET 0x80000000
#define GRCR_RCVEN 0x40000000
#define GRCR_RCVALL 0x20000000
#define GRCR_RCVBAD 0x10000000
#define GRCR_CTLEN 0x08000000
#define GRCR_ADDRAEN 0x02000000
#define GRCR_HASHSIZE_SHIFT 17
#define GRCR_HASHSIZE 14
#define SLIC_EEPROM_ID 0xA5A5
#define SLIC_SRAM_SIZE2GB (64 * 1024)
#define SLIC_SRAM_SIZE1GB (32 * 1024)
#define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
#define SLIC_NBR_MACS 4
struct slic_rcvbuf {
u8 pad1[6];
u16 pad2;
u32 pad3;
u32 pad4;
u32 buffer;
u32 length;
u32 status;
u32 pad5;
u16 pad6;
u8 data[SLIC_RCVBUF_DATASIZE];
};
struct slic_hddr_wds {
union {
struct {
u32 frame_status;
u32 frame_status_b;
u32 time_stamp;
u32 checksum;
} hdrs_14port;
struct {
u32 frame_status;
u16 ByteCnt;
u16 TpChksum;
u16 CtxHash;
u16 MacHash;
u32 BufLnk;
} hdrs_gbit;
} u0;
};
#define frame_status14 u0.hdrs_14port.frame_status
#define frame_status_b14 u0.hdrs_14port.frame_status_b
#define frame_statusGB u0.hdrs_gbit.frame_status
struct slic_host64sg {
u32 paddrl;
u32 paddrh;
u32 length;
};
struct slic_host64_cmd {
u32 hosthandle;
u32 RSVD;
u8 command;
u8 flags;
union {
u16 rsv1;
u16 rsv2;
} u0;
union {
struct {
u32 totlen;
struct slic_host64sg bufs[SLIC_MAX64_BCNT];
} slic_buffers;
} u;
};
struct slic_rspbuf {
u32 hosthandle;
u32 pad0;
u32 pad1;
u32 status;
u32 pad2[4];
};
struct slic_regs {
u32 slic_reset; /* Reset Register */
u32 pad0;
u32 slic_icr; /* Interrupt Control Register */
u32 pad2;
#define SLIC_ICR 0x0008
u32 slic_isp; /* Interrupt status pointer */
u32 pad1;
#define SLIC_ISP 0x0010
u32 slic_isr; /* Interrupt status */
u32 pad3;
#define SLIC_ISR 0x0018
u32 slic_hbar; /* Header buffer address reg */
u32 pad4;
/* 31-8 - phy addr of set of contiguous hdr buffers
7-0 - number of buffers passed
Buffers are 256 bytes long on 256-byte boundaries. */
#define SLIC_HBAR 0x0020
#define SLIC_HBAR_CNT_MSK 0x000000FF
u32 slic_dbar; /* Data buffer handle & address reg */
u32 pad5;
/* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
#define SLIC_DBAR 0x0028
#define SLIC_DBAR_SIZE 2048
u32 slic_cbar; /* Xmt Cmd buf addr regs.*/
/* 1 per XMT interface
31-5 - phy addr of host command buffer
4-0 - length of cmd in multiples of 32 bytes
Buffers are 32 bytes up to 512 bytes long */
#define SLIC_CBAR 0x0030
#define SLIC_CBAR_LEN_MSK 0x0000001F
#define SLIC_CBAR_ALIGN 0x00000020
u32 slic_wcs; /* write control store*/
#define SLIC_WCS 0x0034
#define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
#define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
u32 slic_rbar; /* Response buffer address reg.*/
u32 pad7;
/*31-8 - phy addr of set of contiguous response buffers
7-0 - number of buffers passed
Buffers are 32 bytes long on 32-byte boundaries.*/
#define SLIC_RBAR 0x0038
#define SLIC_RBAR_CNT_MSK 0x000000FF
#define SLIC_RBAR_SIZE 32
u32 slic_stats; /* read statistics (UPR) */
u32 pad8;
#define SLIC_RSTAT 0x0040
u32 slic_rlsr; /* read link status */
u32 pad9;
#define SLIC_LSTAT 0x0048
u32 slic_wmcfg; /* Write Mac Config */
u32 pad10;
#define SLIC_WMCFG 0x0050
u32 slic_wphy; /* Write phy register */
u32 pad11;
#define SLIC_WPHY 0x0058
u32 slic_rcbar; /* Rcv Cmd buf addr reg */
u32 pad12;
#define SLIC_RCBAR 0x0060
u32 slic_rconfig; /* Read SLIC Config*/
u32 pad13;
#define SLIC_RCONFIG 0x0068
u32 slic_intagg; /* Interrupt aggregation time */
u32 pad14;
#define SLIC_INTAGG 0x0070
u32 slic_wxcfg; /* Write XMIT config reg*/
u32 pad16;
#define SLIC_WXCFG 0x0078
u32 slic_wrcfg; /* Write RCV config reg*/
u32 pad17;
#define SLIC_WRCFG 0x0080
u32 slic_wraddral; /* Write rcv addr a low*/
u32 pad18;
#define SLIC_WRADDRAL 0x0088
u32 slic_wraddrah; /* Write rcv addr a high*/
u32 pad19;
#define SLIC_WRADDRAH 0x0090
u32 slic_wraddrbl; /* Write rcv addr b low*/
u32 pad20;
#define SLIC_WRADDRBL 0x0098
u32 slic_wraddrbh; /* Write rcv addr b high*/
u32 pad21;
#define SLIC_WRADDRBH 0x00a0
u32 slic_mcastlow; /* Low bits of mcast mask*/
u32 pad22;
#define SLIC_MCASTLOW 0x00a8
u32 slic_mcasthigh; /* High bits of mcast mask*/
u32 pad23;
#define SLIC_MCASTHIGH 0x00b0
u32 slic_ping; /* Ping the card*/
u32 pad24;
#define SLIC_PING 0x00b8
u32 slic_dump_cmd; /* Dump command */
u32 pad25;
#define SLIC_DUMP_CMD 0x00c0
u32 slic_dump_data; /* Dump data pointer */
u32 pad26;
#define SLIC_DUMP_DATA 0x00c8
u32 slic_pcistatus; /* Read card's pci_status register */
u32 pad27;
#define SLIC_PCISTATUS 0x00d0
u32 slic_wrhostid; /* Write hostid field */
u32 pad28;
#define SLIC_WRHOSTID 0x00d8
#define SLIC_RDHOSTID_1GB 0x1554
#define SLIC_RDHOSTID_2GB 0x1554
u32 slic_low_power; /* Put card in a low power state */
u32 pad29;
#define SLIC_LOW_POWER 0x00e0
u32 slic_quiesce; /* force slic into quiescent state
before soft reset */
u32 pad30;
#define SLIC_QUIESCE 0x00e8
u32 slic_reset_iface;/* reset interface queues */
u32 pad31;
#define SLIC_RESET_IFACE 0x00f0
u32 slic_addr_upper;/* Bits 63-32 for host i/f addrs */
u32 pad32;
#define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
u32 slic_hbar64; /* 64 bit Header buffer address reg */
u32 pad33;
#define SLIC_HBAR64 0x0100
u32 slic_dbar64; /* 64 bit Data buffer handle & address reg */
u32 pad34;
#define SLIC_DBAR64 0x0108
u32 slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
u32 pad35;
#define SLIC_CBAR64 0x0110
u32 slic_rbar64; /* 64 bit Response buffer address reg.*/
u32 pad36;
#define SLIC_RBAR64 0x0118
u32 slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
u32 pad37;
#define SLIC_RCBAR64 0x0120
u32 slic_stats64; /* read statistics (64 bit UPR) */
u32 pad38;
#define SLIC_RSTAT64 0x0128
u32 slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
u32 pad39;
#define SLIC_RCV_WCS 0x0130
#define SLIC_RCVWCS_BEGIN 0x40000000
#define SLIC_RCVWCS_FINISH 0x80000000
u32 slic_wrvlanid; /* Write VlanId field */
u32 pad40;
#define SLIC_WRVLANID 0x0138
u32 slic_read_xf_info; /* Read Transformer info */
u32 pad41;
#define SLIC_READ_XF_INFO 0x0140
u32 slic_write_xf_info; /* Write Transformer info */
u32 pad42;
#define SLIC_WRITE_XF_INFO 0x0148
u32 RSVD1; /* TOE Only */
u32 pad43;
u32 RSVD2; /* TOE Only */
u32 pad44;
u32 RSVD3; /* TOE Only */
u32 pad45;
u32 RSVD4; /* TOE Only */
u32 pad46;
u32 slic_ticks_per_sec; /* Write card ticks per second */
u32 pad47;
#define SLIC_TICKS_PER_SEC 0x0170
};
enum UPR_REQUEST {
SLIC_UPR_STATS,
SLIC_UPR_RLSR,
SLIC_UPR_WCFG,
SLIC_UPR_RCONFIG,
SLIC_UPR_RPHY,
SLIC_UPR_ENLB,
SLIC_UPR_ENCT,
SLIC_UPR_PDWN,
SLIC_UPR_PING,
SLIC_UPR_DUMP,
};
struct inicpm_wakepattern {
u32 patternlength;
u8 pattern[SLIC_PM_PATTERNSIZE];
u8 mask[SLIC_PM_PATTERNSIZE];
};
struct inicpm_state {
u32 powercaps;
u32 powerstate;
u32 wake_linkstatus;
u32 wake_magicpacket;
u32 wake_framepattern;
struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
};
struct slicpm_packet_pattern {
u32 priority;
u32 reserved;
u32 masksize;
u32 patternoffset;
u32 patternsize;
u32 patternflags;
};
enum slicpm_power_state {
slicpm_state_unspecified = 0,
slicpm_state_d0,
slicpm_state_d1,
slicpm_state_d2,
slicpm_state_d3,
slicpm_state_maximum
};
struct slicpm_wakeup_capabilities {
enum slicpm_power_state min_magic_packet_wakeup;
enum slicpm_power_state min_pattern_wakeup;
enum slicpm_power_state min_link_change_wakeup;
};
struct slic_pnp_capabilities {
u32 flags;
struct slicpm_wakeup_capabilities wakeup_capabilities;
};
struct xmt_stats {
u32 xmit_tcp_bytes;
u32 xmit_tcp_segs;
u32 xmit_bytes;
u32 xmit_collisions;
u32 xmit_unicasts;
u32 xmit_other_error;
u32 xmit_excess_collisions;
};
struct rcv_stats {
u32 rcv_tcp_bytes;
u32 rcv_tcp_segs;
u32 rcv_bytes;
u32 rcv_unicasts;
u32 rcv_other_error;
u32 rcv_drops;
};
struct xmt_statsgb {
u64 xmit_tcp_bytes;
u64 xmit_tcp_segs;
u64 xmit_bytes;
u64 xmit_collisions;
u64 xmit_unicasts;
u64 xmit_other_error;
u64 xmit_excess_collisions;
};
struct rcv_statsgb {
u64 rcv_tcp_bytes;
u64 rcv_tcp_segs;
u64 rcv_bytes;
u64 rcv_unicasts;
u64 rcv_other_error;
u64 rcv_drops;
};
struct slic_stats {
union {
struct {
struct xmt_stats xmt100;
struct rcv_stats rcv100;
} stats_100;
struct {
struct xmt_statsgb xmtGB;
struct rcv_statsgb rcvGB;
} stats_GB;
} u;
};
#define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
#define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
#define xmit_bytes100 u.stats_100.xmt100.xmit_bytes
#define xmit_collisions100 u.stats_100.xmt100.xmit_collisions
#define xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts
#define xmit_other_error100 u.stats_100.xmt100.xmit_other_error
#define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions
#define rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs
#define rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes
#define rcv_bytes100 u.stats_100.rcv100.rcv_bytes
#define rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts
#define rcv_other_error100 u.stats_100.rcv100.rcv_other_error
#define rcv_drops100 u.stats_100.rcv100.rcv_drops
#define xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs
#define xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes
#define xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes
#define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions
#define xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts
#define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error
#define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions
#define rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs
#define rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes
#define rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes
#define rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts
#define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
#define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
struct slic_config_mac {
u8 macaddrA[6];
};
#define ATK_FRU_FORMAT 0x00
#define VENDOR1_FRU_FORMAT 0x01
#define VENDOR2_FRU_FORMAT 0x02
#define VENDOR3_FRU_FORMAT 0x03
#define VENDOR4_FRU_FORMAT 0x04
#define NO_FRU_FORMAT 0xFF
struct atk_fru {
u8 assembly[6];
u8 revision[2];
u8 serial[14];
u8 pad[3];
};
struct vendor1_fru {
u8 commodity;
u8 assembly[4];
u8 revision[2];
u8 supplier[2];
u8 date[2];
u8 sequence[3];
u8 pad[13];
};
struct vendor2_fru {
u8 part[8];
u8 supplier[5];
u8 date[3];
u8 sequence[4];
u8 pad[7];
};
struct vendor3_fru {
u8 assembly[6];
u8 revision[2];
u8 serial[14];
u8 pad[3];
};
struct vendor4_fru {
u8 number[8];
u8 part[8];
u8 version[8];
u8 pad[3];
};
union oemfru {
struct vendor1_fru vendor1_fru;
struct vendor2_fru vendor2_fru;
struct vendor3_fru vendor3_fru;
struct vendor4_fru vendor4_fru;
};
/*
* SLIC EEPROM structure for Mojave
*/
struct slic_eeprom {
u16 Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
u16 EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
u16 FlashSize; /* 02 Flash size */
u16 EepromSize; /* 03 EEPROM Size */
u16 VendorId; /* 04 Vendor ID */
u16 DeviceId; /* 05 Device ID */
u8 RevisionId; /* 06 Revision ID */
u8 ClassCode[3]; /* 07 Class Code */
u8 DbgIntPin; /* 08 Debug Interrupt pin */
u8 NetIntPin0; /* Network Interrupt Pin */
u8 MinGrant; /* 09 Minimum grant */
u8 MaxLat; /* Maximum Latency */
u16 PciStatus; /* 10 PCI Status */
u16 SubSysVId; /* 11 Subsystem Vendor Id */
u16 SubSysId; /* 12 Subsystem ID */
u16 DbgDevId; /* 13 Debug Device Id */
u16 DramRomFn; /* 14 Dram/Rom function */
u16 DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
u16 RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
u8 NetIntPin1; /* 17 Network Interface Pin 1
(simba/leone only) */
u8 NetIntPin2; /* Network Interface Pin 2 (simba/leone only)*/
union {
u8 NetIntPin3; /* 18 Network Interface Pin 3 (simba only) */
u8 FreeTime; /* FreeTime setting (leone/mojave only) */
} u1;
u8 TBIctl; /* 10-bit interface control (Mojave only) */
u16 DramSize; /* 19 DRAM size (bytes * 64k) */
union {
struct {
/* Mac Interface Specific portions */
struct slic_config_mac MacInfo[SLIC_NBR_MACS];
} mac; /* MAC access for all boards */
struct {
/* use above struct for MAC access */
struct slic_config_mac pad[SLIC_NBR_MACS - 1];
u16 DeviceId2; /* Device ID for 2nd PCI function */
u8 IntPin2; /* Interrupt pin for 2nd PCI function */
u8 ClassCode2[3]; /* Class Code for 2nd PCI function */
} mojave; /* 2nd function access for gigabit board */
} u2;
u16 CfgByte6; /* Config Byte 6 */
u16 PMECapab; /* Power Mgment capabilities */
u16 NwClkCtrls; /* NetworkClockControls */
u8 FruFormat; /* Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
u8 OemFruFormat; /* optional OEM FRU format type */
union oemfru OemFru; /* optional OEM FRU information */
u8 Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
* (if OEM FRU info exists) and two unusable
* bytes at the end */
};
/* SLIC EEPROM structure for Oasis */
struct oslic_eeprom {
u16 Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
u16 EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
u16 FlashConfig0; /* 02 Flash Config for SPI device 0 */
u16 FlashConfig1; /* 03 Flash Config for SPI device 1 */
u16 VendorId; /* 04 Vendor ID */
u16 DeviceId; /* 05 Device ID (function 0) */
u8 RevisionId; /* 06 Revision ID */
u8 ClassCode[3]; /* 07 Class Code for PCI function 0 */
u8 IntPin1; /* 08 Interrupt pin for PCI function 1*/
u8 ClassCode2[3]; /* 09 Class Code for PCI function 1 */
u8 IntPin2; /* 10 Interrupt pin for PCI function 2*/
u8 IntPin0; /* Interrupt pin for PCI function 0*/
u8 MinGrant; /* 11 Minimum grant */
u8 MaxLat; /* Maximum Latency */
u16 SubSysVId; /* 12 Subsystem Vendor Id */
u16 SubSysId; /* 13 Subsystem ID */
u16 FlashSize; /* 14 Flash size (bytes / 4K) */
u16 DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */
u16 RSize2Pci; /* 16 Flash (ROM extension) size to PCI
(bytes / 4K) */
u16 DeviceId1; /* 17 Device Id (function 1) */
u16 DeviceId2; /* 18 Device Id (function 2) */
u16 CfgByte6; /* 19 Device Status Config Bytes 6-7 */
u16 PMECapab; /* 20 Power Mgment capabilities */
u8 MSICapab; /* 21 MSI capabilities */
u8 ClockDivider; /* Clock divider */
u16 PciStatusLow; /* 22 PCI Status bits 15:0 */
u16 PciStatusHigh; /* 23 PCI Status bits 31:16 */
u16 DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
u16 DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */
u16 DramSize; /* 26 DRAM size (bytes / 64K) */
u16 GpioTbiCtl; /* 27 GPIO/TBI controls for functions 1/0 */
u16 EepromSize; /* 28 EEPROM Size */
struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */
u8 FruFormat; /* 35 Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
u8 OemFruFormat; /* optional OEM FRU format type */
union oemfru OemFru; /* optional OEM FRU information */
u8 Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
* (if OEM FRU info exists) and two unusable
* bytes at the end
*/
};
#define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
#define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
/*
* SLIC CONFIG structure
*
* This structure lives in the CARD structure and is valid for all board types.
* It is filled in from the appropriate EEPROM structure by
* SlicGetConfigData()
*/
struct slic_config {
bool EepromValid; /* Valid EEPROM flag (checksum good?) */
u16 DramSize; /* DRAM size (bytes / 64K) */
struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
u8 FruFormat; /* Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
u8 OemFruFormat; /* optional OEM FRU format type */
union {
struct vendor1_fru vendor1_fru;
struct vendor2_fru vendor2_fru;
struct vendor3_fru vendor3_fru;
struct vendor4_fru vendor4_fru;
} OemFru;
};
#pragma pack()
#endif

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