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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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34
drivers/nfc/pn544/Kconfig Normal file
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config NFC_PN544
tristate "NXP PN544 NFC driver"
depends on NFC_HCI
select CRC_CCITT
default n
---help---
NXP PN544 core driver.
This is a driver based on the HCI NFC kernel layers and
will thus not work with NXP libnfc library.
To compile this driver as a module, choose m here. The module will
be called pn544.
Say N if unsure.
config NFC_PN544_I2C
tristate "NFC PN544 i2c support"
depends on NFC_PN544 && I2C && NFC_SHDLC
---help---
This module adds support for the NXP pn544 i2c interface.
Select this if your platform is using the i2c bus.
If you choose to build a module, it'll be called pn544_i2c.
Say N if unsure.
config NFC_PN544_MEI
tristate "NFC PN544 MEI support"
depends on NFC_PN544 && NFC_MEI_PHY
---help---
This module adds support for the mei interface of adapters using
NXP pn544 chipsets. Select this if your pn544 chipset
is handled by Intel's Management Engine Interface on your platform.
If you choose to build a module, it'll be called pn544_mei.
Say N if unsure.

10
drivers/nfc/pn544/Makefile Normal file
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#
# Makefile for PN544 HCI based NFC driver
#
pn544_i2c-objs = i2c.o
pn544_mei-objs = mei.o
obj-$(CONFIG_NFC_PN544) += pn544.o
obj-$(CONFIG_NFC_PN544_I2C) += pn544_i2c.o
obj-$(CONFIG_NFC_PN544_MEI) += pn544_mei.o

976
drivers/nfc/pn544/i2c.c Normal file
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/*
* I2C Link Layer for PN544 HCI based Driver
*
* Copyright (C) 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/crc-ccitt.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/nfc.h>
#include <linux/firmware.h>
#include <linux/unaligned/access_ok.h>
#include <linux/platform_data/pn544.h>
#include <net/nfc/hci.h>
#include <net/nfc/llc.h>
#include <net/nfc/nfc.h>
#include "pn544.h"
#define PN544_I2C_FRAME_HEADROOM 1
#define PN544_I2C_FRAME_TAILROOM 2
/* framing in HCI mode */
#define PN544_HCI_I2C_LLC_LEN 1
#define PN544_HCI_I2C_LLC_CRC 2
#define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \
PN544_HCI_I2C_LLC_CRC)
#define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC)
#define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29
#define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
PN544_HCI_I2C_LLC_MAX_PAYLOAD)
static struct i2c_device_id pn544_hci_i2c_id_table[] = {
{"pn544", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
#define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
/*
* Exposed through the 4 most significant bytes
* from the HCI SW_VERSION first byte, a.k.a.
* SW RomLib.
*/
#define PN544_HW_VARIANT_C2 0xa
#define PN544_HW_VARIANT_C3 0xb
#define PN544_FW_CMD_RESET 0x01
#define PN544_FW_CMD_WRITE 0x08
#define PN544_FW_CMD_CHECK 0x06
#define PN544_FW_CMD_SECURE_WRITE 0x0C
#define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D
struct pn544_i2c_fw_frame_write {
u8 cmd;
u16 be_length;
u8 be_dest_addr[3];
u16 be_datalen;
u8 data[];
} __packed;
struct pn544_i2c_fw_frame_check {
u8 cmd;
u16 be_length;
u8 be_start_addr[3];
u16 be_datalen;
u16 be_crc;
} __packed;
struct pn544_i2c_fw_frame_response {
u8 status;
u16 be_length;
} __packed;
struct pn544_i2c_fw_blob {
u32 be_size;
u32 be_destaddr;
u8 data[];
};
struct pn544_i2c_fw_secure_frame {
u8 cmd;
u16 be_datalen;
u8 data[];
} __packed;
struct pn544_i2c_fw_secure_blob {
u64 header;
u8 data[];
};
#define PN544_FW_CMD_RESULT_TIMEOUT 0x01
#define PN544_FW_CMD_RESULT_BAD_CRC 0x02
#define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
#define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
#define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
#define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13
#define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
#define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19
#define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D
#define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20
#define PN544_FW_CMD_RESULT_CHUNK_OK 0x21
#define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
#define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0
#define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
#define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
#define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
#define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
PN544_FW_WRITE_BUFFER_MAX_LEN)
#define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3
#define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN)
#define PN544_FW_SECURE_FRAME_HEADER_LEN 3
#define PN544_FW_SECURE_BLOB_HEADER_LEN 8
#define FW_WORK_STATE_IDLE 1
#define FW_WORK_STATE_START 2
#define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
#define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
#define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5
struct pn544_i2c_phy {
struct i2c_client *i2c_dev;
struct nfc_hci_dev *hdev;
unsigned int gpio_en;
unsigned int gpio_irq;
unsigned int gpio_fw;
unsigned int en_polarity;
u8 hw_variant;
struct work_struct fw_work;
int fw_work_state;
char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
const struct firmware *fw;
u32 fw_blob_dest_addr;
size_t fw_blob_size;
const u8 *fw_blob_data;
size_t fw_written;
size_t fw_size;
int fw_cmd_result;
int powered;
int run_mode;
int hard_fault; /*
* < 0 if hardware error occured (e.g. i2c err)
* and prevents normal operation.
*/
};
#define I2C_DUMP_SKB(info, skb) \
do { \
pr_debug("%s:\n", info); \
print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
16, 1, (skb)->data, (skb)->len, 0); \
} while (0)
static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy)
{
int polarity, retry, ret;
char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
int count = sizeof(rset_cmd);
nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n");
/* Disable fw download */
gpio_set_value(phy->gpio_fw, 0);
for (polarity = 0; polarity < 2; polarity++) {
phy->en_polarity = polarity;
retry = 3;
while (retry--) {
/* power off */
gpio_set_value(phy->gpio_en, !phy->en_polarity);
usleep_range(10000, 15000);
/* power on */
gpio_set_value(phy->gpio_en, phy->en_polarity);
usleep_range(10000, 15000);
/* send reset */
dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n");
ret = i2c_master_send(phy->i2c_dev, rset_cmd, count);
if (ret == count) {
nfc_info(&phy->i2c_dev->dev,
"nfc_en polarity : active %s\n",
(polarity == 0 ? "low" : "high"));
goto out;
}
}
}
nfc_err(&phy->i2c_dev->dev,
"Could not detect nfc_en polarity, fallback to active high\n");
out:
gpio_set_value(phy->gpio_en, !phy->en_polarity);
}
static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
{
gpio_set_value(phy->gpio_fw, run_mode == PN544_FW_MODE ? 1 : 0);
gpio_set_value(phy->gpio_en, phy->en_polarity);
usleep_range(10000, 15000);
phy->run_mode = run_mode;
}
static int pn544_hci_i2c_enable(void *phy_id)
{
struct pn544_i2c_phy *phy = phy_id;
pr_info("%s\n", __func__);
pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
phy->powered = 1;
return 0;
}
static void pn544_hci_i2c_disable(void *phy_id)
{
struct pn544_i2c_phy *phy = phy_id;
gpio_set_value(phy->gpio_fw, 0);
gpio_set_value(phy->gpio_en, !phy->en_polarity);
usleep_range(10000, 15000);
gpio_set_value(phy->gpio_en, phy->en_polarity);
usleep_range(10000, 15000);
gpio_set_value(phy->gpio_en, !phy->en_polarity);
usleep_range(10000, 15000);
phy->powered = 0;
}
static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb)
{
u16 crc;
int len;
len = skb->len + 2;
*skb_push(skb, 1) = len;
crc = crc_ccitt(0xffff, skb->data, skb->len);
crc = ~crc;
*skb_put(skb, 1) = crc & 0xff;
*skb_put(skb, 1) = crc >> 8;
}
static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb)
{
skb_pull(skb, PN544_I2C_FRAME_HEADROOM);
skb_trim(skb, PN544_I2C_FRAME_TAILROOM);
}
/*
* Writing a frame must not return the number of written bytes.
* It must return either zero for success, or <0 for error.
* In addition, it must not alter the skb
*/
static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb)
{
int r;
struct pn544_i2c_phy *phy = phy_id;
struct i2c_client *client = phy->i2c_dev;
if (phy->hard_fault != 0)
return phy->hard_fault;
usleep_range(3000, 6000);
pn544_hci_i2c_add_len_crc(skb);
I2C_DUMP_SKB("i2c frame written", skb);
r = i2c_master_send(client, skb->data, skb->len);
if (r == -EREMOTEIO) { /* Retry, chip was in standby */
usleep_range(6000, 10000);
r = i2c_master_send(client, skb->data, skb->len);
}
if (r >= 0) {
if (r != skb->len)
r = -EREMOTEIO;
else
r = 0;
}
pn544_hci_i2c_remove_len_crc(skb);
return r;
}
static int check_crc(u8 *buf, int buflen)
{
int len;
u16 crc;
len = buf[0] + 1;
crc = crc_ccitt(0xffff, buf, len - 2);
crc = ~crc;
if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
pr_err("CRC error 0x%x != 0x%x 0x%x\n",
crc, buf[len - 1], buf[len - 2]);
pr_info("%s: BAD CRC\n", __func__);
print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
16, 2, buf, buflen, false);
return -EPERM;
}
return 0;
}
/*
* Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
* that i2c bus will be flushed and that next read will start on a new frame.
* returned skb contains only LLC header and payload.
* returns:
* -EREMOTEIO : i2c read error (fatal)
* -EBADMSG : frame was incorrect and discarded
* -ENOMEM : cannot allocate skb, frame dropped
*/
static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
{
int r;
u8 len;
u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1];
struct i2c_client *client = phy->i2c_dev;
r = i2c_master_recv(client, &len, 1);
if (r != 1) {
nfc_err(&client->dev, "cannot read len byte\n");
return -EREMOTEIO;
}
if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
(len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
nfc_err(&client->dev, "invalid len byte\n");
r = -EBADMSG;
goto flush;
}
*skb = alloc_skb(1 + len, GFP_KERNEL);
if (*skb == NULL) {
r = -ENOMEM;
goto flush;
}
*skb_put(*skb, 1) = len;
r = i2c_master_recv(client, skb_put(*skb, len), len);
if (r != len) {
kfree_skb(*skb);
return -EREMOTEIO;
}
I2C_DUMP_SKB("i2c frame read", *skb);
r = check_crc((*skb)->data, (*skb)->len);
if (r != 0) {
kfree_skb(*skb);
r = -EBADMSG;
goto flush;
}
skb_pull(*skb, 1);
skb_trim(*skb, (*skb)->len - 2);
usleep_range(3000, 6000);
return 0;
flush:
if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
r = -EREMOTEIO;
usleep_range(3000, 6000);
return r;
}
static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
{
int r;
struct pn544_i2c_fw_frame_response response;
struct i2c_client *client = phy->i2c_dev;
r = i2c_master_recv(client, (char *) &response, sizeof(response));
if (r != sizeof(response)) {
nfc_err(&client->dev, "cannot read fw status\n");
return -EIO;
}
usleep_range(3000, 6000);
switch (response.status) {
case 0:
return 0;
case PN544_FW_CMD_RESULT_CHUNK_OK:
return response.status;
case PN544_FW_CMD_RESULT_TIMEOUT:
return -ETIMEDOUT;
case PN544_FW_CMD_RESULT_BAD_CRC:
return -ENODATA;
case PN544_FW_CMD_RESULT_ACCESS_DENIED:
return -EACCES;
case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
return -EPROTO;
case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
return -EINVAL;
case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND:
return -ENOTSUPP;
case PN544_FW_CMD_RESULT_INVALID_LENGTH:
return -EBADMSG;
case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR:
return -ENOKEY;
case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR:
return -EINVAL;
case PN544_FW_CMD_RESULT_MEMORY_ERROR:
return -ENOMEM;
case PN544_FW_CMD_RESULT_COMMAND_REJECTED:
return -EACCES;
case PN544_FW_CMD_RESULT_WRITE_FAILED:
case PN544_FW_CMD_RESULT_CHUNK_ERROR:
return -EIO;
default:
return -EIO;
}
}
/*
* Reads an shdlc frame from the chip. This is not as straightforward as it
* seems. There are cases where we could loose the frame start synchronization.
* The frame format is len-data-crc, and corruption can occur anywhere while
* transiting on i2c bus, such that we could read an invalid len.
* In order to recover synchronization with the next frame, we must be sure
* to read the real amount of data without using the len byte. We do this by
* assuming the following:
* - the chip will always present only one single complete frame on the bus
* before triggering the interrupt
* - the chip will not present a new frame until we have completely read
* the previous one (or until we have handled the interrupt).
* The tricky case is when we read a corrupted len that is less than the real
* len. We must detect this here in order to determine that we need to flush
* the bus. This is the reason why we check the crc here.
*/
static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
{
struct pn544_i2c_phy *phy = phy_id;
struct i2c_client *client;
struct sk_buff *skb = NULL;
int r;
if (!phy || irq != phy->i2c_dev->irq) {
WARN_ON_ONCE(1);
return IRQ_NONE;
}
client = phy->i2c_dev;
dev_dbg(&client->dev, "IRQ\n");
if (phy->hard_fault != 0)
return IRQ_HANDLED;
if (phy->run_mode == PN544_FW_MODE) {
phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
schedule_work(&phy->fw_work);
} else {
r = pn544_hci_i2c_read(phy, &skb);
if (r == -EREMOTEIO) {
phy->hard_fault = r;
nfc_hci_recv_frame(phy->hdev, NULL);
return IRQ_HANDLED;
} else if ((r == -ENOMEM) || (r == -EBADMSG)) {
return IRQ_HANDLED;
}
nfc_hci_recv_frame(phy->hdev, skb);
}
return IRQ_HANDLED;
}
static struct nfc_phy_ops i2c_phy_ops = {
.write = pn544_hci_i2c_write,
.enable = pn544_hci_i2c_enable,
.disable = pn544_hci_i2c_disable,
};
static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name,
u8 hw_variant)
{
struct pn544_i2c_phy *phy = phy_id;
pr_info("Starting Firmware Download (%s)\n", firmware_name);
strcpy(phy->firmware_name, firmware_name);
phy->hw_variant = hw_variant;
phy->fw_work_state = FW_WORK_STATE_START;
schedule_work(&phy->fw_work);
return 0;
}
static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
int result)
{
pr_info("Firmware Download Complete, result=%d\n", result);
pn544_hci_i2c_disable(phy);
phy->fw_work_state = FW_WORK_STATE_IDLE;
if (phy->fw) {
release_firmware(phy->fw);
phy->fw = NULL;
}
nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
}
static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
const u8 *data, u16 datalen)
{
u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
struct pn544_i2c_fw_frame_write *framep;
u16 params_len;
int framelen;
int r;
if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
framep = (struct pn544_i2c_fw_frame_write *) frame;
params_len = sizeof(framep->be_dest_addr) +
sizeof(framep->be_datalen) + datalen;
framelen = params_len + sizeof(framep->cmd) +
sizeof(framep->be_length);
framep->cmd = PN544_FW_CMD_WRITE;
put_unaligned_be16(params_len, &framep->be_length);
framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
framep->be_dest_addr[2] = dest_addr & 0xff;
put_unaligned_be16(datalen, &framep->be_datalen);
memcpy(framep->data, data, datalen);
r = i2c_master_send(client, frame, framelen);
if (r == framelen)
return datalen;
else if (r < 0)
return r;
else
return -EIO;
}
static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
const u8 *data, u16 datalen)
{
struct pn544_i2c_fw_frame_check frame;
int r;
u16 crc;
/* calculate local crc for the data we want to check */
crc = crc_ccitt(0xffff, data, datalen);
frame.cmd = PN544_FW_CMD_CHECK;
put_unaligned_be16(sizeof(frame.be_start_addr) +
sizeof(frame.be_datalen) + sizeof(frame.be_crc),
&frame.be_length);
/* tell the chip the memory region to which our crc applies */
frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
frame.be_start_addr[2] = start_addr & 0xff;
put_unaligned_be16(datalen, &frame.be_datalen);
/*
* and give our local crc. Chip will calculate its own crc for the
* region and compare with ours.
*/
put_unaligned_be16(crc, &frame.be_crc);
r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
if (r == sizeof(frame))
return 0;
else if (r < 0)
return r;
else
return -EIO;
}
static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
{
int r;
r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
phy->fw_blob_dest_addr + phy->fw_written,
phy->fw_blob_data + phy->fw_written,
phy->fw_blob_size - phy->fw_written);
if (r < 0)
return r;
phy->fw_written += r;
phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
return 0;
}
static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy,
const u8 *data, u16 datalen)
{
u8 buf[PN544_FW_I2C_MAX_PAYLOAD];
struct pn544_i2c_fw_secure_frame *chunk;
int chunklen;
int r;
if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN)
datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN;
chunk = (struct pn544_i2c_fw_secure_frame *) buf;
chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE;
put_unaligned_be16(datalen, &chunk->be_datalen);
memcpy(chunk->data, data, datalen);
chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen;
r = i2c_master_send(phy->i2c_dev, buf, chunklen);
if (r == chunklen)
return datalen;
else if (r < 0)
return r;
else
return -EIO;
}
static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy)
{
struct pn544_i2c_fw_secure_frame *framep;
int r;
framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data;
if (phy->fw_written == 0)
phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen)
+ PN544_FW_SECURE_FRAME_HEADER_LEN;
/* Only secure write command can be chunked*/
if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD &&
framep->cmd != PN544_FW_CMD_SECURE_WRITE)
return -EINVAL;
/* The firmware also have other commands, we just send them directly */
if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) {
r = i2c_master_send(phy->i2c_dev,
(const char *) phy->fw_blob_data, phy->fw_blob_size);
if (r == phy->fw_blob_size)
goto exit;
else if (r < 0)
return r;
else
return -EIO;
}
r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy,
phy->fw_blob_data + phy->fw_written,
phy->fw_blob_size - phy->fw_written);
if (r < 0)
return r;
exit:
phy->fw_written += r;
phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER;
/* SW reset command will not trig any response from PN544 */
if (framep->cmd == PN544_FW_CMD_RESET) {
pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
phy->fw_cmd_result = 0;
schedule_work(&phy->fw_work);
}
return 0;
}
static void pn544_hci_i2c_fw_work(struct work_struct *work)
{
struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
fw_work);
int r;
struct pn544_i2c_fw_blob *blob;
struct pn544_i2c_fw_secure_blob *secure_blob;
switch (phy->fw_work_state) {
case FW_WORK_STATE_START:
pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
r = request_firmware(&phy->fw, phy->firmware_name,
&phy->i2c_dev->dev);
if (r < 0)
goto exit_state_start;
phy->fw_written = 0;
switch (phy->hw_variant) {
case PN544_HW_VARIANT_C2:
blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
phy->fw_blob_dest_addr = get_unaligned_be32(
&blob->be_destaddr);
phy->fw_blob_data = blob->data;
r = pn544_hci_i2c_fw_write_chunk(phy);
break;
case PN544_HW_VARIANT_C3:
secure_blob = (struct pn544_i2c_fw_secure_blob *)
phy->fw->data;
phy->fw_blob_data = secure_blob->data;
phy->fw_size = phy->fw->size;
r = pn544_hci_i2c_fw_secure_write_frame(phy);
break;
default:
r = -ENOTSUPP;
break;
}
exit_state_start:
if (r < 0)
pn544_hci_i2c_fw_work_complete(phy, r);
break;
case FW_WORK_STATE_WAIT_WRITE_ANSWER:
r = phy->fw_cmd_result;
if (r < 0)
goto exit_state_wait_write_answer;
if (phy->fw_written == phy->fw_blob_size) {
r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
phy->fw_blob_dest_addr,
phy->fw_blob_data,
phy->fw_blob_size);
if (r < 0)
goto exit_state_wait_write_answer;
phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
break;
}
r = pn544_hci_i2c_fw_write_chunk(phy);
exit_state_wait_write_answer:
if (r < 0)
pn544_hci_i2c_fw_work_complete(phy, r);
break;
case FW_WORK_STATE_WAIT_CHECK_ANSWER:
r = phy->fw_cmd_result;
if (r < 0)
goto exit_state_wait_check_answer;
blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
phy->fw_blob_size);
phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
if (phy->fw_blob_size != 0) {
phy->fw_blob_dest_addr =
get_unaligned_be32(&blob->be_destaddr);
phy->fw_blob_data = blob->data;
phy->fw_written = 0;
r = pn544_hci_i2c_fw_write_chunk(phy);
}
exit_state_wait_check_answer:
if (r < 0 || phy->fw_blob_size == 0)
pn544_hci_i2c_fw_work_complete(phy, r);
break;
case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER:
r = phy->fw_cmd_result;
if (r < 0)
goto exit_state_wait_secure_write_answer;
if (r == PN544_FW_CMD_RESULT_CHUNK_OK) {
r = pn544_hci_i2c_fw_secure_write_frame(phy);
goto exit_state_wait_secure_write_answer;
}
if (phy->fw_written == phy->fw_blob_size) {
secure_blob = (struct pn544_i2c_fw_secure_blob *)
(phy->fw_blob_data + phy->fw_blob_size);
phy->fw_size -= phy->fw_blob_size +
PN544_FW_SECURE_BLOB_HEADER_LEN;
if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN
+ PN544_FW_SECURE_FRAME_HEADER_LEN) {
phy->fw_blob_data = secure_blob->data;
phy->fw_written = 0;
r = pn544_hci_i2c_fw_secure_write_frame(phy);
}
}
exit_state_wait_secure_write_answer:
if (r < 0 || phy->fw_size == 0)
pn544_hci_i2c_fw_work_complete(phy, r);
break;
default:
break;
}
}
static int pn544_hci_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct pn544_i2c_phy *phy;
struct pn544_nfc_platform_data *pdata;
int r = 0;
dev_dbg(&client->dev, "%s\n", __func__);
dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
return -ENODEV;
}
phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy),
GFP_KERNEL);
if (!phy) {
nfc_err(&client->dev,
"Cannot allocate memory for pn544 i2c phy.\n");
return -ENOMEM;
}
INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
phy->fw_work_state = FW_WORK_STATE_IDLE;
phy->i2c_dev = client;
i2c_set_clientdata(client, phy);
pdata = client->dev.platform_data;
if (pdata == NULL) {
nfc_err(&client->dev, "No platform data\n");
return -EINVAL;
}
if (pdata->request_resources == NULL) {
nfc_err(&client->dev, "request_resources() missing\n");
return -EINVAL;
}
r = pdata->request_resources(client);
if (r) {
nfc_err(&client->dev, "Cannot get platform resources\n");
return r;
}
phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
pn544_hci_i2c_platform_init(phy);
r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
PN544_HCI_I2C_DRIVER_NAME, phy);
if (r < 0) {
nfc_err(&client->dev, "Unable to register IRQ handler\n");
goto err_rti;
}
r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
PN544_HCI_I2C_LLC_MAX_PAYLOAD,
pn544_hci_i2c_fw_download, &phy->hdev);
if (r < 0)
goto err_hci;
return 0;
err_hci:
free_irq(client->irq, phy);
err_rti:
if (pdata->free_resources != NULL)
pdata->free_resources();
return r;
}
static int pn544_hci_i2c_remove(struct i2c_client *client)
{
struct pn544_i2c_phy *phy = i2c_get_clientdata(client);
struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
dev_dbg(&client->dev, "%s\n", __func__);
cancel_work_sync(&phy->fw_work);
if (phy->fw_work_state != FW_WORK_STATE_IDLE)
pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
pn544_hci_remove(phy->hdev);
if (phy->powered)
pn544_hci_i2c_disable(phy);
free_irq(client->irq, phy);
if (pdata->free_resources)
pdata->free_resources();
return 0;
}
static struct i2c_driver pn544_hci_i2c_driver = {
.driver = {
.name = PN544_HCI_I2C_DRIVER_NAME,
},
.probe = pn544_hci_i2c_probe,
.id_table = pn544_hci_i2c_id_table,
.remove = pn544_hci_i2c_remove,
};
module_i2c_driver(pn544_hci_i2c_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION(DRIVER_DESC);

111
drivers/nfc/pn544/mei.c Normal file
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@@ -0,0 +1,111 @@
/*
* HCI based Driver for NXP pn544 NFC Chip
*
* Copyright (C) 2013 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/nfc.h>
#include <net/nfc/hci.h>
#include <net/nfc/llc.h>
#include "../mei_phy.h"
#include "pn544.h"
#define PN544_DRIVER_NAME "pn544"
static int pn544_mei_probe(struct mei_cl_device *device,
const struct mei_cl_device_id *id)
{
struct nfc_mei_phy *phy;
int r;
pr_info("Probing NFC pn544\n");
phy = nfc_mei_phy_alloc(device);
if (!phy) {
pr_err("Cannot allocate memory for pn544 mei phy.\n");
return -ENOMEM;
}
r = pn544_hci_probe(phy, &mei_phy_ops, LLC_NOP_NAME,
MEI_NFC_HEADER_SIZE, 0, MEI_NFC_MAX_HCI_PAYLOAD,
NULL, &phy->hdev);
if (r < 0) {
nfc_mei_phy_free(phy);
return r;
}
return 0;
}
static int pn544_mei_remove(struct mei_cl_device *device)
{
struct nfc_mei_phy *phy = mei_cl_get_drvdata(device);
pr_info("Removing pn544\n");
pn544_hci_remove(phy->hdev);
nfc_mei_phy_free(phy);
return 0;
}
static struct mei_cl_device_id pn544_mei_tbl[] = {
{ PN544_DRIVER_NAME },
/* required last entry */
{ }
};
MODULE_DEVICE_TABLE(mei, pn544_mei_tbl);
static struct mei_cl_driver pn544_driver = {
.id_table = pn544_mei_tbl,
.name = PN544_DRIVER_NAME,
.probe = pn544_mei_probe,
.remove = pn544_mei_remove,
};
static int pn544_mei_init(void)
{
int r;
pr_debug(DRIVER_DESC ": %s\n", __func__);
r = mei_cl_driver_register(&pn544_driver);
if (r) {
pr_err(PN544_DRIVER_NAME ": driver registration failed\n");
return r;
}
return 0;
}
static void pn544_mei_exit(void)
{
mei_cl_driver_unregister(&pn544_driver);
}
module_init(pn544_mei_init);
module_exit(pn544_mei_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION(DRIVER_DESC);

996
drivers/nfc/pn544/pn544.c Normal file
View File

@@ -0,0 +1,996 @@
/*
* HCI based Driver for NXP PN544 NFC Chip
*
* Copyright (C) 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/nfc.h>
#include <net/nfc/hci.h>
#include <net/nfc/llc.h>
#include "pn544.h"
/* Timing restrictions (ms) */
#define PN544_HCI_RESETVEN_TIME 30
enum pn544_state {
PN544_ST_COLD,
PN544_ST_FW_READY,
PN544_ST_READY,
};
#define FULL_VERSION_LEN 11
/* Proprietary commands */
#define PN544_WRITE 0x3f
#define PN544_TEST_SWP 0x21
/* Proprietary gates, events, commands and registers */
/* NFC_HCI_RF_READER_A_GATE additional registers and commands */
#define PN544_RF_READER_A_AUTO_ACTIVATION 0x10
#define PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION 0x12
#define PN544_MIFARE_CMD 0x21
/* Commands that apply to all RF readers */
#define PN544_RF_READER_CMD_PRESENCE_CHECK 0x30
#define PN544_RF_READER_CMD_ACTIVATE_NEXT 0x32
/* NFC_HCI_ID_MGMT_GATE additional registers */
#define PN544_ID_MGMT_FULL_VERSION_SW 0x10
#define PN544_RF_READER_ISO15693_GATE 0x12
#define PN544_RF_READER_F_GATE 0x14
#define PN544_FELICA_ID 0x04
#define PN544_FELICA_RAW 0x20
#define PN544_RF_READER_JEWEL_GATE 0x15
#define PN544_JEWEL_RAW_CMD 0x23
#define PN544_RF_READER_NFCIP1_INITIATOR_GATE 0x30
#define PN544_RF_READER_NFCIP1_TARGET_GATE 0x31
#define PN544_SYS_MGMT_GATE 0x90
#define PN544_SYS_MGMT_INFO_NOTIFICATION 0x02
#define PN544_POLLING_LOOP_MGMT_GATE 0x94
#define PN544_DEP_MODE 0x01
#define PN544_DEP_ATR_REQ 0x02
#define PN544_DEP_ATR_RES 0x03
#define PN544_DEP_MERGE 0x0D
#define PN544_PL_RDPHASES 0x06
#define PN544_PL_EMULATION 0x07
#define PN544_PL_NFCT_DEACTIVATED 0x09
#define PN544_SWP_MGMT_GATE 0xA0
#define PN544_SWP_DEFAULT_MODE 0x01
#define PN544_NFC_WI_MGMT_GATE 0xA1
#define PN544_NFC_ESE_DEFAULT_MODE 0x01
#define PN544_HCI_EVT_SND_DATA 0x01
#define PN544_HCI_EVT_ACTIVATED 0x02
#define PN544_HCI_EVT_DEACTIVATED 0x03
#define PN544_HCI_EVT_RCV_DATA 0x04
#define PN544_HCI_EVT_CONTINUE_MI 0x05
#define PN544_HCI_EVT_SWITCH_MODE 0x03
#define PN544_HCI_CMD_ATTREQUEST 0x12
#define PN544_HCI_CMD_CONTINUE_ACTIVATION 0x13
static struct nfc_hci_gate pn544_gates[] = {
{NFC_HCI_ADMIN_GATE, NFC_HCI_INVALID_PIPE},
{NFC_HCI_LOOPBACK_GATE, NFC_HCI_INVALID_PIPE},
{NFC_HCI_ID_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{NFC_HCI_LINK_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{NFC_HCI_RF_READER_B_GATE, NFC_HCI_INVALID_PIPE},
{NFC_HCI_RF_READER_A_GATE, NFC_HCI_INVALID_PIPE},
{PN544_SYS_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{PN544_SWP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{PN544_POLLING_LOOP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{PN544_NFC_WI_MGMT_GATE, NFC_HCI_INVALID_PIPE},
{PN544_RF_READER_F_GATE, NFC_HCI_INVALID_PIPE},
{PN544_RF_READER_JEWEL_GATE, NFC_HCI_INVALID_PIPE},
{PN544_RF_READER_ISO15693_GATE, NFC_HCI_INVALID_PIPE},
{PN544_RF_READER_NFCIP1_INITIATOR_GATE, NFC_HCI_INVALID_PIPE},
{PN544_RF_READER_NFCIP1_TARGET_GATE, NFC_HCI_INVALID_PIPE}
};
/* Largest headroom needed for outgoing custom commands */
#define PN544_CMDS_HEADROOM 2
struct pn544_hci_info {
struct nfc_phy_ops *phy_ops;
void *phy_id;
struct nfc_hci_dev *hdev;
enum pn544_state state;
struct mutex info_lock;
int async_cb_type;
data_exchange_cb_t async_cb;
void *async_cb_context;
fw_download_t fw_download;
};
static int pn544_hci_open(struct nfc_hci_dev *hdev)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
int r = 0;
mutex_lock(&info->info_lock);
if (info->state != PN544_ST_COLD) {
r = -EBUSY;
goto out;
}
r = info->phy_ops->enable(info->phy_id);
if (r == 0)
info->state = PN544_ST_READY;
out:
mutex_unlock(&info->info_lock);
return r;
}
static void pn544_hci_close(struct nfc_hci_dev *hdev)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
mutex_lock(&info->info_lock);
if (info->state == PN544_ST_COLD)
goto out;
info->phy_ops->disable(info->phy_id);
info->state = PN544_ST_COLD;
out:
mutex_unlock(&info->info_lock);
}
static int pn544_hci_ready(struct nfc_hci_dev *hdev)
{
struct sk_buff *skb;
static struct hw_config {
u8 adr[2];
u8 value;
} hw_config[] = {
{{0x9f, 0x9a}, 0x00},
{{0x98, 0x10}, 0xbc},
{{0x9e, 0x71}, 0x00},
{{0x98, 0x09}, 0x00},
{{0x9e, 0xb4}, 0x00},
{{0x9c, 0x01}, 0x08},
{{0x9e, 0xaa}, 0x01},
{{0x9b, 0xd1}, 0x17},
{{0x9b, 0xd2}, 0x58},
{{0x9b, 0xd3}, 0x10},
{{0x9b, 0xd4}, 0x47},
{{0x9b, 0xd5}, 0x0c},
{{0x9b, 0xd6}, 0x37},
{{0x9b, 0xdd}, 0x33},
{{0x9b, 0x84}, 0x00},
{{0x99, 0x81}, 0x79},
{{0x99, 0x31}, 0x79},
{{0x98, 0x00}, 0x3f},
{{0x9f, 0x09}, 0x02},
{{0x9f, 0x0a}, 0x05},
{{0x9e, 0xd1}, 0xa1},
{{0x99, 0x23}, 0x01},
{{0x9e, 0x74}, 0x00},
{{0x9e, 0x90}, 0x00},
{{0x9f, 0x28}, 0x10},
{{0x9f, 0x35}, 0x04},
{{0x9f, 0x36}, 0x11},
{{0x9c, 0x31}, 0x00},
{{0x9c, 0x32}, 0x00},
{{0x9c, 0x19}, 0x0a},
{{0x9c, 0x1a}, 0x0a},
{{0x9c, 0x0c}, 0x00},
{{0x9c, 0x0d}, 0x00},
{{0x9c, 0x12}, 0x00},
{{0x9c, 0x13}, 0x00},
{{0x98, 0xa2}, 0x09},
{{0x98, 0x93}, 0x00},
{{0x98, 0x7d}, 0x08},
{{0x98, 0x7e}, 0x00},
{{0x9f, 0xc8}, 0x00},
};
struct hw_config *p = hw_config;
int count = ARRAY_SIZE(hw_config);
struct sk_buff *res_skb;
u8 param[4];
int r;
param[0] = 0;
while (count--) {
param[1] = p->adr[0];
param[2] = p->adr[1];
param[3] = p->value;
r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_WRITE,
param, 4, &res_skb);
if (r < 0)
return r;
if (res_skb->len != 1) {
kfree_skb(res_skb);
return -EPROTO;
}
if (res_skb->data[0] != p->value) {
kfree_skb(res_skb);
return -EIO;
}
kfree_skb(res_skb);
p++;
}
param[0] = NFC_HCI_UICC_HOST_ID;
r = nfc_hci_set_param(hdev, NFC_HCI_ADMIN_GATE,
NFC_HCI_ADMIN_WHITELIST, param, 1);
if (r < 0)
return r;
param[0] = 0x3d;
r = nfc_hci_set_param(hdev, PN544_SYS_MGMT_GATE,
PN544_SYS_MGMT_INFO_NOTIFICATION, param, 1);
if (r < 0)
return r;
param[0] = 0x0;
r = nfc_hci_set_param(hdev, NFC_HCI_RF_READER_A_GATE,
PN544_RF_READER_A_AUTO_ACTIVATION, param, 1);
if (r < 0)
return r;
r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
if (r < 0)
return r;
param[0] = 0x1;
r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
PN544_PL_NFCT_DEACTIVATED, param, 1);
if (r < 0)
return r;
param[0] = 0x0;
r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
PN544_PL_RDPHASES, param, 1);
if (r < 0)
return r;
r = nfc_hci_get_param(hdev, NFC_HCI_ID_MGMT_GATE,
PN544_ID_MGMT_FULL_VERSION_SW, &skb);
if (r < 0)
return r;
if (skb->len != FULL_VERSION_LEN) {
kfree_skb(skb);
return -EINVAL;
}
print_hex_dump(KERN_DEBUG, "FULL VERSION SOFTWARE INFO: ",
DUMP_PREFIX_NONE, 16, 1,
skb->data, FULL_VERSION_LEN, false);
kfree_skb(skb);
return 0;
}
static int pn544_hci_xmit(struct nfc_hci_dev *hdev, struct sk_buff *skb)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
return info->phy_ops->write(info->phy_id, skb);
}
static int pn544_hci_start_poll(struct nfc_hci_dev *hdev,
u32 im_protocols, u32 tm_protocols)
{
u8 phases = 0;
int r;
u8 duration[2];
u8 activated;
u8 i_mode = 0x3f; /* Enable all supported modes */
u8 t_mode = 0x0f;
u8 t_merge = 0x01; /* Enable merge by default */
pr_info(DRIVER_DESC ": %s protocols 0x%x 0x%x\n",
__func__, im_protocols, tm_protocols);
r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
if (r < 0)
return r;
duration[0] = 0x18;
duration[1] = 0x6a;
r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
PN544_PL_EMULATION, duration, 2);
if (r < 0)
return r;
activated = 0;
r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
PN544_PL_NFCT_DEACTIVATED, &activated, 1);
if (r < 0)
return r;
if (im_protocols & (NFC_PROTO_ISO14443_MASK | NFC_PROTO_MIFARE_MASK |
NFC_PROTO_JEWEL_MASK))
phases |= 1; /* Type A */
if (im_protocols & NFC_PROTO_FELICA_MASK) {
phases |= (1 << 2); /* Type F 212 */
phases |= (1 << 3); /* Type F 424 */
}
phases |= (1 << 5); /* NFC active */
r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
PN544_PL_RDPHASES, &phases, 1);
if (r < 0)
return r;
if ((im_protocols | tm_protocols) & NFC_PROTO_NFC_DEP_MASK) {
hdev->gb = nfc_get_local_general_bytes(hdev->ndev,
&hdev->gb_len);
pr_debug("generate local bytes %p\n", hdev->gb);
if (hdev->gb == NULL || hdev->gb_len == 0) {
im_protocols &= ~NFC_PROTO_NFC_DEP_MASK;
tm_protocols &= ~NFC_PROTO_NFC_DEP_MASK;
}
}
if (im_protocols & NFC_PROTO_NFC_DEP_MASK) {
r = nfc_hci_send_event(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
if (r < 0)
return r;
r = nfc_hci_set_param(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
PN544_DEP_MODE, &i_mode, 1);
if (r < 0)
return r;
r = nfc_hci_set_param(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
PN544_DEP_ATR_REQ, hdev->gb, hdev->gb_len);
if (r < 0)
return r;
r = nfc_hci_send_event(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
if (r < 0)
nfc_hci_send_event(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
}
if (tm_protocols & NFC_PROTO_NFC_DEP_MASK) {
r = nfc_hci_set_param(hdev, PN544_RF_READER_NFCIP1_TARGET_GATE,
PN544_DEP_MODE, &t_mode, 1);
if (r < 0)
return r;
r = nfc_hci_set_param(hdev, PN544_RF_READER_NFCIP1_TARGET_GATE,
PN544_DEP_ATR_RES, hdev->gb, hdev->gb_len);
if (r < 0)
return r;
r = nfc_hci_set_param(hdev, PN544_RF_READER_NFCIP1_TARGET_GATE,
PN544_DEP_MERGE, &t_merge, 1);
if (r < 0)
return r;
}
r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
if (r < 0)
nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
return r;
}
static int pn544_hci_dep_link_up(struct nfc_hci_dev *hdev,
struct nfc_target *target, u8 comm_mode,
u8 *gb, size_t gb_len)
{
struct sk_buff *rgb_skb = NULL;
int r;
r = nfc_hci_get_param(hdev, target->hci_reader_gate,
PN544_DEP_ATR_RES, &rgb_skb);
if (r < 0)
return r;
if (rgb_skb->len == 0 || rgb_skb->len > NFC_GB_MAXSIZE) {
r = -EPROTO;
goto exit;
}
print_hex_dump(KERN_DEBUG, "remote gb: ", DUMP_PREFIX_OFFSET,
16, 1, rgb_skb->data, rgb_skb->len, true);
r = nfc_set_remote_general_bytes(hdev->ndev, rgb_skb->data,
rgb_skb->len);
if (r == 0)
r = nfc_dep_link_is_up(hdev->ndev, target->idx, comm_mode,
NFC_RF_INITIATOR);
exit:
kfree_skb(rgb_skb);
return r;
}
static int pn544_hci_dep_link_down(struct nfc_hci_dev *hdev)
{
return nfc_hci_send_event(hdev, PN544_RF_READER_NFCIP1_INITIATOR_GATE,
NFC_HCI_EVT_END_OPERATION, NULL, 0);
}
static int pn544_hci_target_from_gate(struct nfc_hci_dev *hdev, u8 gate,
struct nfc_target *target)
{
switch (gate) {
case PN544_RF_READER_F_GATE:
target->supported_protocols = NFC_PROTO_FELICA_MASK;
break;
case PN544_RF_READER_JEWEL_GATE:
target->supported_protocols = NFC_PROTO_JEWEL_MASK;
target->sens_res = 0x0c00;
break;
case PN544_RF_READER_NFCIP1_INITIATOR_GATE:
target->supported_protocols = NFC_PROTO_NFC_DEP_MASK;
break;
default:
return -EPROTO;
}
return 0;
}
static int pn544_hci_complete_target_discovered(struct nfc_hci_dev *hdev,
u8 gate,
struct nfc_target *target)
{
struct sk_buff *uid_skb;
int r = 0;
if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE)
return r;
if (target->supported_protocols & NFC_PROTO_NFC_DEP_MASK) {
r = nfc_hci_send_cmd(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
PN544_HCI_CMD_CONTINUE_ACTIVATION, NULL, 0, NULL);
if (r < 0)
return r;
target->hci_reader_gate = PN544_RF_READER_NFCIP1_INITIATOR_GATE;
} else if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
target->nfcid1_len != 10)
return -EPROTO;
r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
PN544_RF_READER_CMD_ACTIVATE_NEXT,
target->nfcid1, target->nfcid1_len, NULL);
} else if (target->supported_protocols & NFC_PROTO_FELICA_MASK) {
r = nfc_hci_get_param(hdev, PN544_RF_READER_F_GATE,
PN544_FELICA_ID, &uid_skb);
if (r < 0)
return r;
if (uid_skb->len != 8) {
kfree_skb(uid_skb);
return -EPROTO;
}
/* Type F NFC-DEP IDm has prefix 0x01FE */
if ((uid_skb->data[0] == 0x01) && (uid_skb->data[1] == 0xfe)) {
kfree_skb(uid_skb);
r = nfc_hci_send_cmd(hdev,
PN544_RF_READER_NFCIP1_INITIATOR_GATE,
PN544_HCI_CMD_CONTINUE_ACTIVATION,
NULL, 0, NULL);
if (r < 0)
return r;
target->supported_protocols = NFC_PROTO_NFC_DEP_MASK;
target->hci_reader_gate =
PN544_RF_READER_NFCIP1_INITIATOR_GATE;
} else {
r = nfc_hci_send_cmd(hdev, PN544_RF_READER_F_GATE,
PN544_RF_READER_CMD_ACTIVATE_NEXT,
uid_skb->data, uid_skb->len, NULL);
kfree_skb(uid_skb);
}
} else if (target->supported_protocols & NFC_PROTO_ISO14443_MASK) {
/*
* TODO: maybe other ISO 14443 require some kind of continue
* activation, but for now we've seen only this one below.
*/
if (target->sens_res == 0x4403) /* Type 4 Mifare DESFire */
r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION,
NULL, 0, NULL);
}
return r;
}
#define PN544_CB_TYPE_READER_F 1
static void pn544_hci_data_exchange_cb(void *context, struct sk_buff *skb,
int err)
{
struct pn544_hci_info *info = context;
switch (info->async_cb_type) {
case PN544_CB_TYPE_READER_F:
if (err == 0)
skb_pull(skb, 1);
info->async_cb(info->async_cb_context, skb, err);
break;
default:
if (err == 0)
kfree_skb(skb);
break;
}
}
#define MIFARE_CMD_AUTH_KEY_A 0x60
#define MIFARE_CMD_AUTH_KEY_B 0x61
#define MIFARE_CMD_HEADER 2
#define MIFARE_UID_LEN 4
#define MIFARE_KEY_LEN 6
#define MIFARE_CMD_LEN 12
/*
* Returns:
* <= 0: driver handled the data exchange
* 1: driver doesn't especially handle, please do standard processing
*/
static int pn544_hci_im_transceive(struct nfc_hci_dev *hdev,
struct nfc_target *target,
struct sk_buff *skb, data_exchange_cb_t cb,
void *cb_context)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__,
target->hci_reader_gate);
switch (target->hci_reader_gate) {
case NFC_HCI_RF_READER_A_GATE:
if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
/*
* It seems that pn544 is inverting key and UID for
* MIFARE authentication commands.
*/
if (skb->len == MIFARE_CMD_LEN &&
(skb->data[0] == MIFARE_CMD_AUTH_KEY_A ||
skb->data[0] == MIFARE_CMD_AUTH_KEY_B)) {
u8 uid[MIFARE_UID_LEN];
u8 *data = skb->data + MIFARE_CMD_HEADER;
memcpy(uid, data + MIFARE_KEY_LEN,
MIFARE_UID_LEN);
memmove(data + MIFARE_UID_LEN, data,
MIFARE_KEY_LEN);
memcpy(data, uid, MIFARE_UID_LEN);
}
return nfc_hci_send_cmd_async(hdev,
target->hci_reader_gate,
PN544_MIFARE_CMD,
skb->data, skb->len,
cb, cb_context);
} else
return 1;
case PN544_RF_READER_F_GATE:
*skb_push(skb, 1) = 0;
*skb_push(skb, 1) = 0;
info->async_cb_type = PN544_CB_TYPE_READER_F;
info->async_cb = cb;
info->async_cb_context = cb_context;
return nfc_hci_send_cmd_async(hdev, target->hci_reader_gate,
PN544_FELICA_RAW, skb->data,
skb->len,
pn544_hci_data_exchange_cb, info);
case PN544_RF_READER_JEWEL_GATE:
return nfc_hci_send_cmd_async(hdev, target->hci_reader_gate,
PN544_JEWEL_RAW_CMD, skb->data,
skb->len, cb, cb_context);
case PN544_RF_READER_NFCIP1_INITIATOR_GATE:
*skb_push(skb, 1) = 0;
return nfc_hci_send_event(hdev, target->hci_reader_gate,
PN544_HCI_EVT_SND_DATA, skb->data,
skb->len);
default:
return 1;
}
}
static int pn544_hci_tm_send(struct nfc_hci_dev *hdev, struct sk_buff *skb)
{
int r;
/* Set default false for multiple information chaining */
*skb_push(skb, 1) = 0;
r = nfc_hci_send_event(hdev, PN544_RF_READER_NFCIP1_TARGET_GATE,
PN544_HCI_EVT_SND_DATA, skb->data, skb->len);
kfree_skb(skb);
return r;
}
static int pn544_hci_check_presence(struct nfc_hci_dev *hdev,
struct nfc_target *target)
{
pr_debug("supported protocol %d\b", target->supported_protocols);
if (target->supported_protocols & (NFC_PROTO_ISO14443_MASK |
NFC_PROTO_ISO14443_B_MASK)) {
return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
PN544_RF_READER_CMD_PRESENCE_CHECK,
NULL, 0, NULL);
} else if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
target->nfcid1_len != 10)
return -EOPNOTSUPP;
return nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
PN544_RF_READER_CMD_ACTIVATE_NEXT,
target->nfcid1, target->nfcid1_len, NULL);
} else if (target->supported_protocols & (NFC_PROTO_JEWEL_MASK |
NFC_PROTO_FELICA_MASK)) {
return -EOPNOTSUPP;
} else if (target->supported_protocols & NFC_PROTO_NFC_DEP_MASK) {
return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
PN544_HCI_CMD_ATTREQUEST,
NULL, 0, NULL);
}
return 0;
}
/*
* Returns:
* <= 0: driver handled the event, skb consumed
* 1: driver does not handle the event, please do standard processing
*/
static int pn544_hci_event_received(struct nfc_hci_dev *hdev, u8 gate, u8 event,
struct sk_buff *skb)
{
struct sk_buff *rgb_skb = NULL;
int r;
pr_debug("hci event %d\n", event);
switch (event) {
case PN544_HCI_EVT_ACTIVATED:
if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE) {
r = nfc_hci_target_discovered(hdev, gate);
} else if (gate == PN544_RF_READER_NFCIP1_TARGET_GATE) {
r = nfc_hci_get_param(hdev, gate, PN544_DEP_ATR_REQ,
&rgb_skb);
if (r < 0)
goto exit;
r = nfc_tm_activated(hdev->ndev, NFC_PROTO_NFC_DEP_MASK,
NFC_COMM_PASSIVE, rgb_skb->data,
rgb_skb->len);
kfree_skb(rgb_skb);
} else {
r = -EINVAL;
}
break;
case PN544_HCI_EVT_DEACTIVATED:
r = nfc_hci_send_event(hdev, gate, NFC_HCI_EVT_END_OPERATION,
NULL, 0);
break;
case PN544_HCI_EVT_RCV_DATA:
if (skb->len < 2) {
r = -EPROTO;
goto exit;
}
if (skb->data[0] != 0) {
pr_debug("data0 %d\n", skb->data[0]);
r = -EPROTO;
goto exit;
}
skb_pull(skb, 2);
return nfc_tm_data_received(hdev->ndev, skb);
default:
return 1;
}
exit:
kfree_skb(skb);
return r;
}
static int pn544_hci_fw_download(struct nfc_hci_dev *hdev,
const char *firmware_name)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
if (info->fw_download == NULL)
return -ENOTSUPP;
return info->fw_download(info->phy_id, firmware_name, hdev->sw_romlib);
}
static int pn544_hci_discover_se(struct nfc_hci_dev *hdev)
{
u32 se_idx = 0;
u8 ese_mode = 0x01; /* Default mode */
struct sk_buff *res_skb;
int r;
r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_TEST_SWP,
NULL, 0, &res_skb);
if (r == 0) {
if (res_skb->len == 2 && res_skb->data[0] == 0x00)
nfc_add_se(hdev->ndev, se_idx++, NFC_SE_UICC);
kfree_skb(res_skb);
}
r = nfc_hci_send_event(hdev, PN544_NFC_WI_MGMT_GATE,
PN544_HCI_EVT_SWITCH_MODE,
&ese_mode, 1);
if (r == 0)
nfc_add_se(hdev->ndev, se_idx++, NFC_SE_EMBEDDED);
return !se_idx;
}
#define PN544_SE_MODE_OFF 0x00
#define PN544_SE_MODE_ON 0x01
static int pn544_hci_enable_se(struct nfc_hci_dev *hdev, u32 se_idx)
{
struct nfc_se *se;
u8 enable = PN544_SE_MODE_ON;
static struct uicc_gatelist {
u8 head;
u8 adr[2];
u8 value;
} uicc_gatelist[] = {
{0x00, {0x9e, 0xd9}, 0x23},
{0x00, {0x9e, 0xda}, 0x21},
{0x00, {0x9e, 0xdb}, 0x22},
{0x00, {0x9e, 0xdc}, 0x24},
};
struct uicc_gatelist *p = uicc_gatelist;
int count = ARRAY_SIZE(uicc_gatelist);
struct sk_buff *res_skb;
int r;
se = nfc_find_se(hdev->ndev, se_idx);
switch (se->type) {
case NFC_SE_UICC:
while (count--) {
r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE,
PN544_WRITE, (u8 *)p, 4, &res_skb);
if (r < 0)
return r;
if (res_skb->len != 1) {
kfree_skb(res_skb);
return -EPROTO;
}
if (res_skb->data[0] != p->value) {
kfree_skb(res_skb);
return -EIO;
}
kfree_skb(res_skb);
p++;
}
return nfc_hci_set_param(hdev, PN544_SWP_MGMT_GATE,
PN544_SWP_DEFAULT_MODE, &enable, 1);
case NFC_SE_EMBEDDED:
return nfc_hci_set_param(hdev, PN544_NFC_WI_MGMT_GATE,
PN544_NFC_ESE_DEFAULT_MODE, &enable, 1);
default:
return -EINVAL;
}
}
static int pn544_hci_disable_se(struct nfc_hci_dev *hdev, u32 se_idx)
{
struct nfc_se *se;
u8 disable = PN544_SE_MODE_OFF;
se = nfc_find_se(hdev->ndev, se_idx);
switch (se->type) {
case NFC_SE_UICC:
return nfc_hci_set_param(hdev, PN544_SWP_MGMT_GATE,
PN544_SWP_DEFAULT_MODE, &disable, 1);
case NFC_SE_EMBEDDED:
return nfc_hci_set_param(hdev, PN544_NFC_WI_MGMT_GATE,
PN544_NFC_ESE_DEFAULT_MODE, &disable, 1);
default:
return -EINVAL;
}
}
static struct nfc_hci_ops pn544_hci_ops = {
.open = pn544_hci_open,
.close = pn544_hci_close,
.hci_ready = pn544_hci_ready,
.xmit = pn544_hci_xmit,
.start_poll = pn544_hci_start_poll,
.dep_link_up = pn544_hci_dep_link_up,
.dep_link_down = pn544_hci_dep_link_down,
.target_from_gate = pn544_hci_target_from_gate,
.complete_target_discovered = pn544_hci_complete_target_discovered,
.im_transceive = pn544_hci_im_transceive,
.tm_send = pn544_hci_tm_send,
.check_presence = pn544_hci_check_presence,
.event_received = pn544_hci_event_received,
.fw_download = pn544_hci_fw_download,
.discover_se = pn544_hci_discover_se,
.enable_se = pn544_hci_enable_se,
.disable_se = pn544_hci_disable_se,
};
int pn544_hci_probe(void *phy_id, struct nfc_phy_ops *phy_ops, char *llc_name,
int phy_headroom, int phy_tailroom, int phy_payload,
fw_download_t fw_download, struct nfc_hci_dev **hdev)
{
struct pn544_hci_info *info;
u32 protocols;
struct nfc_hci_init_data init_data;
int r;
info = kzalloc(sizeof(struct pn544_hci_info), GFP_KERNEL);
if (!info) {
r = -ENOMEM;
goto err_info_alloc;
}
info->phy_ops = phy_ops;
info->phy_id = phy_id;
info->fw_download = fw_download;
info->state = PN544_ST_COLD;
mutex_init(&info->info_lock);
init_data.gate_count = ARRAY_SIZE(pn544_gates);
memcpy(init_data.gates, pn544_gates, sizeof(pn544_gates));
/*
* TODO: Session id must include the driver name + some bus addr
* persistent info to discriminate 2 identical chips
*/
strcpy(init_data.session_id, "ID544HCI");
protocols = NFC_PROTO_JEWEL_MASK |
NFC_PROTO_MIFARE_MASK |
NFC_PROTO_FELICA_MASK |
NFC_PROTO_ISO14443_MASK |
NFC_PROTO_ISO14443_B_MASK |
NFC_PROTO_NFC_DEP_MASK;
info->hdev = nfc_hci_allocate_device(&pn544_hci_ops, &init_data, 0,
protocols, llc_name,
phy_headroom + PN544_CMDS_HEADROOM,
phy_tailroom, phy_payload);
if (!info->hdev) {
pr_err("Cannot allocate nfc hdev\n");
r = -ENOMEM;
goto err_alloc_hdev;
}
nfc_hci_set_clientdata(info->hdev, info);
r = nfc_hci_register_device(info->hdev);
if (r)
goto err_regdev;
*hdev = info->hdev;
return 0;
err_regdev:
nfc_hci_free_device(info->hdev);
err_alloc_hdev:
kfree(info);
err_info_alloc:
return r;
}
EXPORT_SYMBOL(pn544_hci_probe);
void pn544_hci_remove(struct nfc_hci_dev *hdev)
{
struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
nfc_hci_unregister_device(hdev);
nfc_hci_free_device(hdev);
kfree(info);
}
EXPORT_SYMBOL(pn544_hci_remove);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION(DRIVER_DESC);

38
drivers/nfc/pn544/pn544.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* Copyright (C) 2011 - 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __LOCAL_PN544_H_
#define __LOCAL_PN544_H_
#include <net/nfc/hci.h>
#define DRIVER_DESC "HCI NFC driver for PN544"
#define PN544_HCI_MODE 0
#define PN544_FW_MODE 1
typedef int (*fw_download_t)(void *context, const char *firmware_name,
u8 hw_variant);
int pn544_hci_probe(void *phy_id, struct nfc_phy_ops *phy_ops, char *llc_name,
int phy_headroom, int phy_tailroom, int phy_payload,
fw_download_t fw_download, struct nfc_hci_dev **hdev);
void pn544_hci_remove(struct nfc_hci_dev *hdev);
#endif /* __LOCAL_PN544_H_ */