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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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65
drivers/net/ethernet/cirrus/Kconfig Normal file
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#
# Cirrus network device configuration
#
config NET_VENDOR_CIRRUS
bool "Cirrus devices"
default y
depends on ISA || EISA || ARM || MAC
---help---
If you have a network (Ethernet) card belonging to this class, say Y
and read the Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto>.
Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all
the questions about Cirrus cards. If you say Y, you will be asked
for your specific card in the following questions.
if NET_VENDOR_CIRRUS
config CS89x0
tristate "CS89x0 support"
depends on ISA || EISA || ARM
---help---
Support for CS89x0 chipset based Ethernet cards. If you have a
network (Ethernet) card of this type, say Y and read the
Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto> as well as
<file:Documentation/networking/cs89x0.txt>.
To compile this driver as a module, choose M here. The module
will be called cs89x0.
config CS89x0_PLATFORM
bool "CS89x0 platform driver support"
depends on CS89x0
help
Say Y to compile the cs89x0 driver as a platform driver. This
makes this driver suitable for use on certain evaluation boards
such as the iMX21ADS.
If you are unsure, say N.
config EP93XX_ETH
tristate "EP93xx Ethernet support"
depends on ARM && ARCH_EP93XX
select NET_CORE
select MII
help
This is a driver for the ethernet hardware included in EP93xx CPUs.
Say Y if you are building a kernel for EP93xx based devices.
config MAC89x0
tristate "Macintosh CS89x0 based ethernet cards"
depends on MAC
---help---
Support for CS89x0 chipset based Ethernet cards. If you have a
Nubus or LC-PDS network (Ethernet) card of this type, say Y and
read the Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto>.
To compile this driver as a module, choose M here. This module will
be called mac89x0.
endif # NET_VENDOR_CIRRUS

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drivers/net/ethernet/cirrus/Makefile Normal file
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#
# Makefile for the Cirrus network device drivers.
#
obj-$(CONFIG_CS89x0) += cs89x0.o
obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
obj-$(CONFIG_MAC89x0) += mac89x0.o

1925
drivers/net/ethernet/cirrus/cs89x0.c Normal file
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465
drivers/net/ethernet/cirrus/cs89x0.h Normal file
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/* Copyright, 1988-1992, Russell Nelson, Crynwr Software
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, version 1.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
/* offset 2h -> Model/Product Number */
/* offset 3h -> Chip Revision Number */
#define PP_ISAIOB 0x0020 /* IO base address */
#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
#define PP_ISASOF 0x0026 /* ISA DMA offset */
#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
#define PP_CS8900_ISAMemB 0x002C /* Memory base */
#define PP_CS8920_ISAMemB 0x0348 /* */
#define PP_ISABootBase 0x0030 /* Boot Prom base */
#define PP_ISABootMask 0x0034 /* Boot Prom Mask */
/* EEPROM data and command registers */
#define PP_EECMD 0x0040 /* NVR Interface Command register */
#define PP_EEData 0x0042 /* NVR Interface Data Register */
#define PP_DebugReg 0x0044 /* Debug Register */
#define PP_RxCFG 0x0102 /* Rx Bus config */
#define PP_RxCTL 0x0104 /* Receive Control Register */
#define PP_TxCFG 0x0106 /* Transmit Config Register */
#define PP_TxCMD 0x0108 /* Transmit Command Register */
#define PP_BufCFG 0x010A /* Bus configuration Register */
#define PP_LineCTL 0x0112 /* Line Config Register */
#define PP_SelfCTL 0x0114 /* Self Command Register */
#define PP_BusCTL 0x0116 /* ISA bus control Register */
#define PP_TestCTL 0x0118 /* Test Register */
#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
#define PP_ISQ 0x0120 /* Interrupt Status */
#define PP_RxEvent 0x0124 /* Rx Event Register */
#define PP_TxEvent 0x0128 /* Tx Event Register */
#define PP_BufEvent 0x012C /* Bus Event Register */
#define PP_RxMiss 0x0130 /* Receive Miss Count */
#define PP_TxCol 0x0132 /* Transmit Collision Count */
#define PP_LineST 0x0134 /* Line State Register */
#define PP_SelfST 0x0136 /* Self State register */
#define PP_BusST 0x0138 /* Bus Status */
#define PP_TDR 0x013C /* Time Domain Reflectometry */
#define PP_AutoNegST 0x013E /* Auto Neg Status */
#define PP_TxCommand 0x0144 /* Tx Command */
#define PP_TxLength 0x0146 /* Tx Length */
#define PP_LAF 0x0150 /* Hash Table */
#define PP_IA 0x0158 /* Physical Address Register */
#define PP_RxStatus 0x0400 /* Receive start of frame */
#define PP_RxLength 0x0402 /* Receive Length of frame */
#define PP_RxFrame 0x0404 /* Receive frame pointer */
#define PP_TxFrame 0x0A00 /* Transmit frame pointer */
/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
/* can be used as the default I/O base to access the PacketPage Area. */
#define DEFAULTIOBASE 0x0300
#define FIRST_IO 0x020C /* First I/O port to check */
#define LAST_IO 0x037C /* Last I/O port to check (+10h) */
#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
#define ADD_SIG 0x3000 /* Expected ID signature */
/* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
#ifdef CONFIG_MAC
#define LCSLOTBASE 0xfee00000
#define MMIOBASE 0x40000
#endif
#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
#define CHIP_EISA_ID_SIG_STR "0x630E"
#ifdef IBMEIPKT
#define EISA_ID_SIG 0x4D24 /* IBM */
#define PART_NO_SIG 0x1010 /* IBM */
#define MONGOOSE_BIT 0x0000 /* IBM */
#else
#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
#endif
#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
/* Mask to find out the types of registers */
#define REG_TYPE_MASK 0x001F
/* Eeprom Commands */
#define ERSE_WR_ENBL 0x00F0
#define ERSE_WR_DISABLE 0x0000
/* Defines Control/Config register quintuplet numbers */
#define RX_BUF_CFG 0x0003
#define RX_CONTROL 0x0005
#define TX_CFG 0x0007
#define TX_COMMAND 0x0009
#define BUF_CFG 0x000B
#define LINE_CONTROL 0x0013
#define SELF_CONTROL 0x0015
#define BUS_CONTROL 0x0017
#define TEST_CONTROL 0x0019
/* Defines Status/Count registers quintuplet numbers */
#define RX_EVENT 0x0004
#define TX_EVENT 0x0008
#define BUF_EVENT 0x000C
#define RX_MISS_COUNT 0x0010
#define TX_COL_COUNT 0x0012
#define LINE_STATUS 0x0014
#define SELF_STATUS 0x0016
#define BUS_STATUS 0x0018
#define TDR 0x001C
/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
#define SKIP_1 0x0040
#define RX_STREAM_ENBL 0x0080
#define RX_OK_ENBL 0x0100
#define RX_DMA_ONLY 0x0200
#define AUTO_RX_DMA 0x0400
#define BUFFER_CRC 0x0800
#define RX_CRC_ERROR_ENBL 0x1000
#define RX_RUNT_ENBL 0x2000
#define RX_EXTRA_DATA_ENBL 0x4000
/* PP_RxCTL - Receive Control bit definition - Read/write */
#define RX_IA_HASH_ACCEPT 0x0040
#define RX_PROM_ACCEPT 0x0080
#define RX_OK_ACCEPT 0x0100
#define RX_MULTCAST_ACCEPT 0x0200
#define RX_IA_ACCEPT 0x0400
#define RX_BROADCAST_ACCEPT 0x0800
#define RX_BAD_CRC_ACCEPT 0x1000
#define RX_RUNT_ACCEPT 0x2000
#define RX_EXTRA_DATA_ACCEPT 0x4000
#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
/* Default receive mode - individually addressed, broadcast, and error free */
#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
#define TX_LOST_CRS_ENBL 0x0040
#define TX_SQE_ERROR_ENBL 0x0080
#define TX_OK_ENBL 0x0100
#define TX_LATE_COL_ENBL 0x0200
#define TX_JBR_ENBL 0x0400
#define TX_ANY_COL_ENBL 0x0800
#define TX_16_COL_ENBL 0x8000
/* PP_TxCMD - Transmit Command bit definition - Read-only */
#define TX_START_4_BYTES 0x0000
#define TX_START_64_BYTES 0x0040
#define TX_START_128_BYTES 0x0080
#define TX_START_ALL_BYTES 0x00C0
#define TX_FORCE 0x0100
#define TX_ONE_COL 0x0200
#define TX_TWO_PART_DEFF_DISABLE 0x0400
#define TX_NO_CRC 0x1000
#define TX_RUNT 0x2000
/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
#define GENERATE_SW_INTERRUPT 0x0040
#define RX_DMA_ENBL 0x0080
#define READY_FOR_TX_ENBL 0x0100
#define TX_UNDERRUN_ENBL 0x0200
#define RX_MISS_ENBL 0x0400
#define RX_128_BYTE_ENBL 0x0800
#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
#define RX_DEST_MATCH_ENBL 0x8000
/* PP_LineCTL - Line Control bit definition - Read/write */
#define SERIAL_RX_ON 0x0040
#define SERIAL_TX_ON 0x0080
#define AUI_ONLY 0x0100
#define AUTO_AUI_10BASET 0x0200
#define MODIFIED_BACKOFF 0x0800
#define NO_AUTO_POLARITY 0x1000
#define TWO_PART_DEFDIS 0x2000
#define LOW_RX_SQUELCH 0x4000
/* PP_SelfCTL - Software Self Control bit definition - Read/write */
#define POWER_ON_RESET 0x0040
#define SW_STOP 0x0100
#define SLEEP_ON 0x0200
#define AUTO_WAKEUP 0x0400
#define HCB0_ENBL 0x1000
#define HCB1_ENBL 0x2000
#define HCB0 0x4000
#define HCB1 0x8000
/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
#define RESET_RX_DMA 0x0040
#define MEMORY_ON 0x0400
#define DMA_BURST_MODE 0x0800
#define IO_CHANNEL_READY_ON 0x1000
#define RX_DMA_SIZE_64K 0x2000
#define ENABLE_IRQ 0x8000
/* PP_TestCTL - Test Control bit definition - Read/write */
#define LINK_OFF 0x0080
#define ENDEC_LOOPBACK 0x0200
#define AUI_LOOPBACK 0x0400
#define BACKOFF_OFF 0x0800
#define FDX_8900 0x4000
#define FAST_TEST 0x8000
/* PP_RxEvent - Receive Event Bit definition - Read-only */
#define RX_IA_HASHED 0x0040
#define RX_DRIBBLE 0x0080
#define RX_OK 0x0100
#define RX_HASHED 0x0200
#define RX_IA 0x0400
#define RX_BROADCAST 0x0800
#define RX_CRC_ERROR 0x1000
#define RX_RUNT 0x2000
#define RX_EXTRA_DATA 0x4000
#define HASH_INDEX_MASK 0x0FC00
/* PP_TxEvent - Transmit Event Bit definition - Read-only */
#define TX_LOST_CRS 0x0040
#define TX_SQE_ERROR 0x0080
#define TX_OK 0x0100
#define TX_LATE_COL 0x0200
#define TX_JBR 0x0400
#define TX_16_COL 0x8000
#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
#define TX_COL_COUNT_MASK 0x7800
/* PP_BufEvent - Buffer Event Bit definition - Read-only */
#define SW_INTERRUPT 0x0040
#define RX_DMA 0x0080
#define READY_FOR_TX 0x0100
#define TX_UNDERRUN 0x0200
#define RX_MISS 0x0400
#define RX_128_BYTE 0x0800
#define TX_COL_OVRFLW 0x1000
#define RX_MISS_OVRFLW 0x2000
#define RX_DEST_MATCH 0x8000
/* PP_LineST - Ethernet Line Status bit definition - Read-only */
#define LINK_OK 0x0080
#define AUI_ON 0x0100
#define TENBASET_ON 0x0200
#define POLARITY_OK 0x1000
#define CRS_OK 0x4000
/* PP_SelfST - Chip Software Status bit definition */
#define ACTIVE_33V 0x0040
#define INIT_DONE 0x0080
#define SI_BUSY 0x0100
#define EEPROM_PRESENT 0x0200
#define EEPROM_OK 0x0400
#define EL_PRESENT 0x0800
#define EE_SIZE_64 0x1000
/* PP_BusST - ISA Bus Status bit definition */
#define TX_BID_ERROR 0x0080
#define READY_FOR_TX_NOW 0x0100
/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
#define RE_NEG_NOW 0x0040
#define ALLOW_FDX 0x0080
#define AUTO_NEG_ENABLE 0x0100
#define NLP_ENABLE 0x0200
#define FORCE_FDX 0x8000
#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
/* PP_AutoNegST - Auto Negotiation Status bit definition */
#define AUTO_NEG_BUSY 0x0080
#define FLP_LINK 0x0100
#define FLP_LINK_GOOD 0x0800
#define LINK_FAULT 0x1000
#define HDX_ACTIVE 0x4000
#define FDX_ACTIVE 0x8000
/* The following block defines the ISQ event types */
#define ISQ_RECEIVER_EVENT 0x04
#define ISQ_TRANSMITTER_EVENT 0x08
#define ISQ_BUFFER_EVENT 0x0c
#define ISQ_RX_MISS_EVENT 0x10
#define ISQ_TX_COL_EVENT 0x12
#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
#define ISQ_HIST 16 /* small history buffer */
#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
#define TXRXBUFSIZE 0x0600
#define RXDMABUFSIZE 0x8000
#define RXDMASIZE 0x4000
#define TXRX_LENGTH_MASK 0x07FF
/* rx options bits */
#define RCV_WITH_RXON 1 /* Set SerRx ON */
#define RCV_COUNTS 2 /* Use Framecnt1 */
#define RCV_PONG 4 /* Pong respondent */
#define RCV_DONG 8 /* Dong operation */
#define RCV_POLLING 0x10 /* Poll RxEvent */
#define RCV_ISQ 0x20 /* Use ISQ, int */
#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
#define RCV_DMA 0x200 /* Set RxDMA only */
#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
#define RCV_FIXED_DATA 0x800 /* Every frame same */
#define RCV_IO 0x1000 /* Use ISA IO only */
#define RCV_MEMORY 0x2000 /* Use ISA Memory */
#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
#define PKT_START PP_TxFrame /* Start of packet RAM */
#define RX_FRAME_PORT 0x0000
#define TX_FRAME_PORT RX_FRAME_PORT
#define TX_CMD_PORT 0x0004
#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
#define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
#define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */
#define TX_LEN_PORT 0x0006
#define ISQ_PORT 0x0008
#define ADD_PORT 0x000A
#define DATA_PORT 0x000C
#define EEPROM_WRITE_EN 0x00F0
#define EEPROM_WRITE_DIS 0x0000
#define EEPROM_WRITE_CMD 0x0100
#define EEPROM_READ_CMD 0x0200
/* Receive Header */
/* Description of header of each packet in receive area of memory */
#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
#define RBUF_LEN_LOW 2 /* Length of received data - low byte */
#define RBUF_LEN_HI 3 /* Length of received data - high byte */
#define RBUF_HEAD_LEN 4 /* Length of this header */
#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
/* for bios scan */
/* */
#ifdef CSDEBUG
/* use these values for debugging bios scan */
#define BIOS_START_SEG 0x00000
#define BIOS_OFFSET_INC 0x0010
#else
#define BIOS_START_SEG 0x0c000
#define BIOS_OFFSET_INC 0x0200
#endif
#define BIOS_LAST_OFFSET 0x0fc00
/* Byte offsets into the EEPROM configuration buffer */
#define ISA_CNF_OFFSET 0x6
#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
/* the assumption here is that the bits in the eeprom are generally */
/* in the same position as those in the autonegctl register. */
/* Of course the IMM bit is not in that register so it must be */
/* masked out */
#define EE_FORCE_FDX 0x8000
#define EE_NLP_ENABLE 0x0200
#define EE_AUTO_NEG_ENABLE 0x0100
#define EE_ALLOW_FDX 0x0080
#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
#define IMM_BIT 0x0040 /* ignore missing media */
#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
#define A_CNF_10B_T 0x0001
#define A_CNF_AUI 0x0002
#define A_CNF_10B_2 0x0004
#define A_CNF_MEDIA_TYPE 0x0070
#define A_CNF_MEDIA_AUTO 0x0070
#define A_CNF_MEDIA_10B_T 0x0020
#define A_CNF_MEDIA_AUI 0x0040
#define A_CNF_MEDIA_10B_2 0x0010
#define A_CNF_DC_DC_POLARITY 0x0080
#define A_CNF_NO_AUTO_POLARITY 0x2000
#define A_CNF_LOW_RX_SQUELCH 0x4000
#define A_CNF_EXTND_10B_2 0x8000
#define PACKET_PAGE_OFFSET 0x8
/* Bit definitions for the ISA configuration word from the EEPROM */
#define INT_NO_MASK 0x000F
#define DMA_NO_MASK 0x0070
#define ISA_DMA_SIZE 0x0200
#define ISA_AUTO_RxDMA 0x0400
#define ISA_RxDMA 0x0800
#define DMA_BURST 0x1000
#define STREAM_TRANSFER 0x2000
#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
/* DMA controller registers */
#define DMA_BASE 0x00 /* DMA controller base */
#define DMA_BASE_2 0x0C0 /* DMA controller base */
#define DMA_STAT 0x0D0 /* DMA controller status register */
#define DMA_MASK 0x0D4 /* DMA controller mask register */
#define DMA_MODE 0x0D6 /* DMA controller mode register */
#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
/* DMA data */
#define DMA_DISABLE 0x04 /* Disable channel n */
#define DMA_ENABLE 0x00 /* Enable channel n */
/* Demand transfers, incr. address, auto init, writes, ch. n */
#define DMA_RX_MODE 0x14
/* Demand transfers, incr. address, auto init, reads, ch. n */
#define DMA_TX_MODE 0x18
#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
#define CS8900 0x0000
#define CS8920 0x4000
#define CS8920M 0x6000
#define REVISON_BITS 0x1F00
#define EEVER_NUMBER 0x12
#define CHKSUM_LEN 0x14
#define CHKSUM_VAL 0x0000
#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
#define PNP_ADD_PORT 0x0279
#define PNP_WRITE_PORT 0x0A79
#define GET_PNP_ISA_STRUCT 0x40
#define PNP_ISA_STRUCT_LEN 0x06
#define PNP_CSN_CNT_OFF 0x01
#define PNP_RD_PORT_OFF 0x02
#define PNP_FUNCTION_OK 0x00
#define PNP_WAKE 0x03
#define PNP_RSRC_DATA 0x04
#define PNP_RSRC_READY 0x01
#define PNP_STATUS 0x05
#define PNP_ACTIVATE 0x30
#define PNP_CNF_IO_H 0x60
#define PNP_CNF_IO_L 0x61
#define PNP_CNF_INT 0x70
#define PNP_CNF_DMA 0x74
#define PNP_CNF_MEM 0x48
#define BIT0 1
#define BIT15 0x8000

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drivers/net/ethernet/cirrus/ep93xx_eth.c Normal file
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/*
* EP93xx ethernet network device driver
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/mii.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#define DRV_MODULE_NAME "ep93xx-eth"
#define DRV_MODULE_VERSION "0.1"
#define RX_QUEUE_ENTRIES 64
#define TX_QUEUE_ENTRIES 8
#define MAX_PKT_SIZE 2044
#define PKT_BUF_SIZE 2048
#define REG_RXCTL 0x0000
#define REG_RXCTL_DEFAULT 0x00073800
#define REG_TXCTL 0x0004
#define REG_TXCTL_ENABLE 0x00000001
#define REG_MIICMD 0x0010
#define REG_MIICMD_READ 0x00008000
#define REG_MIICMD_WRITE 0x00004000
#define REG_MIIDATA 0x0014
#define REG_MIISTS 0x0018
#define REG_MIISTS_BUSY 0x00000001
#define REG_SELFCTL 0x0020
#define REG_SELFCTL_RESET 0x00000001
#define REG_INTEN 0x0024
#define REG_INTEN_TX 0x00000008
#define REG_INTEN_RX 0x00000007
#define REG_INTSTSP 0x0028
#define REG_INTSTS_TX 0x00000008
#define REG_INTSTS_RX 0x00000004
#define REG_INTSTSC 0x002c
#define REG_AFP 0x004c
#define REG_INDAD0 0x0050
#define REG_INDAD1 0x0051
#define REG_INDAD2 0x0052
#define REG_INDAD3 0x0053
#define REG_INDAD4 0x0054
#define REG_INDAD5 0x0055
#define REG_GIINTMSK 0x0064
#define REG_GIINTMSK_ENABLE 0x00008000
#define REG_BMCTL 0x0080
#define REG_BMCTL_ENABLE_TX 0x00000100
#define REG_BMCTL_ENABLE_RX 0x00000001
#define REG_BMSTS 0x0084
#define REG_BMSTS_RX_ACTIVE 0x00000008
#define REG_RXDQBADD 0x0090
#define REG_RXDQBLEN 0x0094
#define REG_RXDCURADD 0x0098
#define REG_RXDENQ 0x009c
#define REG_RXSTSQBADD 0x00a0
#define REG_RXSTSQBLEN 0x00a4
#define REG_RXSTSQCURADD 0x00a8
#define REG_RXSTSENQ 0x00ac
#define REG_TXDQBADD 0x00b0
#define REG_TXDQBLEN 0x00b4
#define REG_TXDQCURADD 0x00b8
#define REG_TXDENQ 0x00bc
#define REG_TXSTSQBADD 0x00c0
#define REG_TXSTSQBLEN 0x00c4
#define REG_TXSTSQCURADD 0x00c8
#define REG_MAXFRMLEN 0x00e8
struct ep93xx_rdesc
{
u32 buf_addr;
u32 rdesc1;
};
#define RDESC1_NSOF 0x80000000
#define RDESC1_BUFFER_INDEX 0x7fff0000
#define RDESC1_BUFFER_LENGTH 0x0000ffff
struct ep93xx_rstat
{
u32 rstat0;
u32 rstat1;
};
#define RSTAT0_RFP 0x80000000
#define RSTAT0_RWE 0x40000000
#define RSTAT0_EOF 0x20000000
#define RSTAT0_EOB 0x10000000
#define RSTAT0_AM 0x00c00000
#define RSTAT0_RX_ERR 0x00200000
#define RSTAT0_OE 0x00100000
#define RSTAT0_FE 0x00080000
#define RSTAT0_RUNT 0x00040000
#define RSTAT0_EDATA 0x00020000
#define RSTAT0_CRCE 0x00010000
#define RSTAT0_CRCI 0x00008000
#define RSTAT0_HTI 0x00003f00
#define RSTAT1_RFP 0x80000000
#define RSTAT1_BUFFER_INDEX 0x7fff0000
#define RSTAT1_FRAME_LENGTH 0x0000ffff
struct ep93xx_tdesc
{
u32 buf_addr;
u32 tdesc1;
};
#define TDESC1_EOF 0x80000000
#define TDESC1_BUFFER_INDEX 0x7fff0000
#define TDESC1_BUFFER_ABORT 0x00008000
#define TDESC1_BUFFER_LENGTH 0x00000fff
struct ep93xx_tstat
{
u32 tstat0;
};
#define TSTAT0_TXFP 0x80000000
#define TSTAT0_TXWE 0x40000000
#define TSTAT0_FA 0x20000000
#define TSTAT0_LCRS 0x10000000
#define TSTAT0_OW 0x04000000
#define TSTAT0_TXU 0x02000000
#define TSTAT0_ECOLL 0x01000000
#define TSTAT0_NCOLL 0x001f0000
#define TSTAT0_BUFFER_INDEX 0x00007fff
struct ep93xx_descs
{
struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
};
struct ep93xx_priv
{
struct resource *res;
void __iomem *base_addr;
int irq;
struct ep93xx_descs *descs;
dma_addr_t descs_dma_addr;
void *rx_buf[RX_QUEUE_ENTRIES];
void *tx_buf[TX_QUEUE_ENTRIES];
spinlock_t rx_lock;
unsigned int rx_pointer;
unsigned int tx_clean_pointer;
unsigned int tx_pointer;
spinlock_t tx_pending_lock;
unsigned int tx_pending;
struct net_device *dev;
struct napi_struct napi;
struct mii_if_info mii;
u8 mdc_divisor;
};
#define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
#define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
#define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
#define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
#define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
#define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
{
struct ep93xx_priv *ep = netdev_priv(dev);
int data;
int i;
wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
for (i = 0; i < 10; i++) {
if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
break;
msleep(1);
}
if (i == 10) {
pr_info("mdio read timed out\n");
data = 0xffff;
} else {
data = rdl(ep, REG_MIIDATA);
}
return data;
}
static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
{
struct ep93xx_priv *ep = netdev_priv(dev);
int i;
wrl(ep, REG_MIIDATA, data);
wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
for (i = 0; i < 10; i++) {
if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
break;
msleep(1);
}
if (i == 10)
pr_info("mdio write timed out\n");
}
static int ep93xx_rx(struct net_device *dev, int processed, int budget)
{
struct ep93xx_priv *ep = netdev_priv(dev);
while (processed < budget) {
int entry;
struct ep93xx_rstat *rstat;
u32 rstat0;
u32 rstat1;
int length;
struct sk_buff *skb;
entry = ep->rx_pointer;
rstat = ep->descs->rstat + entry;
rstat0 = rstat->rstat0;
rstat1 = rstat->rstat1;
if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
break;
rstat->rstat0 = 0;
rstat->rstat1 = 0;
if (!(rstat0 & RSTAT0_EOF))
pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
if (!(rstat0 & RSTAT0_EOB))
pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
if (!(rstat0 & RSTAT0_RWE)) {
dev->stats.rx_errors++;
if (rstat0 & RSTAT0_OE)
dev->stats.rx_fifo_errors++;
if (rstat0 & RSTAT0_FE)
dev->stats.rx_frame_errors++;
if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
dev->stats.rx_length_errors++;
if (rstat0 & RSTAT0_CRCE)
dev->stats.rx_crc_errors++;
goto err;
}
length = rstat1 & RSTAT1_FRAME_LENGTH;
if (length > MAX_PKT_SIZE) {
pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
goto err;
}
/* Strip FCS. */
if (rstat0 & RSTAT0_CRCI)
length -= 4;
skb = netdev_alloc_skb(dev, length + 2);
if (likely(skb != NULL)) {
struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
skb_reserve(skb, 2);
dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
length, DMA_FROM_DEVICE);
skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
dma_sync_single_for_device(dev->dev.parent,
rxd->buf_addr, length,
DMA_FROM_DEVICE);
skb_put(skb, length);
skb->protocol = eth_type_trans(skb, dev);
netif_receive_skb(skb);
dev->stats.rx_packets++;
dev->stats.rx_bytes += length;
} else {
dev->stats.rx_dropped++;
}
err:
ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
processed++;
}
return processed;
}
static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
{
struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
}
static int ep93xx_poll(struct napi_struct *napi, int budget)
{
struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
struct net_device *dev = ep->dev;
int rx = 0;
poll_some_more:
rx = ep93xx_rx(dev, rx, budget);
if (rx < budget) {
int more = 0;
spin_lock_irq(&ep->rx_lock);
__napi_complete(napi);
wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
if (ep93xx_have_more_rx(ep)) {
wrl(ep, REG_INTEN, REG_INTEN_TX);
wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
more = 1;
}
spin_unlock_irq(&ep->rx_lock);
if (more && napi_reschedule(napi))
goto poll_some_more;
}
if (rx) {
wrw(ep, REG_RXDENQ, rx);
wrw(ep, REG_RXSTSENQ, rx);
}
return rx;
}
static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
struct ep93xx_tdesc *txd;
int entry;
if (unlikely(skb->len > MAX_PKT_SIZE)) {
dev->stats.tx_dropped++;
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
entry = ep->tx_pointer;
ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
txd = &ep->descs->tdesc[entry];
txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
DMA_TO_DEVICE);
skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
DMA_TO_DEVICE);
dev_kfree_skb(skb);
spin_lock_irq(&ep->tx_pending_lock);
ep->tx_pending++;
if (ep->tx_pending == TX_QUEUE_ENTRIES)
netif_stop_queue(dev);
spin_unlock_irq(&ep->tx_pending_lock);
wrl(ep, REG_TXDENQ, 1);
return NETDEV_TX_OK;
}
static void ep93xx_tx_complete(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
int wake;
wake = 0;
spin_lock(&ep->tx_pending_lock);
while (1) {
int entry;
struct ep93xx_tstat *tstat;
u32 tstat0;
entry = ep->tx_clean_pointer;
tstat = ep->descs->tstat + entry;
tstat0 = tstat->tstat0;
if (!(tstat0 & TSTAT0_TXFP))
break;
tstat->tstat0 = 0;
if (tstat0 & TSTAT0_FA)
pr_crit("frame aborted %.8x\n", tstat0);
if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
pr_crit("entry mismatch %.8x\n", tstat0);
if (tstat0 & TSTAT0_TXWE) {
int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
dev->stats.tx_packets++;
dev->stats.tx_bytes += length;
} else {
dev->stats.tx_errors++;
}
if (tstat0 & TSTAT0_OW)
dev->stats.tx_window_errors++;
if (tstat0 & TSTAT0_TXU)
dev->stats.tx_fifo_errors++;
dev->stats.collisions += (tstat0 >> 16) & 0x1f;
ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
if (ep->tx_pending == TX_QUEUE_ENTRIES)
wake = 1;
ep->tx_pending--;
}
spin_unlock(&ep->tx_pending_lock);
if (wake)
netif_wake_queue(dev);
}
static irqreturn_t ep93xx_irq(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct ep93xx_priv *ep = netdev_priv(dev);
u32 status;
status = rdl(ep, REG_INTSTSC);
if (status == 0)
return IRQ_NONE;
if (status & REG_INTSTS_RX) {
spin_lock(&ep->rx_lock);
if (likely(napi_schedule_prep(&ep->napi))) {
wrl(ep, REG_INTEN, REG_INTEN_TX);
__napi_schedule(&ep->napi);
}
spin_unlock(&ep->rx_lock);
}
if (status & REG_INTSTS_TX)
ep93xx_tx_complete(dev);
return IRQ_HANDLED;
}
static void ep93xx_free_buffers(struct ep93xx_priv *ep)
{
struct device *dev = ep->dev->dev.parent;
int i;
for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
dma_addr_t d;
d = ep->descs->rdesc[i].buf_addr;
if (d)
dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
if (ep->rx_buf[i] != NULL)
kfree(ep->rx_buf[i]);
}
for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
dma_addr_t d;
d = ep->descs->tdesc[i].buf_addr;
if (d)
dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
if (ep->tx_buf[i] != NULL)
kfree(ep->tx_buf[i]);
}
dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
ep->descs_dma_addr);
}
static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
{
struct device *dev = ep->dev->dev.parent;
int i;
ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
&ep->descs_dma_addr, GFP_KERNEL);
if (ep->descs == NULL)
return 1;
for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
void *buf;
dma_addr_t d;
buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
if (buf == NULL)
goto err;
d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
if (dma_mapping_error(dev, d)) {
kfree(buf);
goto err;
}
ep->rx_buf[i] = buf;
ep->descs->rdesc[i].buf_addr = d;
ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
}
for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
void *buf;
dma_addr_t d;
buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
if (buf == NULL)
goto err;
d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
if (dma_mapping_error(dev, d)) {
kfree(buf);
goto err;
}
ep->tx_buf[i] = buf;
ep->descs->tdesc[i].buf_addr = d;
}
return 0;
err:
ep93xx_free_buffers(ep);
return 1;
}
static int ep93xx_start_hw(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
unsigned long addr;
int i;
wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
for (i = 0; i < 10; i++) {
if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
break;
msleep(1);
}
if (i == 10) {
pr_crit("hw failed to reset\n");
return 1;
}
wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
/* Does the PHY support preamble suppress? */
if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
/* Receive descriptor ring. */
addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
wrl(ep, REG_RXDQBADD, addr);
wrl(ep, REG_RXDCURADD, addr);
wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
/* Receive status ring. */
addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
wrl(ep, REG_RXSTSQBADD, addr);
wrl(ep, REG_RXSTSQCURADD, addr);
wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
/* Transmit descriptor ring. */
addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
wrl(ep, REG_TXDQBADD, addr);
wrl(ep, REG_TXDQCURADD, addr);
wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
/* Transmit status ring. */
addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
wrl(ep, REG_TXSTSQBADD, addr);
wrl(ep, REG_TXSTSQCURADD, addr);
wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
wrl(ep, REG_GIINTMSK, 0);
for (i = 0; i < 10; i++) {
if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
break;
msleep(1);
}
if (i == 10) {
pr_crit("hw failed to start\n");
return 1;
}
wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
wrb(ep, REG_INDAD0, dev->dev_addr[0]);
wrb(ep, REG_INDAD1, dev->dev_addr[1]);
wrb(ep, REG_INDAD2, dev->dev_addr[2]);
wrb(ep, REG_INDAD3, dev->dev_addr[3]);
wrb(ep, REG_INDAD4, dev->dev_addr[4]);
wrb(ep, REG_INDAD5, dev->dev_addr[5]);
wrl(ep, REG_AFP, 0);
wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
return 0;
}
static void ep93xx_stop_hw(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
int i;
wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
for (i = 0; i < 10; i++) {
if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
break;
msleep(1);
}
if (i == 10)
pr_crit("hw failed to reset\n");
}
static int ep93xx_open(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
int err;
if (ep93xx_alloc_buffers(ep))
return -ENOMEM;
napi_enable(&ep->napi);
if (ep93xx_start_hw(dev)) {
napi_disable(&ep->napi);
ep93xx_free_buffers(ep);
return -EIO;
}
spin_lock_init(&ep->rx_lock);
ep->rx_pointer = 0;
ep->tx_clean_pointer = 0;
ep->tx_pointer = 0;
spin_lock_init(&ep->tx_pending_lock);
ep->tx_pending = 0;
err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
if (err) {
napi_disable(&ep->napi);
ep93xx_stop_hw(dev);
ep93xx_free_buffers(ep);
return err;
}
wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
netif_start_queue(dev);
return 0;
}
static int ep93xx_close(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
napi_disable(&ep->napi);
netif_stop_queue(dev);
wrl(ep, REG_GIINTMSK, 0);
free_irq(ep->irq, dev);
ep93xx_stop_hw(dev);
ep93xx_free_buffers(ep);
return 0;
}
static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct ep93xx_priv *ep = netdev_priv(dev);
struct mii_ioctl_data *data = if_mii(ifr);
return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
}
static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
}
static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct ep93xx_priv *ep = netdev_priv(dev);
return mii_ethtool_gset(&ep->mii, cmd);
}
static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct ep93xx_priv *ep = netdev_priv(dev);
return mii_ethtool_sset(&ep->mii, cmd);
}
static int ep93xx_nway_reset(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
return mii_nway_restart(&ep->mii);
}
static u32 ep93xx_get_link(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
return mii_link_ok(&ep->mii);
}
static const struct ethtool_ops ep93xx_ethtool_ops = {
.get_drvinfo = ep93xx_get_drvinfo,
.get_settings = ep93xx_get_settings,
.set_settings = ep93xx_set_settings,
.nway_reset = ep93xx_nway_reset,
.get_link = ep93xx_get_link,
};
static const struct net_device_ops ep93xx_netdev_ops = {
.ndo_open = ep93xx_open,
.ndo_stop = ep93xx_close,
.ndo_start_xmit = ep93xx_xmit,
.ndo_do_ioctl = ep93xx_ioctl,
.ndo_validate_addr = eth_validate_addr,
.ndo_change_mtu = eth_change_mtu,
.ndo_set_mac_address = eth_mac_addr,
};
static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
{
struct net_device *dev;
dev = alloc_etherdev(sizeof(struct ep93xx_priv));
if (dev == NULL)
return NULL;
memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
dev->ethtool_ops = &ep93xx_ethtool_ops;
dev->netdev_ops = &ep93xx_netdev_ops;
dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
return dev;
}
static int ep93xx_eth_remove(struct platform_device *pdev)
{
struct net_device *dev;
struct ep93xx_priv *ep;
dev = platform_get_drvdata(pdev);
if (dev == NULL)
return 0;
platform_set_drvdata(pdev, NULL);
ep = netdev_priv(dev);
/* @@@ Force down. */
unregister_netdev(dev);
ep93xx_free_buffers(ep);
if (ep->base_addr != NULL)
iounmap(ep->base_addr);
if (ep->res != NULL) {
release_resource(ep->res);
kfree(ep->res);
}
free_netdev(dev);
return 0;
}
static int ep93xx_eth_probe(struct platform_device *pdev)
{
struct ep93xx_eth_data *data;
struct net_device *dev;
struct ep93xx_priv *ep;
struct resource *mem;
int irq;
int err;
if (pdev == NULL)
return -ENODEV;
data = pdev->dev.platform_data;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!mem || irq < 0)
return -ENXIO;
dev = ep93xx_dev_alloc(data);
if (dev == NULL) {
err = -ENOMEM;
goto err_out;
}
ep = netdev_priv(dev);
ep->dev = dev;
SET_NETDEV_DEV(dev, &pdev->dev);
netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
platform_set_drvdata(pdev, dev);
ep->res = request_mem_region(mem->start, resource_size(mem),
dev_name(&pdev->dev));
if (ep->res == NULL) {
dev_err(&pdev->dev, "Could not reserve memory region\n");
err = -ENOMEM;
goto err_out;
}
ep->base_addr = ioremap(mem->start, resource_size(mem));
if (ep->base_addr == NULL) {
dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
err = -EIO;
goto err_out;
}
ep->irq = irq;
ep->mii.phy_id = data->phy_id;
ep->mii.phy_id_mask = 0x1f;
ep->mii.reg_num_mask = 0x1f;
ep->mii.dev = dev;
ep->mii.mdio_read = ep93xx_mdio_read;
ep->mii.mdio_write = ep93xx_mdio_write;
ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
if (is_zero_ether_addr(dev->dev_addr))
eth_hw_addr_random(dev);
err = register_netdev(dev);
if (err) {
dev_err(&pdev->dev, "Failed to register netdev\n");
goto err_out;
}
printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
dev->name, ep->irq, dev->dev_addr);
return 0;
err_out:
ep93xx_eth_remove(pdev);
return err;
}
static struct platform_driver ep93xx_eth_driver = {
.probe = ep93xx_eth_probe,
.remove = ep93xx_eth_remove,
.driver = {
.name = "ep93xx-eth",
.owner = THIS_MODULE,
},
};
module_platform_driver(ep93xx_eth_driver);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ep93xx-eth");

637
drivers/net/ethernet/cirrus/mac89x0.c Normal file
View File

@@ -0,0 +1,637 @@
/* mac89x0.c: A Crystal Semiconductor CS89[02]0 driver for linux. */
/*
Written 1996 by Russell Nelson, with reference to skeleton.c
written 1993-1994 by Donald Becker.
This software may be used and distributed according to the terms
of the GNU General Public License, incorporated herein by reference.
The author may be reached at nelson@crynwr.com, Crynwr
Software, 11 Grant St., Potsdam, NY 13676
Changelog:
Mike Cruse : mcruse@cti-ltd.com
: Changes for Linux 2.0 compatibility.
: Added dev_id parameter in net_interrupt(),
: request_irq() and free_irq(). Just NULL for now.
Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros
: in net_open() and net_close() so kerneld would know
: that the module is in use and wouldn't eject the
: driver prematurely.
Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c
: as an example. Disabled autoprobing in init_module(),
: not a good thing to do to other devices while Linux
: is running from all accounts.
Alan Cox : Removed 1.2 support, added 2.1 extra counters.
David Huggins-Daines <dhd@debian.org>
Split this off into mac89x0.c, and gutted it of all parts which are
not relevant to the existing CS8900 cards on the Macintosh
(i.e. basically the Daynaport CS and LC cards). To be precise:
* Removed all the media-detection stuff, because these cards are
TP-only.
* Lobotomized the ISA interrupt bogosity, because these cards use
a hardwired NuBus interrupt and a magic ISAIRQ value in the card.
* Basically eliminated everything not relevant to getting the
cards minimally functioning on the Macintosh.
I might add that these cards are badly designed even from the Mac
standpoint, in that Dayna, in their infinite wisdom, used NuBus slot
I/O space and NuBus interrupts for these cards, but neglected to
provide anything even remotely resembling a NuBus ROM. Therefore we
have to probe for them in a brain-damaged ISA-like fashion.
Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 11/01/2001
check kmalloc and release the allocated memory on failure in
mac89x0_probe and in init_module
use local_irq_{save,restore}(flags) in net_get_stat, not just
local_irq_{dis,en}able()
*/
static char *version =
"cs89x0.c:v1.02 11/26/96 Russell Nelson <nelson@crynwr.com>\n";
/* ======================= configure the driver here ======================= */
/* use 0 for production, 1 for verification, >2 for debug */
#ifndef NET_DEBUG
#define NET_DEBUG 0
#endif
/* ======================= end of configuration ======================= */
/* Always include 'config.h' first in case the user wants to turn on
or override something. */
#include <linux/module.h>
/*
Sources:
Crynwr packet driver epktisa.
Crystal Semiconductor data sheets.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/in.h>
#include <linux/string.h>
#include <linux/nubus.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/gfp.h>
#include <asm/io.h>
#include <asm/hwtest.h>
#include <asm/macints.h>
#include "cs89x0.h"
static unsigned int net_debug = NET_DEBUG;
/* Information that need to be kept for each board. */
struct net_local {
int chip_type; /* one of: CS8900, CS8920, CS8920M */
char chip_revision; /* revision letter of the chip ('A'...) */
int send_cmd; /* the propercommand used to send a packet. */
int rx_mode;
int curr_rx_cfg;
int send_underrun; /* keep track of how many underruns in a row we get */
struct sk_buff *skb;
};
/* Index to functions, as function prototypes. */
#if 0
extern void reset_chip(struct net_device *dev);
#endif
static int net_open(struct net_device *dev);
static int net_send_packet(struct sk_buff *skb, struct net_device *dev);
static irqreturn_t net_interrupt(int irq, void *dev_id);
static void set_multicast_list(struct net_device *dev);
static void net_rx(struct net_device *dev);
static int net_close(struct net_device *dev);
static struct net_device_stats *net_get_stats(struct net_device *dev);
static int set_mac_address(struct net_device *dev, void *addr);
/* Example routines you must write ;->. */
#define tx_done(dev) 1
/* For reading/writing registers ISA-style */
static inline int
readreg_io(struct net_device *dev, int portno)
{
nubus_writew(swab16(portno), dev->base_addr + ADD_PORT);
return swab16(nubus_readw(dev->base_addr + DATA_PORT));
}
static inline void
writereg_io(struct net_device *dev, int portno, int value)
{
nubus_writew(swab16(portno), dev->base_addr + ADD_PORT);
nubus_writew(swab16(value), dev->base_addr + DATA_PORT);
}
/* These are for reading/writing registers in shared memory */
static inline int
readreg(struct net_device *dev, int portno)
{
return swab16(nubus_readw(dev->mem_start + portno));
}
static inline void
writereg(struct net_device *dev, int portno, int value)
{
nubus_writew(swab16(value), dev->mem_start + portno);
}
static const struct net_device_ops mac89x0_netdev_ops = {
.ndo_open = net_open,
.ndo_stop = net_close,
.ndo_start_xmit = net_send_packet,
.ndo_get_stats = net_get_stats,
.ndo_set_rx_mode = set_multicast_list,
.ndo_set_mac_address = set_mac_address,
.ndo_validate_addr = eth_validate_addr,
.ndo_change_mtu = eth_change_mtu,
};
/* Probe for the CS8900 card in slot E. We won't bother looking
anywhere else until we have a really good reason to do so. */
struct net_device * __init mac89x0_probe(int unit)
{
struct net_device *dev;
static int once_is_enough;
struct net_local *lp;
static unsigned version_printed;
int i, slot;
unsigned rev_type = 0;
unsigned long ioaddr;
unsigned short sig;
int err = -ENODEV;
if (!MACH_IS_MAC)
return ERR_PTR(-ENODEV);
dev = alloc_etherdev(sizeof(struct net_local));
if (!dev)
return ERR_PTR(-ENOMEM);
if (unit >= 0) {
sprintf(dev->name, "eth%d", unit);
netdev_boot_setup_check(dev);
}
if (once_is_enough)
goto out;
once_is_enough = 1;
/* We might have to parameterize this later */
slot = 0xE;
/* Get out now if there's a real NuBus card in slot E */
if (nubus_find_slot(slot, NULL) != NULL)
goto out;
/* The pseudo-ISA bits always live at offset 0x300 (gee,
wonder why...) */
ioaddr = (unsigned long)
nubus_slot_addr(slot) | (((slot&0xf) << 20) + DEFAULTIOBASE);
{
unsigned long flags;
int card_present;
local_irq_save(flags);
card_present = (hwreg_present((void*) ioaddr+4) &&
hwreg_present((void*) ioaddr + DATA_PORT));
local_irq_restore(flags);
if (!card_present)
goto out;
}
nubus_writew(0, ioaddr + ADD_PORT);
sig = nubus_readw(ioaddr + DATA_PORT);
if (sig != swab16(CHIP_EISA_ID_SIG))
goto out;
/* Initialize the net_device structure. */
lp = netdev_priv(dev);
/* Fill in the 'dev' fields. */
dev->base_addr = ioaddr;
dev->mem_start = (unsigned long)
nubus_slot_addr(slot) | (((slot&0xf) << 20) + MMIOBASE);
dev->mem_end = dev->mem_start + 0x1000;
/* Turn on shared memory */
writereg_io(dev, PP_BusCTL, MEMORY_ON);
/* get the chip type */
rev_type = readreg(dev, PRODUCT_ID_ADD);
lp->chip_type = rev_type &~ REVISON_BITS;
lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A';
/* Check the chip type and revision in order to set the correct send command
CS8920 revision C and CS8900 revision F can use the faster send. */
lp->send_cmd = TX_AFTER_381;
if (lp->chip_type == CS8900 && lp->chip_revision >= 'F')
lp->send_cmd = TX_NOW;
if (lp->chip_type != CS8900 && lp->chip_revision >= 'C')
lp->send_cmd = TX_NOW;
if (net_debug && version_printed++ == 0)
printk(version);
printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#8lx",
dev->name,
lp->chip_type==CS8900?'0':'2',
lp->chip_type==CS8920M?"M":"",
lp->chip_revision,
dev->base_addr);
/* Try to read the MAC address */
if ((readreg(dev, PP_SelfST) & (EEPROM_PRESENT | EEPROM_OK)) == 0) {
printk("\nmac89x0: No EEPROM, giving up now.\n");
goto out1;
} else {
for (i = 0; i < ETH_ALEN; i += 2) {
/* Big-endian (why??!) */
unsigned short s = readreg(dev, PP_IA + i);
dev->dev_addr[i] = s >> 8;
dev->dev_addr[i+1] = s & 0xff;
}
}
dev->irq = SLOT2IRQ(slot);
/* print the IRQ and ethernet address. */
printk(" IRQ %d ADDR %pM\n", dev->irq, dev->dev_addr);
dev->netdev_ops = &mac89x0_netdev_ops;
err = register_netdev(dev);
if (err)
goto out1;
return NULL;
out1:
nubus_writew(0, dev->base_addr + ADD_PORT);
out:
free_netdev(dev);
return ERR_PTR(err);
}
#if 0
/* This is useful for something, but I don't know what yet. */
void __init reset_chip(struct net_device *dev)
{
int reset_start_time;
writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
/* wait 30 ms */
msleep_interruptible(30);
/* Wait until the chip is reset */
reset_start_time = jiffies;
while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2)
;
}
#endif
/* Open/initialize the board. This is called (in the current kernel)
sometime after booting when the 'ifconfig' program is run.
This routine should set everything up anew at each open, even
registers that "should" only need to be set once at boot, so that
there is non-reboot way to recover if something goes wrong.
*/
static int
net_open(struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
int i;
/* Disable the interrupt for now */
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ);
/* Grab the interrupt */
if (request_irq(dev->irq, net_interrupt, 0, "cs89x0", dev))
return -EAGAIN;
/* Set up the IRQ - Apparently magic */
if (lp->chip_type == CS8900)
writereg(dev, PP_CS8900_ISAINT, 0);
else
writereg(dev, PP_CS8920_ISAINT, 0);
/* set the Ethernet address */
for (i=0; i < ETH_ALEN/2; i++)
writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
/* Turn on both receive and transmit operations */
writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON);
/* Receive only error free packets addressed to this card */
lp->rx_mode = 0;
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT);
lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL;
writereg(dev, PP_RxCFG, lp->curr_rx_cfg);
writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL |
TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL);
writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL |
TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL);
/* now that we've got our act together, enable everything */
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ);
netif_start_queue(dev);
return 0;
}
static int
net_send_packet(struct sk_buff *skb, struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
unsigned long flags;
if (net_debug > 3)
printk("%s: sent %d byte packet of type %x\n",
dev->name, skb->len,
(skb->data[ETH_ALEN+ETH_ALEN] << 8)
| skb->data[ETH_ALEN+ETH_ALEN+1]);
/* keep the upload from being interrupted, since we
ask the chip to start transmitting before the
whole packet has been completely uploaded. */
local_irq_save(flags);
netif_stop_queue(dev);
/* initiate a transmit sequence */
writereg(dev, PP_TxCMD, lp->send_cmd);
writereg(dev, PP_TxLength, skb->len);
/* Test to see if the chip has allocated memory for the packet */
if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) {
/* Gasp! It hasn't. But that shouldn't happen since
we're waiting for TxOk, so return 1 and requeue this packet. */
local_irq_restore(flags);
return NETDEV_TX_BUSY;
}
/* Write the contents of the packet */
skb_copy_from_linear_data(skb, (void *)(dev->mem_start + PP_TxFrame),
skb->len+1);
local_irq_restore(flags);
dev_kfree_skb (skb);
return NETDEV_TX_OK;
}
/* The typical workload of the driver:
Handle the network interface interrupts. */
static irqreturn_t net_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct net_local *lp;
int ioaddr, status;
if (dev == NULL) {
printk ("net_interrupt(): irq %d for unknown device.\n", irq);
return IRQ_NONE;
}
ioaddr = dev->base_addr;
lp = netdev_priv(dev);
/* we MUST read all the events out of the ISQ, otherwise we'll never
get interrupted again. As a consequence, we can't have any limit
on the number of times we loop in the interrupt handler. The
hardware guarantees that eventually we'll run out of events. Of
course, if you're on a slow machine, and packets are arriving
faster than you can read them off, you're screwed. Hasta la
vista, baby! */
while ((status = swab16(nubus_readw(dev->base_addr + ISQ_PORT)))) {
if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status);
switch(status & ISQ_EVENT_MASK) {
case ISQ_RECEIVER_EVENT:
/* Got a packet(s). */
net_rx(dev);
break;
case ISQ_TRANSMITTER_EVENT:
dev->stats.tx_packets++;
netif_wake_queue(dev);
if ((status & TX_OK) == 0)
dev->stats.tx_errors++;
if (status & TX_LOST_CRS)
dev->stats.tx_carrier_errors++;
if (status & TX_SQE_ERROR)
dev->stats.tx_heartbeat_errors++;
if (status & TX_LATE_COL)
dev->stats.tx_window_errors++;
if (status & TX_16_COL)
dev->stats.tx_aborted_errors++;
break;
case ISQ_BUFFER_EVENT:
if (status & READY_FOR_TX) {
/* we tried to transmit a packet earlier,
but inexplicably ran out of buffers.
That shouldn't happen since we only ever
load one packet. Shrug. Do the right
thing anyway. */
netif_wake_queue(dev);
}
if (status & TX_UNDERRUN) {
if (net_debug > 0) printk("%s: transmit underrun\n", dev->name);
lp->send_underrun++;
if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381;
else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL;
}
break;
case ISQ_RX_MISS_EVENT:
dev->stats.rx_missed_errors += (status >> 6);
break;
case ISQ_TX_COL_EVENT:
dev->stats.collisions += (status >> 6);
break;
}
}
return IRQ_HANDLED;
}
/* We have a good packet(s), get it/them out of the buffers. */
static void
net_rx(struct net_device *dev)
{
struct sk_buff *skb;
int status, length;
status = readreg(dev, PP_RxStatus);
if ((status & RX_OK) == 0) {
dev->stats.rx_errors++;
if (status & RX_RUNT)
dev->stats.rx_length_errors++;
if (status & RX_EXTRA_DATA)
dev->stats.rx_length_errors++;
if ((status & RX_CRC_ERROR) &&
!(status & (RX_EXTRA_DATA|RX_RUNT)))
/* per str 172 */
dev->stats.rx_crc_errors++;
if (status & RX_DRIBBLE)
dev->stats.rx_frame_errors++;
return;
}
length = readreg(dev, PP_RxLength);
/* Malloc up new buffer. */
skb = alloc_skb(length, GFP_ATOMIC);
if (skb == NULL) {
printk("%s: Memory squeeze, dropping packet.\n", dev->name);
dev->stats.rx_dropped++;
return;
}
skb_put(skb, length);
skb_copy_to_linear_data(skb, (void *)(dev->mem_start + PP_RxFrame),
length);
if (net_debug > 3)printk("%s: received %d byte packet of type %x\n",
dev->name, length,
(skb->data[ETH_ALEN+ETH_ALEN] << 8)
| skb->data[ETH_ALEN+ETH_ALEN+1]);
skb->protocol=eth_type_trans(skb,dev);
netif_rx(skb);
dev->stats.rx_packets++;
dev->stats.rx_bytes += length;
}
/* The inverse routine to net_open(). */
static int
net_close(struct net_device *dev)
{
writereg(dev, PP_RxCFG, 0);
writereg(dev, PP_TxCFG, 0);
writereg(dev, PP_BufCFG, 0);
writereg(dev, PP_BusCTL, 0);
netif_stop_queue(dev);
free_irq(dev->irq, dev);
/* Update the statistics here. */
return 0;
}
/* Get the current statistics. This may be called with the card open or
closed. */
static struct net_device_stats *
net_get_stats(struct net_device *dev)
{
unsigned long flags;
local_irq_save(flags);
/* Update the statistics from the device registers. */
dev->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6);
dev->stats.collisions += (readreg(dev, PP_TxCol) >> 6);
local_irq_restore(flags);
return &dev->stats;
}
static void set_multicast_list(struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
if(dev->flags&IFF_PROMISC)
{
lp->rx_mode = RX_ALL_ACCEPT;
} else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
/* The multicast-accept list is initialized to accept-all, and we
rely on higher-level filtering for now. */
lp->rx_mode = RX_MULTCAST_ACCEPT;
}
else
lp->rx_mode = 0;
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode);
/* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */
writereg(dev, PP_RxCFG, lp->curr_rx_cfg |
(lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0));
}
static int set_mac_address(struct net_device *dev, void *addr)
{
struct sockaddr *saddr = addr;
int i;
if (!is_valid_ether_addr(saddr->sa_data))
return -EADDRNOTAVAIL;
memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
printk("%s: Setting MAC address to %pM\n", dev->name, dev->dev_addr);
/* set the Ethernet address */
for (i=0; i < ETH_ALEN/2; i++)
writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
return 0;
}
#ifdef MODULE
static struct net_device *dev_cs89x0;
static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "CS89[02]0 debug level (0-5)");
MODULE_LICENSE("GPL");
int __init
init_module(void)
{
net_debug = debug;
dev_cs89x0 = mac89x0_probe(-1);
if (IS_ERR(dev_cs89x0)) {
printk(KERN_WARNING "mac89x0.c: No card found\n");
return PTR_ERR(dev_cs89x0);
}
return 0;
}
void
cleanup_module(void)
{
unregister_netdev(dev_cs89x0);
nubus_writew(0, dev_cs89x0->base_addr + ADD_PORT);
free_netdev(dev_cs89x0);
}
#endif /* MODULE */