nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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141
drivers/gpu/drm/nouveau/core/subdev/bar/base.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/object.h>
#include <subdev/fb.h>
#include <subdev/vm.h>
#include "priv.h"
struct nouveau_barobj {
struct nouveau_object base;
struct nouveau_vma vma;
void __iomem *iomem;
};
static int
nouveau_barobj_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *mem, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_bar *bar = (void *)engine;
struct nouveau_barobj *barobj;
int ret;
ret = nouveau_object_create(parent, engine, oclass, 0, &barobj);
*pobject = nv_object(barobj);
if (ret)
return ret;
ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma);
if (ret)
return ret;
barobj->iomem = bar->iomem + (u32)barobj->vma.offset;
return 0;
}
static void
nouveau_barobj_dtor(struct nouveau_object *object)
{
struct nouveau_bar *bar = (void *)object->engine;
struct nouveau_barobj *barobj = (void *)object;
if (barobj->vma.node)
bar->unmap(bar, &barobj->vma);
nouveau_object_destroy(&barobj->base);
}
static u32
nouveau_barobj_rd32(struct nouveau_object *object, u64 addr)
{
struct nouveau_barobj *barobj = (void *)object;
return ioread32_native(barobj->iomem + addr);
}
static void
nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
{
struct nouveau_barobj *barobj = (void *)object;
iowrite32_native(data, barobj->iomem + addr);
}
static struct nouveau_oclass
nouveau_barobj_oclass = {
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nouveau_barobj_ctor,
.dtor = nouveau_barobj_dtor,
.init = nouveau_object_init,
.fini = nouveau_object_fini,
.rd32 = nouveau_barobj_rd32,
.wr32 = nouveau_barobj_wr32,
},
};
int
nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent,
struct nouveau_mem *mem, struct nouveau_object **pobject)
{
struct nouveau_object *engine = nv_object(bar);
return nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass,
mem, 0, pobject);
}
int
nouveau_bar_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, int length, void **pobject)
{
struct nouveau_device *device = nv_device(parent);
struct nouveau_bar *bar;
int ret;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL",
"bar", length, pobject);
bar = *pobject;
if (ret)
return ret;
if (nv_device_resource_len(device, 3) != 0)
bar->iomem = ioremap(nv_device_resource_start(device, 3),
nv_device_resource_len(device, 3));
return 0;
}
void
nouveau_bar_destroy(struct nouveau_bar *bar)
{
if (bar->iomem)
iounmap(bar->iomem);
nouveau_subdev_destroy(&bar->base);
}
void
_nouveau_bar_dtor(struct nouveau_object *object)
{
struct nouveau_bar *bar = (void *)object;
nouveau_bar_destroy(bar);
}

273
drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/vm.h>
#include "priv.h"
struct nv50_bar_priv {
struct nouveau_bar base;
spinlock_t lock;
struct nouveau_gpuobj *mem;
struct nouveau_gpuobj *pad;
struct nouveau_gpuobj *pgd;
struct nouveau_vm *bar1_vm;
struct nouveau_gpuobj *bar1;
struct nouveau_vm *bar3_vm;
struct nouveau_gpuobj *bar3;
};
static int
nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
u32 flags, struct nouveau_vma *vma)
{
struct nv50_bar_priv *priv = (void *)bar;
int ret;
ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
if (ret)
return ret;
nouveau_vm_map(vma, mem);
return 0;
}
static int
nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
u32 flags, struct nouveau_vma *vma)
{
struct nv50_bar_priv *priv = (void *)bar;
int ret;
ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
if (ret)
return ret;
nouveau_vm_map(vma, mem);
return 0;
}
static void
nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
{
nouveau_vm_unmap(vma);
nouveau_vm_put(vma);
}
static void
nv50_bar_flush(struct nouveau_bar *bar)
{
struct nv50_bar_priv *priv = (void *)bar;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
nv_wr32(priv, 0x00330c, 0x00000001);
if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))
nv_warn(priv, "flush timeout\n");
spin_unlock_irqrestore(&priv->lock, flags);
}
void
nv84_bar_flush(struct nouveau_bar *bar)
{
struct nv50_bar_priv *priv = (void *)bar;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
nv_wr32(bar, 0x070000, 0x00000001);
if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))
nv_warn(priv, "flush timeout\n");
spin_unlock_irqrestore(&priv->lock, flags);
}
static int
nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
struct nouveau_object *heap;
struct nouveau_vm *vm;
struct nv50_bar_priv *priv;
u64 start, limit;
int ret;
ret = nouveau_bar_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
NVOBJ_FLAG_HEAP, &priv->mem);
heap = nv_object(priv->mem);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), heap,
(device->chipset == 0x50) ? 0x1400 : 0x0200,
0, 0, &priv->pad);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0,
0, &priv->pgd);
if (ret)
return ret;
/* BAR3 */
start = 0x0100000000ULL;
limit = start + nv_device_resource_len(device, 3);
ret = nouveau_vm_new(device, start, limit, start, &vm);
if (ret)
return ret;
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
ret = nouveau_gpuobj_new(nv_object(priv), heap,
((limit-- - start) >> 12) * 8, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
nouveau_vm_ref(NULL, &vm, NULL);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
if (ret)
return ret;
nv_wo32(priv->bar3, 0x00, 0x7fc00000);
nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));
nv_wo32(priv->bar3, 0x08, lower_32_bits(start));
nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |
upper_32_bits(start));
nv_wo32(priv->bar3, 0x10, 0x00000000);
nv_wo32(priv->bar3, 0x14, 0x00000000);
/* BAR1 */
start = 0x0000000000ULL;
limit = start + nv_device_resource_len(device, 1);
ret = nouveau_vm_new(device, start, limit--, start, &vm);
if (ret)
return ret;
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
nouveau_vm_ref(NULL, &vm, NULL);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
if (ret)
return ret;
nv_wo32(priv->bar1, 0x00, 0x7fc00000);
nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));
nv_wo32(priv->bar1, 0x08, lower_32_bits(start));
nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |
upper_32_bits(start));
nv_wo32(priv->bar1, 0x10, 0x00000000);
nv_wo32(priv->bar1, 0x14, 0x00000000);
priv->base.alloc = nouveau_bar_alloc;
priv->base.kmap = nv50_bar_kmap;
priv->base.umap = nv50_bar_umap;
priv->base.unmap = nv50_bar_unmap;
if (device->chipset == 0x50)
priv->base.flush = nv50_bar_flush;
else
priv->base.flush = nv84_bar_flush;
spin_lock_init(&priv->lock);
return 0;
}
static void
nv50_bar_dtor(struct nouveau_object *object)
{
struct nv50_bar_priv *priv = (void *)object;
nouveau_gpuobj_ref(NULL, &priv->bar1);
nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
nouveau_gpuobj_ref(NULL, &priv->bar3);
if (priv->bar3_vm) {
nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
}
nouveau_gpuobj_ref(NULL, &priv->pgd);
nouveau_gpuobj_ref(NULL, &priv->pad);
nouveau_gpuobj_ref(NULL, &priv->mem);
nouveau_bar_destroy(&priv->base);
}
static int
nv50_bar_init(struct nouveau_object *object)
{
struct nv50_bar_priv *priv = (void *)object;
int ret, i;
ret = nouveau_bar_init(&priv->base);
if (ret)
return ret;
nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
nv_wr32(priv, 0x100c80, 0x00060001);
if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) {
nv_error(priv, "vm flush timeout\n");
return -EBUSY;
}
nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);
nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x001900 + (i * 4), 0x00000000);
return 0;
}
static int
nv50_bar_fini(struct nouveau_object *object, bool suspend)
{
struct nv50_bar_priv *priv = (void *)object;
return nouveau_bar_fini(&priv->base, suspend);
}
struct nouveau_oclass
nv50_bar_oclass = {
.handle = NV_SUBDEV(BAR, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_bar_ctor,
.dtor = nv50_bar_dtor,
.init = nv50_bar_init,
.fini = nv50_bar_fini,
},
};

221
drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/vm.h>
#include "priv.h"
struct nvc0_bar_priv_vm {
struct nouveau_gpuobj *mem;
struct nouveau_gpuobj *pgd;
struct nouveau_vm *vm;
};
struct nvc0_bar_priv {
struct nouveau_bar base;
spinlock_t lock;
struct nvc0_bar_priv_vm bar[2];
};
static int
nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
u32 flags, struct nouveau_vma *vma)
{
struct nvc0_bar_priv *priv = (void *)bar;
int ret;
ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
if (ret)
return ret;
nouveau_vm_map(vma, mem);
return 0;
}
static int
nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
u32 flags, struct nouveau_vma *vma)
{
struct nvc0_bar_priv *priv = (void *)bar;
int ret;
ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
mem->page_shift, flags, vma);
if (ret)
return ret;
nouveau_vm_map(vma, mem);
return 0;
}
static void
nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
{
nouveau_vm_unmap(vma);
nouveau_vm_put(vma);
}
static int
nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
int bar_nr)
{
struct nouveau_device *device = nv_device(&priv->base);
struct nouveau_vm *vm;
resource_size_t bar_len;
int ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
&bar_vm->mem);
if (ret)
return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
&bar_vm->pgd);
if (ret)
return ret;
bar_len = nv_device_resource_len(device, bar_nr);
ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
if (ret)
return ret;
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
/*
* Bootstrap page table lookup.
*/
if (bar_nr == 3) {
ret = nouveau_gpuobj_new(nv_object(priv), NULL,
(bar_len >> 12) * 8, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC,
&vm->pgt[0].obj[0]);
vm->pgt[0].refcount[0] = 1;
if (ret)
return ret;
}
ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
nouveau_vm_ref(NULL, &vm, NULL);
if (ret)
return ret;
nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
return 0;
}
static int
nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
struct nvc0_bar_priv *priv;
bool has_bar3 = nv_device_resource_len(device, 3) != 0;
int ret;
ret = nouveau_bar_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* BAR3 */
if (has_bar3) {
ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
if (ret)
return ret;
priv->base.alloc = nouveau_bar_alloc;
priv->base.kmap = nvc0_bar_kmap;
}
/* BAR1 */
ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
if (ret)
return ret;
priv->base.umap = nvc0_bar_umap;
priv->base.unmap = nvc0_bar_unmap;
priv->base.flush = nv84_bar_flush;
spin_lock_init(&priv->lock);
return 0;
}
static void
nvc0_bar_dtor(struct nouveau_object *object)
{
struct nvc0_bar_priv *priv = (void *)object;
nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
if (priv->bar[0].vm) {
nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
}
nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
nouveau_bar_destroy(&priv->base);
}
static int
nvc0_bar_init(struct nouveau_object *object)
{
struct nvc0_bar_priv *priv = (void *)object;
int ret;
ret = nouveau_bar_init(&priv->base);
if (ret)
return ret;
nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
if (priv->bar[0].mem)
nv_wr32(priv, 0x001714,
0xc0000000 | priv->bar[0].mem->addr >> 12);
return 0;
}
struct nouveau_oclass
nvc0_bar_oclass = {
.handle = NV_SUBDEV(BAR, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_bar_ctor,
.dtor = nvc0_bar_dtor,
.init = nvc0_bar_init,
.fini = _nouveau_bar_fini,
},
};

26
drivers/gpu/drm/nouveau/core/subdev/bar/priv.h Normal file
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#ifndef __NVKM_BAR_PRIV_H__
#define __NVKM_BAR_PRIV_H__
#include <subdev/bar.h>
#define nouveau_bar_create(p,e,o,d) \
nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_bar_init(p) \
nouveau_subdev_init(&(p)->base)
#define nouveau_bar_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void nouveau_bar_destroy(struct nouveau_bar *);
void _nouveau_bar_dtor(struct nouveau_object *);
#define _nouveau_bar_init _nouveau_subdev_init
#define _nouveau_bar_fini _nouveau_subdev_fini
int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *,
struct nouveau_mem *, struct nouveau_object **);
void nv84_bar_flush(struct nouveau_bar *);
#endif

109
drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c Normal file
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@@ -0,0 +1,109 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/ramcfg.h>
#include <subdev/bios/P0260.h>
u32
nvbios_P0260Te(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
{
struct bit_entry bit_P;
u32 data = 0x00000000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2 && bit_P.length > 0x63)
data = nv_ro32(bios, bit_P.offset + 0x60);
if (data) {
*ver = nv_ro08(bios, data + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, data + 1);
*cnt = nv_ro08(bios, data + 2);
*len = 4;
*xnr = nv_ro08(bios, data + 3);
*xsz = 4;
return data;
default:
break;
}
}
}
return 0x00000000;
}
u32
nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt, xnr, xsz;
u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, len, &xnr, &xsz);
if (data && idx < cnt)
return data + hdr + (idx * *len);
return 0x00000000;
}
u32
nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_P0260E *info)
{
u32 data = nvbios_P0260Ee(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->data = nv_ro32(bios, data);
return data;
default:
break;
}
return 0x00000000;
}
u32
nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz)
{
u8 hdr, cnt, len, xnr;
u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, &len, &xnr, xsz);
if (data && idx < xnr)
return data + hdr + (cnt * len) + (idx * *xsz);
return 0x00000000;
}
u32
nvbios_P0260Xp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_P0260X *info)
{
u32 data = nvbios_P0260Xe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->data = nv_ro32(bios, data);
return data;
default:
break;
}
return 0x00000000;
}

552
drivers/gpu/drm/nouveau/core/subdev/bios/base.c Normal file
View File

@@ -0,0 +1,552 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/object.h>
#include <core/device.h>
#include <core/subdev.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/bmp.h>
#include <subdev/bios/bit.h>
u8
nvbios_checksum(const u8 *data, int size)
{
u8 sum = 0;
while (size--)
sum += *data++;
return sum;
}
u16
nvbios_findstr(const u8 *data, int size, const char *str, int len)
{
int i, j;
for (i = 0; i <= (size - len); i++) {
for (j = 0; j < len; j++)
if ((char)data[i + j] != str[j])
break;
if (j == len)
return i;
}
return 0;
}
#if defined(__powerpc__)
static void
nouveau_bios_shadow_of(struct nouveau_bios *bios)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct device_node *dn;
const u32 *data;
int size;
dn = pci_device_to_OF_node(pdev);
if (!dn) {
nv_info(bios, "Unable to get the OF node\n");
return;
}
data = of_get_property(dn, "NVDA,BMP", &size);
if (data && size) {
bios->size = size;
bios->data = kmalloc(bios->size, GFP_KERNEL);
if (bios->data)
memcpy(bios->data, data, size);
}
}
#endif
static void
nouveau_bios_shadow_pramin(struct nouveau_bios *bios)
{
struct nouveau_device *device = nv_device(bios);
u64 addr = 0;
u32 bar0 = 0;
int i;
if (device->card_type >= NV_50) {
if (device->card_type >= NV_C0 && device->card_type < GM100) {
if (nv_rd32(bios, 0x022500) & 0x00000001)
return;
} else
if (device->card_type >= GM100) {
if (nv_rd32(bios, 0x021c04) & 0x00000001)
return;
}
addr = nv_rd32(bios, 0x619f04);
if (!(addr & 0x00000008)) {
nv_debug(bios, "... not enabled\n");
return;
}
if ( (addr & 0x00000003) != 1) {
nv_debug(bios, "... not in vram\n");
return;
}
addr = (addr & 0xffffff00) << 8;
if (!addr) {
addr = (u64)nv_rd32(bios, 0x001700) << 16;
addr += 0xf0000;
}
bar0 = nv_mask(bios, 0x001700, 0xffffffff, addr >> 16);
}
/* bail if no rom signature */
if (nv_rd08(bios, 0x700000) != 0x55 ||
nv_rd08(bios, 0x700001) != 0xaa)
goto out;
bios->size = nv_rd08(bios, 0x700002) * 512;
if (!bios->size)
goto out;
bios->data = kmalloc(bios->size, GFP_KERNEL);
if (bios->data) {
for (i = 0; i < bios->size; i++)
nv_wo08(bios, i, nv_rd08(bios, 0x700000 + i));
}
out:
if (device->card_type >= NV_50)
nv_wr32(bios, 0x001700, bar0);
}
static void
nouveau_bios_shadow_prom(struct nouveau_bios *bios)
{
struct nouveau_device *device = nv_device(bios);
u32 pcireg, access;
u16 pcir;
int i;
/* there is no prom on nv4x IGP's */
if (device->card_type == NV_40 && device->chipset >= 0x4c)
return;
/* enable access to rom */
if (device->card_type >= NV_50)
pcireg = 0x088050;
else
pcireg = 0x001850;
access = nv_mask(bios, pcireg, 0x00000001, 0x00000000);
/* WARNING: PROM accesses should always be 32-bits aligned. Other
* accesses work on most chipset but do not on Kepler chipsets
*/
/* bail if no rom signature, with a workaround for a PROM reading
* issue on some chipsets. the first read after a period of
* inactivity returns the wrong result, so retry the first header
* byte a few times before giving up as a workaround
*/
i = 16;
do {
u32 data = le32_to_cpu(nv_rd32(bios, 0x300000)) & 0xffff;
if (data == 0xaa55)
break;
} while (i--);
if (!i)
goto out;
/* read entire bios image to system memory */
bios->size = (le32_to_cpu(nv_rd32(bios, 0x300000)) >> 16) & 0xff;
bios->size = bios->size * 512;
if (!bios->size)
goto out;
bios->data = kmalloc(bios->size, GFP_KERNEL);
if (!bios->data)
goto out;
for (i = 0; i < bios->size; i += 4)
((u32 *)bios->data)[i/4] = nv_rd32(bios, 0x300000 + i);
/* check the PCI record header */
pcir = nv_ro16(bios, 0x0018);
if (bios->data[pcir + 0] != 'P' ||
bios->data[pcir + 1] != 'C' ||
bios->data[pcir + 2] != 'I' ||
bios->data[pcir + 3] != 'R') {
bios->size = 0;
kfree(bios->data);
}
out:
/* disable access to rom */
nv_wr32(bios, pcireg, access);
}
#if defined(CONFIG_ACPI) && defined(CONFIG_X86)
int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
#else
static inline bool
nouveau_acpi_rom_supported(struct pci_dev *pdev) {
return false;
}
static inline int
nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) {
return -EINVAL;
}
#endif
static void
nouveau_bios_shadow_acpi(struct nouveau_bios *bios)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
int ret, cnt, i;
if (!nouveau_acpi_rom_supported(pdev)) {
bios->data = NULL;
return;
}
bios->size = 0;
bios->data = kmalloc(4096, GFP_KERNEL);
if (bios->data) {
if (nouveau_acpi_get_bios_chunk(bios->data, 0, 4096) == 4096)
bios->size = bios->data[2] * 512;
kfree(bios->data);
}
if (!bios->size)
return;
bios->data = kmalloc(bios->size, GFP_KERNEL);
if (bios->data) {
/* disobey the acpi spec - much faster on at least w530 ... */
ret = nouveau_acpi_get_bios_chunk(bios->data, 0, bios->size);
if (ret != bios->size ||
nvbios_checksum(bios->data, bios->size)) {
/* ... that didn't work, ok, i'll be good now */
for (i = 0; i < bios->size; i += cnt) {
cnt = min((bios->size - i), (u32)4096);
ret = nouveau_acpi_get_bios_chunk(bios->data, i, cnt);
if (ret != cnt)
break;
}
}
}
}
static void
nouveau_bios_shadow_pci(struct nouveau_bios *bios)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
size_t size;
if (!pci_enable_rom(pdev)) {
void __iomem *rom = pci_map_rom(pdev, &size);
if (rom && size) {
bios->data = kmalloc(size, GFP_KERNEL);
if (bios->data) {
memcpy_fromio(bios->data, rom, size);
bios->size = size;
}
}
if (rom)
pci_unmap_rom(pdev, rom);
pci_disable_rom(pdev);
}
}
static void
nouveau_bios_shadow_platform(struct nouveau_bios *bios)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
size_t size;
void __iomem *rom = pci_platform_rom(pdev, &size);
if (rom && size) {
bios->data = kmalloc(size, GFP_KERNEL);
if (bios->data) {
memcpy_fromio(bios->data, rom, size);
bios->size = size;
}
}
}
static int
nouveau_bios_score(struct nouveau_bios *bios, const bool writeable)
{
if (bios->size < 3 || !bios->data || bios->data[0] != 0x55 ||
bios->data[1] != 0xAA) {
nv_info(bios, "... signature not found\n");
return 0;
}
if (nvbios_checksum(bios->data,
min_t(u32, bios->data[2] * 512, bios->size))) {
nv_info(bios, "... checksum invalid\n");
/* if a ro image is somewhat bad, it's probably all rubbish */
return writeable ? 2 : 1;
}
nv_info(bios, "... appears to be valid\n");
return 3;
}
struct methods {
const char desc[16];
void (*shadow)(struct nouveau_bios *);
const bool rw;
int score;
u32 size;
u8 *data;
};
static int
nouveau_bios_shadow(struct nouveau_bios *bios)
{
struct methods shadow_methods[] = {
#if defined(__powerpc__)
{ "OpenFirmware", nouveau_bios_shadow_of, true, 0, 0, NULL },
#endif
{ "PRAMIN", nouveau_bios_shadow_pramin, true, 0, 0, NULL },
{ "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL },
{ "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL },
{ "PCIROM", nouveau_bios_shadow_pci, true, 0, 0, NULL },
{ "PLATFORM", nouveau_bios_shadow_platform, true, 0, 0, NULL },
{}
};
struct methods *mthd, *best;
const struct firmware *fw;
const char *optarg;
int optlen, ret;
char *source;
optarg = nouveau_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen);
source = optarg ? kstrndup(optarg, optlen, GFP_KERNEL) : NULL;
if (source) {
/* try to match one of the built-in methods */
mthd = shadow_methods;
do {
if (strcasecmp(source, mthd->desc))
continue;
nv_info(bios, "source: %s\n", mthd->desc);
mthd->shadow(bios);
mthd->score = nouveau_bios_score(bios, mthd->rw);
if (mthd->score) {
kfree(source);
return 0;
}
} while ((++mthd)->shadow);
/* attempt to load firmware image */
ret = request_firmware(&fw, source, &nv_device(bios)->pdev->dev);
if (ret == 0) {
bios->size = fw->size;
bios->data = kmemdup(fw->data, fw->size, GFP_KERNEL);
release_firmware(fw);
nv_info(bios, "image: %s\n", source);
if (nouveau_bios_score(bios, 1)) {
kfree(source);
return 0;
}
kfree(bios->data);
bios->data = NULL;
}
nv_error(bios, "source \'%s\' invalid\n", source);
kfree(source);
}
mthd = shadow_methods;
do {
nv_info(bios, "checking %s for image...\n", mthd->desc);
mthd->shadow(bios);
mthd->score = nouveau_bios_score(bios, mthd->rw);
mthd->size = bios->size;
mthd->data = bios->data;
bios->data = NULL;
} while (mthd->score != 3 && (++mthd)->shadow);
mthd = shadow_methods;
best = mthd;
do {
if (mthd->score > best->score) {
kfree(best->data);
best = mthd;
}
} while ((++mthd)->shadow);
if (best->score) {
nv_info(bios, "using image from %s\n", best->desc);
bios->size = best->size;
bios->data = best->data;
return 0;
}
nv_error(bios, "unable to locate usable image\n");
return -EINVAL;
}
static u8
nouveau_bios_rd08(struct nouveau_object *object, u64 addr)
{
struct nouveau_bios *bios = (void *)object;
return bios->data[addr];
}
static u16
nouveau_bios_rd16(struct nouveau_object *object, u64 addr)
{
struct nouveau_bios *bios = (void *)object;
return get_unaligned_le16(&bios->data[addr]);
}
static u32
nouveau_bios_rd32(struct nouveau_object *object, u64 addr)
{
struct nouveau_bios *bios = (void *)object;
return get_unaligned_le32(&bios->data[addr]);
}
static void
nouveau_bios_wr08(struct nouveau_object *object, u64 addr, u8 data)
{
struct nouveau_bios *bios = (void *)object;
bios->data[addr] = data;
}
static void
nouveau_bios_wr16(struct nouveau_object *object, u64 addr, u16 data)
{
struct nouveau_bios *bios = (void *)object;
put_unaligned_le16(data, &bios->data[addr]);
}
static void
nouveau_bios_wr32(struct nouveau_object *object, u64 addr, u32 data)
{
struct nouveau_bios *bios = (void *)object;
put_unaligned_le32(data, &bios->data[addr]);
}
static int
nouveau_bios_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_bios *bios;
struct bit_entry bit_i;
int ret;
ret = nouveau_subdev_create(parent, engine, oclass, 0,
"VBIOS", "bios", &bios);
*pobject = nv_object(bios);
if (ret)
return ret;
ret = nouveau_bios_shadow(bios);
if (ret)
return ret;
/* detect type of vbios we're dealing with */
bios->bmp_offset = nvbios_findstr(bios->data, bios->size,
"\xff\x7f""NV\0", 5);
if (bios->bmp_offset) {
nv_info(bios, "BMP version %x.%x\n",
bmp_version(bios) >> 8,
bmp_version(bios) & 0xff);
}
bios->bit_offset = nvbios_findstr(bios->data, bios->size,
"\xff\xb8""BIT", 5);
if (bios->bit_offset)
nv_info(bios, "BIT signature found\n");
/* determine the vbios version number */
if (!bit_entry(bios, 'i', &bit_i) && bit_i.length >= 4) {
bios->version.major = nv_ro08(bios, bit_i.offset + 3);
bios->version.chip = nv_ro08(bios, bit_i.offset + 2);
bios->version.minor = nv_ro08(bios, bit_i.offset + 1);
bios->version.micro = nv_ro08(bios, bit_i.offset + 0);
bios->version.patch = nv_ro08(bios, bit_i.offset + 4);
} else
if (bmp_version(bios)) {
bios->version.major = nv_ro08(bios, bios->bmp_offset + 13);
bios->version.chip = nv_ro08(bios, bios->bmp_offset + 12);
bios->version.minor = nv_ro08(bios, bios->bmp_offset + 11);
bios->version.micro = nv_ro08(bios, bios->bmp_offset + 10);
}
nv_info(bios, "version %02x.%02x.%02x.%02x.%02x\n",
bios->version.major, bios->version.chip,
bios->version.minor, bios->version.micro, bios->version.patch);
return 0;
}
static void
nouveau_bios_dtor(struct nouveau_object *object)
{
struct nouveau_bios *bios = (void *)object;
kfree(bios->data);
nouveau_subdev_destroy(&bios->base);
}
static int
nouveau_bios_init(struct nouveau_object *object)
{
struct nouveau_bios *bios = (void *)object;
return nouveau_subdev_init(&bios->base);
}
static int
nouveau_bios_fini(struct nouveau_object *object, bool suspend)
{
struct nouveau_bios *bios = (void *)object;
return nouveau_subdev_fini(&bios->base, suspend);
}
struct nouveau_oclass
nouveau_bios_oclass = {
.handle = NV_SUBDEV(VBIOS, 0x00),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nouveau_bios_ctor,
.dtor = nouveau_bios_dtor,
.init = nouveau_bios_init,
.fini = nouveau_bios_fini,
.rd08 = nouveau_bios_rd08,
.rd16 = nouveau_bios_rd16,
.rd32 = nouveau_bios_rd32,
.wr08 = nouveau_bios_wr08,
.wr16 = nouveau_bios_wr16,
.wr32 = nouveau_bios_wr32,
},
};

52
drivers/gpu/drm/nouveau/core/subdev/bios/bit.c Normal file
View File

@@ -0,0 +1,52 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "core/object.h"
#include "subdev/bios.h"
#include "subdev/bios/bit.h"
int
bit_entry(struct nouveau_bios *bios, u8 id, struct bit_entry *bit)
{
if (likely(bios->bit_offset)) {
u8 entries = nv_ro08(bios, bios->bit_offset + 10);
u32 entry = bios->bit_offset + 12;
while (entries--) {
if (nv_ro08(bios, entry + 0) == id) {
bit->id = nv_ro08(bios, entry + 0);
bit->version = nv_ro08(bios, entry + 1);
bit->length = nv_ro16(bios, entry + 2);
bit->offset = nv_ro16(bios, entry + 4);
return 0;
}
entry += nv_ro08(bios, bios->bit_offset + 9);
}
return -ENOENT;
}
return -EINVAL;
}

127
drivers/gpu/drm/nouveau/core/subdev/bios/boost.c Normal file
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@@ -0,0 +1,127 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/boost.h>
u16
nvbios_boostTe(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 boost = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
boost = nv_ro16(bios, bit_P.offset + 0x30);
if (boost) {
*ver = nv_ro08(bios, boost + 0);
switch (*ver) {
case 0x11:
*hdr = nv_ro08(bios, boost + 1);
*cnt = nv_ro08(bios, boost + 5);
*len = nv_ro08(bios, boost + 2);
*snr = nv_ro08(bios, boost + 4);
*ssz = nv_ro08(bios, boost + 3);
return boost;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_boostEe(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz);
if (data && idx < *cnt) {
data = data + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return data;
}
return 0x0000;
}
u16
nvbios_boostEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
}
return data;
}
u16
nvbios_boostEm(struct nouveau_bios *bios, u8 pstate,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u32 data, idx = 0;
while ((data = nvbios_boostEp(bios, idx++, ver, hdr, cnt, len, info))) {
if (info->pstate == pstate)
break;
}
return data;
}
u16
nvbios_boostSe(struct nouveau_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
if (data && idx < cnt) {
data = data + *hdr + (idx * len);
*hdr = len;
return data;
}
return 0x0000;
}
u16
nvbios_boostSp(struct nouveau_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_boostS *info)
{
data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->domain = nv_ro08(bios, data + 0x00);
info->percent = nv_ro08(bios, data + 0x01);
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
}
return data;
}

100
drivers/gpu/drm/nouveau/core/subdev/bios/conn.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/conn.h>
u32
nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u32 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb && *ver >= 0x30 && *hdr >= 0x16) {
u32 data = nv_ro16(bios, dcb + 0x14);
if (data) {
*ver = nv_ro08(bios, data + 0);
*hdr = nv_ro08(bios, data + 1);
*cnt = nv_ro08(bios, data + 2);
*len = nv_ro08(bios, data + 3);
return data;
}
}
return 0x00000000;
}
u32
nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_connT *info)
{
u32 data = nvbios_connTe(bios, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x30:
case 0x40:
return data;
default:
break;
}
return 0x00000000;
}
u32
nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u32 data = nvbios_connTe(bios, ver, &hdr, &cnt, len);
if (data && idx < cnt)
return data + hdr + (idx * *len);
return 0x00000000;
}
u32
nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
struct nvbios_connE *info)
{
u32 data = nvbios_connEe(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x30:
case 0x40:
info->type = nv_ro08(bios, data + 0x00);
info->location = nv_ro08(bios, data + 0x01) & 0x0f;
info->hpd = (nv_ro08(bios, data + 0x01) & 0x30) >> 4;
info->dp = (nv_ro08(bios, data + 0x01) & 0xc0) >> 6;
if (*len < 4)
return data;
info->hpd |= (nv_ro08(bios, data + 0x02) & 0x03) << 2;
info->dp |= nv_ro08(bios, data + 0x02) & 0x0c;
info->di = (nv_ro08(bios, data + 0x02) & 0xf0) >> 4;
info->hpd |= (nv_ro08(bios, data + 0x03) & 0x07) << 4;
info->sr = (nv_ro08(bios, data + 0x03) & 0x08) >> 3;
info->lcdid = (nv_ro08(bios, data + 0x03) & 0x70) >> 4;
return data;
default:
break;
}
return 0x00000000;
}

123
drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/cstep.h>
u16
nvbios_cstepTe(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
{
struct bit_entry bit_P;
u16 cstep = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
cstep = nv_ro16(bios, bit_P.offset + 0x34);
if (cstep) {
*ver = nv_ro08(bios, cstep + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, cstep + 1);
*cnt = nv_ro08(bios, cstep + 3);
*len = nv_ro08(bios, cstep + 2);
*xnr = nv_ro08(bios, cstep + 5);
*xsz = nv_ro08(bios, cstep + 4);
return cstep;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
if (data && idx < cnt) {
data = data + *hdr + (idx * len);
*hdr = len;
return data;
}
return 0x0000;
}
u16
nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u16 data = nvbios_cstepEe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->index = nv_ro08(bios, data + 0x03);
}
return data;
}
u16
nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u32 data, idx = 0;
while ((data = nvbios_cstepEp(bios, idx++, ver, hdr, info))) {
if (info->pstate == pstate)
break;
}
return data;
}
u16
nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
if (data && idx < xnr) {
data = data + *hdr + (cnt * len) + (idx * xsz);
*hdr = xsz;
return data;
}
return 0x0000;
}
u16
nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *info)
{
u16 data = nvbios_cstepXe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->freq = nv_ro16(bios, data + 0x00) * 1000;
info->unkn[0] = nv_ro08(bios, data + 0x02);
info->unkn[1] = nv_ro08(bios, data + 0x03);
info->voltage = nv_ro08(bios, data + 0x04);
}
return data;
}

231
drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "core/device.h"
#include "subdev/bios.h"
#include "subdev/bios/dcb.h"
u16
dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct nouveau_device *device = nv_device(bios);
u16 dcb = 0x0000;
if (device->card_type > NV_04)
dcb = nv_ro16(bios, 0x36);
if (!dcb) {
nv_warn(bios, "DCB table not found\n");
return dcb;
}
*ver = nv_ro08(bios, dcb);
if (*ver >= 0x41) {
nv_warn(bios, "DCB version 0x%02x unknown\n", *ver);
return 0x0000;
} else
if (*ver >= 0x30) {
if (nv_ro32(bios, dcb + 6) == 0x4edcbdcb) {
*hdr = nv_ro08(bios, dcb + 1);
*cnt = nv_ro08(bios, dcb + 2);
*len = nv_ro08(bios, dcb + 3);
return dcb;
}
} else
if (*ver >= 0x20) {
if (nv_ro32(bios, dcb + 4) == 0x4edcbdcb) {
u16 i2c = nv_ro16(bios, dcb + 2);
*hdr = 8;
*cnt = (i2c - dcb) / 8;
*len = 8;
return dcb;
}
} else
if (*ver >= 0x15) {
if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
u16 i2c = nv_ro16(bios, dcb + 2);
*hdr = 4;
*cnt = (i2c - dcb) / 10;
*len = 10;
return dcb;
}
} else {
/*
* v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
* always has the same single (crt) entry, even when tv-out
* present, so the conclusion is this version cannot really
* be used.
*
* v1.2 tables (some NV6/10, and NV15+) normally have the
* same 5 entries, which are not specific to the card and so
* no use.
*
* v1.2 does have an I2C table that read_dcb_i2c_table can
* handle, but cards exist (nv11 in #14821) with a bad i2c
* table pointer, so use the indices parsed in
* parse_bmp_structure.
*
* v1.1 (NV5+, maybe some NV4) is entirely unhelpful
*/
nv_warn(bios, "DCB contains no useful data\n");
return 0x0000;
}
nv_warn(bios, "DCB header validation failed\n");
return 0x0000;
}
u16
dcb_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 dcb = dcb_table(bios, ver, &hdr, &cnt, len);
if (dcb && idx < cnt)
return dcb + hdr + (idx * *len);
return 0x0000;
}
static inline u16
dcb_outp_hasht(struct dcb_output *outp)
{
return (outp->extdev << 8) | (outp->location << 4) | outp->type;
}
static inline u16
dcb_outp_hashm(struct dcb_output *outp)
{
return (outp->heads << 8) | (outp->link << 6) | outp->or;
}
u16
dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len,
struct dcb_output *outp)
{
u16 dcb = dcb_outp(bios, idx, ver, len);
if (dcb) {
if (*ver >= 0x20) {
u32 conn = nv_ro32(bios, dcb + 0x00);
outp->or = (conn & 0x0f000000) >> 24;
outp->location = (conn & 0x00300000) >> 20;
outp->bus = (conn & 0x000f0000) >> 16;
outp->connector = (conn & 0x0000f000) >> 12;
outp->heads = (conn & 0x00000f00) >> 8;
outp->i2c_index = (conn & 0x000000f0) >> 4;
outp->type = (conn & 0x0000000f);
outp->link = 0;
} else {
dcb = 0x0000;
}
if (*ver >= 0x40) {
u32 conf = nv_ro32(bios, dcb + 0x04);
switch (outp->type) {
case DCB_OUTPUT_DP:
switch (conf & 0x00e00000) {
case 0x00000000:
outp->dpconf.link_bw = 0x06;
break;
case 0x00200000:
outp->dpconf.link_bw = 0x0a;
break;
case 0x00400000:
default:
outp->dpconf.link_bw = 0x14;
break;
}
switch (conf & 0x0f000000) {
case 0x0f000000:
outp->dpconf.link_nr = 4;
break;
case 0x03000000:
outp->dpconf.link_nr = 2;
break;
case 0x01000000:
default:
outp->dpconf.link_nr = 1;
break;
}
/* fall-through... */
case DCB_OUTPUT_TMDS:
case DCB_OUTPUT_LVDS:
outp->link = (conf & 0x00000030) >> 4;
outp->sorconf.link = outp->link; /*XXX*/
outp->extdev = 0x00;
if (outp->location != 0)
outp->extdev = (conf & 0x0000ff00) >> 8;
break;
default:
break;
}
}
outp->hasht = dcb_outp_hasht(outp);
outp->hashm = dcb_outp_hashm(outp);
}
return dcb;
}
u16
dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
u8 *ver, u8 *len, struct dcb_output *outp)
{
u16 dcb, idx = 0;
while ((dcb = dcb_outp_parse(bios, idx++, ver, len, outp))) {
if ((dcb_outp_hasht(outp) & 0x00ff) == (type & 0x00ff)) {
if ((dcb_outp_hashm(outp) & mask) == mask)
break;
}
}
return dcb;
}
int
dcb_outp_foreach(struct nouveau_bios *bios, void *data,
int (*exec)(struct nouveau_bios *, void *, int, u16))
{
int ret, idx = -1;
u8 ver, len;
u16 outp;
while ((outp = dcb_outp(bios, ++idx, &ver, &len))) {
if (nv_ro32(bios, outp) == 0x00000000)
break; /* seen on an NV11 with DCB v1.5 */
if (nv_ro32(bios, outp) == 0xffffffff)
break; /* seen on an NV17 with DCB v2.0 */
if (nv_ro08(bios, outp) == DCB_OUTPUT_UNUSED)
continue;
if (nv_ro08(bios, outp) == DCB_OUTPUT_EOL)
break;
ret = exec(bios, data, idx, outp);
if (ret)
return ret;
}
return 0;
}

178
drivers/gpu/drm/nouveau/core/subdev/bios/disp.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/disp.h>
u16
nvbios_disp_table(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub)
{
struct bit_entry U;
if (!bit_entry(bios, 'U', &U)) {
if (U.version == 1) {
u16 data = nv_ro16(bios, U.offset);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
switch (*ver) {
case 0x20:
case 0x21:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
*sub = nv_ro08(bios, data + 0x04);
return data;
default:
break;
}
}
}
}
return 0x0000;
}
u16
nvbios_disp_entry(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *len, u8 *sub)
{
u8 hdr, cnt;
u16 data = nvbios_disp_table(bios, ver, &hdr, &cnt, len, sub);
if (data && idx < cnt)
return data + hdr + (idx * *len);
*ver = 0x00;
return 0x0000;
}
u16
nvbios_disp_parse(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *len, u8 *sub,
struct nvbios_disp *info)
{
u16 data = nvbios_disp_entry(bios, idx, ver, len, sub);
if (data && *len >= 2) {
info->data = nv_ro16(bios, data + 0);
return data;
}
return 0x0000;
}
u16
nvbios_outp_entry(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct nvbios_disp info;
u16 data = nvbios_disp_parse(bios, idx, ver, len, hdr, &info);
if (data) {
*cnt = nv_ro08(bios, info.data + 0x05);
*len = 0x06;
data = info.data;
}
return data;
}
u16
nvbios_outp_parse(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_outp *info)
{
u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len);
if (data && *hdr >= 0x0a) {
info->type = nv_ro16(bios, data + 0x00);
info->mask = nv_ro32(bios, data + 0x02);
if (*ver <= 0x20) /* match any link */
info->mask |= 0x00c0;
info->script[0] = nv_ro16(bios, data + 0x06);
info->script[1] = nv_ro16(bios, data + 0x08);
info->script[2] = 0x0000;
if (*hdr >= 0x0c)
info->script[2] = nv_ro16(bios, data + 0x0a);
return data;
}
return 0x0000;
}
u16
nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_outp *info)
{
u16 data, idx = 0;
while ((data = nvbios_outp_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
if (data && info->type == type) {
if ((info->mask & mask) == mask)
break;
}
}
return data;
}
u16
nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
if (idx < *cnt)
return outp + *hdr + (idx * *len);
return 0x0000;
}
u16
nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ocfg *info)
{
u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len);
if (data) {
info->match = nv_ro16(bios, data + 0x00);
info->clkcmp[0] = nv_ro16(bios, data + 0x02);
info->clkcmp[1] = nv_ro16(bios, data + 0x04);
}
return data;
}
u16
nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ocfg *info)
{
u16 data, idx = 0;
while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) {
if (info->match == type)
break;
}
return data;
}
u16
nvbios_oclk_match(struct nouveau_bios *bios, u16 cmp, u32 khz)
{
while (cmp) {
if (khz / 10 >= nv_ro16(bios, cmp + 0x00))
return nv_ro16(bios, cmp + 0x02);
cmp += 0x04;
}
return 0x0000;
}

209
drivers/gpu/drm/nouveau/core/subdev/bios/dp.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "subdev/bios.h"
#include "subdev/bios/bit.h"
#include "subdev/bios/dp.h"
static u16
nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry d;
if (!bit_entry(bios, 'd', &d)) {
if (d.version == 1 && d.length >= 2) {
u16 data = nv_ro16(bios, d.offset);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
switch (*ver) {
case 0x21:
case 0x30:
case 0x40:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
return data;
default:
break;
}
}
}
}
return 0x0000;
}
static u16
nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
if (data && idx < *cnt) {
u16 outp = nv_ro16(bios, data + *hdr + idx * *len);
switch (*ver * !!outp) {
case 0x21:
case 0x30:
*hdr = nv_ro08(bios, data + 0x04);
*len = nv_ro08(bios, data + 0x05);
*cnt = nv_ro08(bios, outp + 0x04);
break;
case 0x40:
*hdr = nv_ro08(bios, data + 0x04);
*cnt = 0;
*len = 0;
break;
default:
break;
}
return outp;
}
*ver = 0x00;
return 0x0000;
}
u16
nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *info)
{
u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data && *ver) {
info->type = nv_ro16(bios, data + 0x00);
info->mask = nv_ro16(bios, data + 0x02);
switch (*ver) {
case 0x21:
case 0x30:
info->flags = nv_ro08(bios, data + 0x05);
info->script[0] = nv_ro16(bios, data + 0x06);
info->script[1] = nv_ro16(bios, data + 0x08);
info->lnkcmp = nv_ro16(bios, data + 0x0a);
if (*len >= 0x0f) {
info->script[2] = nv_ro16(bios, data + 0x0c);
info->script[3] = nv_ro16(bios, data + 0x0e);
}
if (*len >= 0x11)
info->script[4] = nv_ro16(bios, data + 0x10);
break;
case 0x40:
info->flags = nv_ro08(bios, data + 0x04);
info->script[0] = nv_ro16(bios, data + 0x05);
info->script[1] = nv_ro16(bios, data + 0x07);
info->lnkcmp = nv_ro16(bios, data + 0x09);
info->script[2] = nv_ro16(bios, data + 0x0b);
info->script[3] = nv_ro16(bios, data + 0x0d);
info->script[4] = nv_ro16(bios, data + 0x0f);
break;
default:
data = 0x0000;
break;
}
}
return data;
}
u16
nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpout *info)
{
u16 data, idx = 0;
while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
if (data && info->type == type) {
if ((info->mask & mask) == mask)
break;
}
}
return data;
}
static u16
nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
if (*ver >= 0x40) {
outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
*hdr = *hdr + (*len * * cnt);
*len = nv_ro08(bios, outp + 0x06);
*cnt = nv_ro08(bios, outp + 0x07);
}
if (idx < *cnt)
return outp + *hdr + (idx * *len);
return 0x0000;
}
u16
nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpcfg *info)
{
u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
switch (*ver) {
case 0x21:
info->dc = nv_ro08(bios, data + 0x02);
info->pe = nv_ro08(bios, data + 0x03);
info->tx_pu = nv_ro08(bios, data + 0x04);
break;
case 0x30:
case 0x40:
info->pc = nv_ro08(bios, data + 0x00);
info->dc = nv_ro08(bios, data + 0x01);
info->pe = nv_ro08(bios, data + 0x02);
info->tx_pu = nv_ro08(bios, data + 0x03);
break;
default:
data = 0x0000;
break;
}
}
return data;
}
u16
nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_dpcfg *info)
{
u8 idx = 0xff;
u16 data;
if (*ver >= 0x30) {
const u8 vsoff[] = { 0, 4, 7, 9 };
idx = (pc * 10) + vsoff[vs] + pe;
} else {
while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
ver, hdr, cnt, len))) {
if (nv_ro08(bios, data + 0x00) == vs &&
nv_ro08(bios, data + 0x01) == pe)
break;
}
}
return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info);
}

100
drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/extdev.h>
static u16
extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
{
u8 dcb_ver, dcb_hdr, dcb_cnt, dcb_len;
u16 dcb, extdev = 0;
dcb = dcb_table(bios, &dcb_ver, &dcb_hdr, &dcb_cnt, &dcb_len);
if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40))
return 0x0000;
extdev = nv_ro16(bios, dcb + 18);
if (!extdev)
return 0x0000;
*ver = nv_ro08(bios, extdev + 0);
*hdr = nv_ro08(bios, extdev + 1);
*cnt = nv_ro08(bios, extdev + 2);
*len = nv_ro08(bios, extdev + 3);
return extdev + *hdr;
}
static u16
nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 extdev = extdev_table(bios, ver, &hdr, len, &cnt);
if (extdev && idx < cnt)
return extdev + idx * *len;
return 0x0000;
}
static void
extdev_parse_entry(struct nouveau_bios *bios, u16 offset,
struct nvbios_extdev_func *entry)
{
entry->type = nv_ro08(bios, offset + 0);
entry->addr = nv_ro08(bios, offset + 1);
entry->bus = (nv_ro08(bios, offset + 2) >> 4) & 1;
}
int
nvbios_extdev_parse(struct nouveau_bios *bios, int idx,
struct nvbios_extdev_func *func)
{
u8 ver, len;
u16 entry;
if (!(entry = nvbios_extdev_entry(bios, idx, &ver, &len)))
return -EINVAL;
extdev_parse_entry(bios, entry, func);
return 0;
}
int
nvbios_extdev_find(struct nouveau_bios *bios, enum nvbios_extdev_type type,
struct nvbios_extdev_func *func)
{
u8 ver, len, i;
u16 entry;
i = 0;
while (!(entry = nvbios_extdev_entry(bios, i++, &ver, &len))) {
extdev_parse_entry(bios, entry, func);
if (func->type == type)
return 0;
}
return -EINVAL;
}

150
drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/gpio.h>
#include <subdev/bios/xpio.h>
u16
dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = 0x0000;
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb) {
if (*ver >= 0x30 && *hdr >= 0x0c)
data = nv_ro16(bios, dcb + 0x0a);
else
if (*ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13)
data = nv_ro16(bios, dcb - 0x0f);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
if (*ver < 0x30) {
*hdr = 3;
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x01);
} else
if (*ver <= 0x41) {
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
} else {
data = 0x0000;
}
}
}
return data;
}
u16
dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len)
{
u8 hdr, cnt, xver; /* use gpio version for xpio entry parsing */
u16 gpio;
if (!idx--)
gpio = dcb_gpio_table(bios, ver, &hdr, &cnt, len);
else
gpio = dcb_xpio_table(bios, idx, &xver, &hdr, &cnt, len);
if (gpio && ent < cnt)
return gpio + hdr + (ent * *len);
return 0x0000;
}
u16
dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len,
struct dcb_gpio_func *gpio)
{
u16 data = dcb_gpio_entry(bios, idx, ent, ver, len);
if (data) {
if (*ver < 0x40) {
u16 info = nv_ro16(bios, data);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x001f) >> 0,
.func = (info & 0x07e0) >> 5,
.log[0] = (info & 0x1800) >> 11,
.log[1] = (info & 0x6000) >> 13,
.param = !!(info & 0x8000),
};
} else
if (*ver < 0x41) {
u32 info = nv_ro32(bios, data);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x0000001f) >> 0,
.func = (info & 0x0000ff00) >> 8,
.log[0] = (info & 0x18000000) >> 27,
.log[1] = (info & 0x60000000) >> 29,
.param = !!(info & 0x80000000),
};
} else {
u32 info = nv_ro32(bios, data + 0);
u8 info1 = nv_ro32(bios, data + 4);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x0000003f) >> 0,
.func = (info & 0x0000ff00) >> 8,
.log[0] = (info1 & 0x30) >> 4,
.log[1] = (info1 & 0xc0) >> 6,
.param = !!(info & 0x80000000),
};
}
}
return data;
}
u16
dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line,
u8 *ver, u8 *len, struct dcb_gpio_func *gpio)
{
u8 hdr, cnt, i = 0;
u16 data;
while ((data = dcb_gpio_parse(bios, idx, i++, ver, len, gpio))) {
if ((line == 0xff || line == gpio->line) &&
(func == 0xff || func == gpio->func))
return data;
}
/* DCB 2.2, fixed TVDAC GPIO data */
if ((data = dcb_table(bios, ver, &hdr, &cnt, len))) {
if (*ver >= 0x22 && *ver < 0x30 && func == DCB_GPIO_TVDAC0) {
u8 conf = nv_ro08(bios, data - 5);
u8 addr = nv_ro08(bios, data - 4);
if (conf & 0x01) {
*gpio = (struct dcb_gpio_func) {
.func = DCB_GPIO_TVDAC0,
.line = addr >> 4,
.log[0] = !!(conf & 0x02),
.log[1] = !(conf & 0x02),
};
*ver = 0x00;
return data;
}
}
}
return 0x0000;
}

134
drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "subdev/bios.h"
#include "subdev/bios/dcb.h"
#include "subdev/bios/i2c.h"
u16
dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 i2c = 0x0000;
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb) {
if (*ver >= 0x15)
i2c = nv_ro16(bios, dcb + 2);
if (*ver >= 0x30)
i2c = nv_ro16(bios, dcb + 4);
}
if (i2c && *ver >= 0x30) {
*ver = nv_ro08(bios, i2c + 0);
*hdr = nv_ro08(bios, i2c + 1);
*cnt = nv_ro08(bios, i2c + 2);
*len = nv_ro08(bios, i2c + 3);
} else {
*ver = *ver; /* use DCB version */
*hdr = 0;
*cnt = 16;
*len = 4;
}
return i2c;
}
u16
dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 i2c = dcb_i2c_table(bios, ver, &hdr, &cnt, len);
if (i2c && idx < cnt)
return i2c + hdr + (idx * *len);
return 0x0000;
}
int
dcb_i2c_parse(struct nouveau_bios *bios, u8 idx, struct dcb_i2c_entry *info)
{
u8 ver, len;
u16 ent = dcb_i2c_entry(bios, idx, &ver, &len);
if (ent) {
info->type = nv_ro08(bios, ent + 3);
info->share = DCB_I2C_UNUSED;
if (ver < 0x30) {
info->type &= 0x07;
if (info->type == 0x07)
info->type = DCB_I2C_UNUSED;
}
switch (info->type) {
case DCB_I2C_NV04_BIT:
info->drive = nv_ro08(bios, ent + 0);
info->sense = nv_ro08(bios, ent + 1);
return 0;
case DCB_I2C_NV4E_BIT:
info->drive = nv_ro08(bios, ent + 1);
return 0;
case DCB_I2C_NVIO_BIT:
case DCB_I2C_NVIO_AUX:
info->drive = nv_ro08(bios, ent + 0) & 0x0f;
if (nv_ro08(bios, ent + 1) & 0x01) {
info->share = nv_ro08(bios, ent + 1) >> 1;
info->share &= 0x0f;
}
return 0;
case DCB_I2C_UNUSED:
return 0;
default:
nv_warn(bios, "unknown i2c type %d\n", info->type);
info->type = DCB_I2C_UNUSED;
return 0;
}
}
if (bios->bmp_offset && idx < 2) {
/* BMP (from v4.0 has i2c info in the structure, it's in a
* fixed location on earlier VBIOS
*/
if (nv_ro08(bios, bios->bmp_offset + 5) < 4)
ent = 0x0048;
else
ent = 0x0036 + bios->bmp_offset;
if (idx == 0) {
info->drive = nv_ro08(bios, ent + 4);
if (!info->drive) info->drive = 0x3f;
info->sense = nv_ro08(bios, ent + 5);
if (!info->sense) info->sense = 0x3e;
} else
if (idx == 1) {
info->drive = nv_ro08(bios, ent + 6);
if (!info->drive) info->drive = 0x37;
info->sense = nv_ro08(bios, ent + 7);
if (!info->sense) info->sense = 0x36;
}
info->type = DCB_I2C_NV04_BIT;
info->share = DCB_I2C_UNUSED;
return 0;
}
return -ENOENT;
}

2185
drivers/gpu/drm/nouveau/core/subdev/bios/init.c Normal file
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File diff suppressed because it is too large Load Diff

135
drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c Normal file
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@@ -0,0 +1,135 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/mxm.h>
u16
mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr)
{
struct bit_entry x;
if (bit_entry(bios, 'x', &x)) {
nv_debug(bios, "BIT 'x' table not present\n");
return 0x0000;
}
*ver = x.version;
*hdr = x.length;
if (*ver != 1 || *hdr < 3) {
nv_warn(bios, "BIT 'x' table %d/%d unknown\n", *ver, *hdr);
return 0x0000;
}
return x.offset;
}
/* These map MXM v2.x digital connection values to the appropriate SOR/link,
* hopefully they're correct for all boards within the same chipset...
*
* MXM v3.x VBIOS are nicer and provide pointers to these tables.
*/
static u8 nv84_sor_map[16] = {
0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static u8 nv92_sor_map[16] = {
0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static u8 nv94_sor_map[16] = {
0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31,
0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00
};
static u8 nv98_sor_map[16] = {
0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31,
0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
u8
mxm_sor_map(struct nouveau_bios *bios, u8 conn)
{
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
if (mxm && hdr >= 6) {
u16 map = nv_ro16(bios, mxm + 4);
if (map) {
ver = nv_ro08(bios, map);
if (ver == 0x10) {
if (conn < nv_ro08(bios, map + 3)) {
map += nv_ro08(bios, map + 1);
map += conn;
return nv_ro08(bios, map);
}
return 0x00;
}
nv_warn(bios, "unknown sor map v%02x\n", ver);
}
}
if (bios->version.chip == 0x84 || bios->version.chip == 0x86)
return nv84_sor_map[conn];
if (bios->version.chip == 0x92)
return nv92_sor_map[conn];
if (bios->version.chip == 0x94 || bios->version.chip == 0x96)
return nv94_sor_map[conn];
if (bios->version.chip == 0x98)
return nv98_sor_map[conn];
nv_warn(bios, "missing sor map\n");
return 0x00;
}
u8
mxm_ddc_map(struct nouveau_bios *bios, u8 port)
{
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
if (mxm && hdr >= 8) {
u16 map = nv_ro16(bios, mxm + 6);
if (map) {
ver = nv_ro08(bios, map);
if (ver == 0x10) {
if (port < nv_ro08(bios, map + 3)) {
map += nv_ro08(bios, map + 1);
map += port;
return nv_ro08(bios, map);
}
return 0x00;
}
nv_warn(bios, "unknown ddc map v%02x\n", ver);
}
}
/* v2.x: directly write port as dcb i2cidx */
return (port << 4) | port;
}

201
drivers/gpu/drm/nouveau/core/subdev/bios/perf.c Normal file
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@@ -0,0 +1,201 @@
/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/perf.h>
u16
nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 perf = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version <= 2) {
perf = nv_ro16(bios, bit_P.offset + 0);
if (perf) {
*ver = nv_ro08(bios, perf + 0);
*hdr = nv_ro08(bios, perf + 1);
if (*ver >= 0x40 && *ver < 0x41) {
*cnt = nv_ro08(bios, perf + 5);
*len = nv_ro08(bios, perf + 2);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 3);
return perf;
} else
if (*ver >= 0x20 && *ver < 0x40) {
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 5);
return perf;
}
}
}
}
if (bios->bmp_offset) {
if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) {
perf = nv_ro16(bios, bios->bmp_offset + 0x94);
if (perf) {
*hdr = nv_ro08(bios, perf + 0);
*ver = nv_ro08(bios, perf + 1);
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*snr = 0;
*ssz = 0;
return perf;
}
}
}
return 0x0000;
}
u16
nvbios_perf_entry(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
if (perf && idx < *cnt) {
perf = perf + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return perf;
}
return 0x0000;
}
u16
nvbios_perfEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_perfE *info)
{
u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
info->pstate = nv_ro08(bios, perf + 0x00);
switch (!!perf * *ver) {
case 0x12:
case 0x13:
case 0x14:
info->core = nv_ro32(bios, perf + 0x01) * 10;
info->memory = nv_ro32(bios, perf + 0x05) * 20;
info->fanspeed = nv_ro08(bios, perf + 0x37);
if (*hdr > 0x38)
info->voltage = nv_ro08(bios, perf + 0x38);
break;
case 0x21:
case 0x23:
case 0x24:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->shader = nv_ro16(bios, perf + 0x06) * 1000;
info->core = info->shader + (signed char)
nv_ro08(bios, perf + 0x08) * 1000;
switch (nv_device(bios)->chipset) {
case 0x49:
case 0x4b:
info->memory = nv_ro16(bios, perf + 0x0b) * 1000;
break;
default:
info->memory = nv_ro16(bios, perf + 0x0b) * 2000;
break;
}
break;
case 0x25:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->core = nv_ro16(bios, perf + 0x06) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
break;
case 0x30:
info->script = nv_ro16(bios, perf + 0x02);
case 0x35:
info->fanspeed = nv_ro08(bios, perf + 0x06);
info->voltage = nv_ro08(bios, perf + 0x07);
info->core = nv_ro16(bios, perf + 0x08) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
info->vdec = nv_ro16(bios, perf + 0x10) * 1000;
info->disp = nv_ro16(bios, perf + 0x14) * 1000;
break;
case 0x40:
info->voltage = nv_ro08(bios, perf + 0x02);
break;
default:
return 0x0000;
}
return perf;
}
u32
nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
u32 data = 0x00000000;
if (idx < cnt) {
data = perfE + *hdr + (idx * len);
*hdr = len;
}
return data;
}
u32
nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_perfS *info)
{
u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x40:
info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000;
break;
default:
break;
}
return data;
}
int
nvbios_perf_fan_parse(struct nouveau_bios *bios,
struct nvbios_perf_fan *fan)
{
u8 ver, hdr, cnt, len, snr, ssz;
u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
if (!perf)
return -ENODEV;
if (ver >= 0x20 && ver < 0x40 && hdr > 6)
fan->pwm_divisor = nv_ro16(bios, perf + 6);
else
fan->pwm_divisor = 0;
return 0;
}

416
drivers/gpu/drm/nouveau/core/subdev/bios/pll.c Normal file
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@@ -0,0 +1,416 @@
/*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <subdev/vga.h>
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/bmp.h>
#include <subdev/bios/pll.h>
struct pll_mapping {
u8 type;
u32 reg;
};
static struct pll_mapping
nv04_pll_mapping[] = {
{ PLL_CORE , 0x680500 },
{ PLL_MEMORY, 0x680504 },
{ PLL_VPLL0 , 0x680508 },
{ PLL_VPLL1 , 0x680520 },
{}
};
static struct pll_mapping
nv40_pll_mapping[] = {
{ PLL_CORE , 0x004000 },
{ PLL_MEMORY, 0x004020 },
{ PLL_VPLL0 , 0x680508 },
{ PLL_VPLL1 , 0x680520 },
{}
};
static struct pll_mapping
nv50_pll_mapping[] = {
{ PLL_CORE , 0x004028 },
{ PLL_SHADER, 0x004020 },
{ PLL_UNK03 , 0x004000 },
{ PLL_MEMORY, 0x004008 },
{ PLL_UNK40 , 0x00e810 },
{ PLL_UNK41 , 0x00e818 },
{ PLL_UNK42 , 0x00e824 },
{ PLL_VPLL0 , 0x614100 },
{ PLL_VPLL1 , 0x614900 },
{}
};
static struct pll_mapping
nv84_pll_mapping[] = {
{ PLL_CORE , 0x004028 },
{ PLL_SHADER, 0x004020 },
{ PLL_MEMORY, 0x004008 },
{ PLL_VDEC , 0x004030 },
{ PLL_UNK41 , 0x00e818 },
{ PLL_VPLL0 , 0x614100 },
{ PLL_VPLL1 , 0x614900 },
{}
};
static u16
pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_C;
if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) {
u16 data = nv_ro16(bios, bit_C.offset + 8);
if (data) {
*ver = nv_ro08(bios, data + 0);
*hdr = nv_ro08(bios, data + 1);
*len = nv_ro08(bios, data + 2);
*cnt = nv_ro08(bios, data + 3);
return data;
}
}
if (bmp_version(bios) >= 0x0524) {
u16 data = nv_ro16(bios, bios->bmp_offset + 142);
if (data) {
*ver = nv_ro08(bios, data + 0);
*hdr = 1;
*cnt = 1;
*len = 0x18;
return data;
}
}
*ver = 0x00;
return 0x0000;
}
static struct pll_mapping *
pll_map(struct nouveau_bios *bios)
{
switch (nv_device(bios)->card_type) {
case NV_04:
case NV_10:
case NV_11:
case NV_20:
case NV_30:
return nv04_pll_mapping;
break;
case NV_40:
return nv40_pll_mapping;
case NV_50:
if (nv_device(bios)->chipset == 0x50)
return nv50_pll_mapping;
else
if (nv_device(bios)->chipset < 0xa3 ||
nv_device(bios)->chipset == 0xaa ||
nv_device(bios)->chipset == 0xac)
return nv84_pll_mapping;
default:
return NULL;
}
}
static u16
pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
{
struct pll_mapping *map;
u8 hdr, cnt;
u16 data;
data = pll_limits_table(bios, ver, &hdr, &cnt, len);
if (data && *ver >= 0x30) {
data += hdr;
while (cnt--) {
if (nv_ro32(bios, data + 3) == reg) {
*type = nv_ro08(bios, data + 0);
return data;
}
data += *len;
}
return 0x0000;
}
map = pll_map(bios);
while (map->reg) {
if (map->reg == reg && *ver >= 0x20) {
u16 addr = (data += hdr);
*type = map->type;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg)
return data;
data += *len;
}
return addr;
} else
if (map->reg == reg) {
*type = map->type;
return data + 1;
}
map++;
}
return 0x0000;
}
static u16
pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
{
struct pll_mapping *map;
u8 hdr, cnt;
u16 data;
data = pll_limits_table(bios, ver, &hdr, &cnt, len);
if (data && *ver >= 0x30) {
data += hdr;
while (cnt--) {
if (nv_ro08(bios, data + 0) == type) {
*reg = nv_ro32(bios, data + 3);
return data;
}
data += *len;
}
return 0x0000;
}
map = pll_map(bios);
while (map->reg) {
if (map->type == type && *ver >= 0x20) {
u16 addr = (data += hdr);
*reg = map->reg;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg)
return data;
data += *len;
}
return addr;
} else
if (map->type == type) {
*reg = map->reg;
return data + 1;
}
map++;
}
return 0x0000;
}
int
nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info)
{
u8 ver, len;
u32 reg = type;
u16 data;
if (type > PLL_MAX) {
reg = type;
data = pll_map_reg(bios, reg, &type, &ver, &len);
} else {
data = pll_map_type(bios, type, &reg, &ver, &len);
}
if (ver && !data)
return -ENOENT;
memset(info, 0, sizeof(*info));
info->type = type;
info->reg = reg;
switch (ver) {
case 0x00:
break;
case 0x10:
case 0x11:
info->vco1.min_freq = nv_ro32(bios, data + 0);
info->vco1.max_freq = nv_ro32(bios, data + 4);
info->vco2.min_freq = nv_ro32(bios, data + 8);
info->vco2.max_freq = nv_ro32(bios, data + 12);
info->vco1.min_inputfreq = nv_ro32(bios, data + 16);
info->vco2.min_inputfreq = nv_ro32(bios, data + 20);
info->vco1.max_inputfreq = INT_MAX;
info->vco2.max_inputfreq = INT_MAX;
info->max_p = 0x7;
info->max_p_usable = 0x6;
/* these values taken from nv30/31/36 */
switch (bios->version.chip) {
case 0x36:
info->vco1.min_n = 0x5;
break;
default:
info->vco1.min_n = 0x1;
break;
}
info->vco1.max_n = 0xff;
info->vco1.min_m = 0x1;
info->vco1.max_m = 0xd;
/*
* On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
* table version (apart from nv35)), N2 is compared to
* maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
* save a comparison
*/
info->vco2.min_n = 0x4;
switch (bios->version.chip) {
case 0x30:
case 0x35:
info->vco2.max_n = 0x1f;
break;
default:
info->vco2.max_n = 0x28;
break;
}
info->vco2.min_m = 0x1;
info->vco2.max_m = 0x4;
break;
case 0x20:
case 0x21:
info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000;
info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000;
info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000;
info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000;
info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000;
info->vco1.min_n = nv_ro08(bios, data + 20);
info->vco1.max_n = nv_ro08(bios, data + 21);
info->vco1.min_m = nv_ro08(bios, data + 22);
info->vco1.max_m = nv_ro08(bios, data + 23);
info->vco2.min_n = nv_ro08(bios, data + 24);
info->vco2.max_n = nv_ro08(bios, data + 25);
info->vco2.min_m = nv_ro08(bios, data + 26);
info->vco2.max_m = nv_ro08(bios, data + 27);
info->max_p = nv_ro08(bios, data + 29);
info->max_p_usable = info->max_p;
if (bios->version.chip < 0x60)
info->max_p_usable = 0x6;
info->bias_p = nv_ro08(bios, data + 30);
if (len > 0x22)
info->refclk = nv_ro32(bios, data + 31);
break;
case 0x30:
data = nv_ro16(bios, data + 1);
info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000;
info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000;
info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000;
info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000;
info->vco1.min_n = nv_ro08(bios, data + 16);
info->vco1.max_n = nv_ro08(bios, data + 17);
info->vco1.min_m = nv_ro08(bios, data + 18);
info->vco1.max_m = nv_ro08(bios, data + 19);
info->vco2.min_n = nv_ro08(bios, data + 20);
info->vco2.max_n = nv_ro08(bios, data + 21);
info->vco2.min_m = nv_ro08(bios, data + 22);
info->vco2.max_m = nv_ro08(bios, data + 23);
info->max_p_usable = info->max_p = nv_ro08(bios, data + 25);
info->bias_p = nv_ro08(bios, data + 27);
info->refclk = nv_ro32(bios, data + 28);
break;
case 0x40:
info->refclk = nv_ro16(bios, data + 9) * 1000;
data = nv_ro16(bios, data + 1);
info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000;
info->vco1.min_m = nv_ro08(bios, data + 8);
info->vco1.max_m = nv_ro08(bios, data + 9);
info->vco1.min_n = nv_ro08(bios, data + 10);
info->vco1.max_n = nv_ro08(bios, data + 11);
info->min_p = nv_ro08(bios, data + 12);
info->max_p = nv_ro08(bios, data + 13);
break;
default:
nv_error(bios, "unknown pll limits version 0x%02x\n", ver);
return -EINVAL;
}
if (!info->refclk) {
info->refclk = nv_device(bios)->crystal;
if (bios->version.chip == 0x51) {
u32 sel_clk = nv_rd32(bios, 0x680524);
if ((info->reg == 0x680508 && sel_clk & 0x20) ||
(info->reg == 0x680520 && sel_clk & 0x80)) {
if (nv_rdvgac(bios, 0, 0x27) < 0xa3)
info->refclk = 200000;
else
info->refclk = 25000;
}
}
}
/*
* By now any valid limit table ought to have set a max frequency for
* vco1, so if it's zero it's either a pre limit table bios, or one
* with an empty limit table (seen on nv18)
*/
if (!info->vco1.max_freq) {
info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67);
info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71);
if (bmp_version(bios) < 0x0506) {
info->vco1.max_freq = 256000;
info->vco1.min_freq = 128000;
}
info->vco1.min_inputfreq = 0;
info->vco1.max_inputfreq = INT_MAX;
info->vco1.min_n = 0x1;
info->vco1.max_n = 0xff;
info->vco1.min_m = 0x1;
if (nv_device(bios)->crystal == 13500) {
/* nv05 does this, nv11 doesn't, nv10 unknown */
if (bios->version.chip < 0x11)
info->vco1.min_m = 0x7;
info->vco1.max_m = 0xd;
} else {
if (bios->version.chip < 0x11)
info->vco1.min_m = 0x8;
info->vco1.max_m = 0xe;
}
if (bios->version.chip < 0x17 ||
bios->version.chip == 0x1a ||
bios->version.chip == 0x20)
info->max_p = 4;
else
info->max_p = 5;
info->max_p_usable = info->max_p;
}
return 0;
}

68
drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/ramcfg.h>
static u8
nvbios_ramcfg_strap(struct nouveau_subdev *subdev)
{
return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2;
}
u8
nvbios_ramcfg_count(struct nouveau_bios *bios)
{
struct bit_entry bit_M;
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 1 && bit_M.length >= 5)
return nv_ro08(bios, bit_M.offset + 2);
if (bit_M.version == 2 && bit_M.length >= 3)
return nv_ro08(bios, bit_M.offset + 0);
}
return 0x00;
}
u8
nvbios_ramcfg_index(struct nouveau_subdev *subdev)
{
struct nouveau_bios *bios = nouveau_bios(subdev);
u8 strap = nvbios_ramcfg_strap(subdev);
u32 xlat = 0x00000000;
struct bit_entry bit_M;
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 1 && bit_M.length >= 5)
xlat = nv_ro16(bios, bit_M.offset + 3);
if (bit_M.version == 2 && bit_M.length >= 3)
xlat = nv_ro16(bios, bit_M.offset + 1);
}
if (xlat)
strap = nv_ro08(bios, xlat + strap);
return strap;
}

173
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/ramcfg.h>
#include <subdev/bios/rammap.h>
u32
nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 rammap = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
rammap = nv_ro16(bios, bit_P.offset + 4);
if (rammap) {
*ver = nv_ro08(bios, rammap + 0);
switch (*ver) {
case 0x10:
case 0x11:
*hdr = nv_ro08(bios, rammap + 1);
*cnt = nv_ro08(bios, rammap + 5);
*len = nv_ro08(bios, rammap + 2);
*snr = nv_ro08(bios, rammap + 4);
*ssz = nv_ro08(bios, rammap + 3);
return rammap;
default:
break;
}
}
}
return 0x0000;
}
u32
nvbios_rammapEe(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
if (rammap && idx < *cnt) {
rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return rammap;
}
return 0x0000;
}
u32
nvbios_rammapEm(struct nouveau_bios *bios, u16 khz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
int idx = 0;
u32 data;
while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) {
if (khz >= nv_ro16(bios, data + 0x00) &&
khz <= nv_ro16(bios, data + 0x02))
break;
}
return data;
}
u32
nvbios_rammapEp(struct nouveau_bios *bios, u16 khz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ramcfg *p)
{
u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len);
memset(p, 0x00, sizeof(*p));
switch (!!data * *ver) {
case 0x11:
p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2;
p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2;
break;
default:
data = 0;
break;
}
return data;
}
u32
nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr)
{
if (idx < ecnt) {
data = data + ehdr + (idx * elen);
*ver = ever;
*hdr = elen;
return data;
}
return 0;
}
u32
nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
{
data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
switch (!!data * *ver) {
case 0x11:
p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1;
p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2;
p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3;
p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4;
p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5;
p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6;
p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7;
p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0;
p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7;
p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4;
p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6;
p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4;
p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0;
p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1;
p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2;
p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3;
p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4;
p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6;
p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7;
p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1;
p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2;
p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3;
p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5;
p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0;
break;
default:
data = 0;
break;
}
return data;
}

215
drivers/gpu/drm/nouveau/core/subdev/bios/therm.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/therm.h>
static u16
therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
{
struct bit_entry bit_P;
u16 therm = 0;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 1)
therm = nv_ro16(bios, bit_P.offset + 12);
else if (bit_P.version == 2)
therm = nv_ro16(bios, bit_P.offset + 16);
else
nv_error(bios,
"unknown offset for thermal in BIT P %d\n",
bit_P.version);
}
/* exit now if we haven't found the thermal table */
if (!therm)
return 0x0000;
*ver = nv_ro08(bios, therm + 0);
*hdr = nv_ro08(bios, therm + 1);
*len = nv_ro08(bios, therm + 2);
*cnt = nv_ro08(bios, therm + 3);
return therm + nv_ro08(bios, therm + 1);
}
static u16
nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 therm = therm_table(bios, ver, &hdr, len, &cnt);
if (therm && idx < cnt)
return therm + idx * *len;
return 0x0000;
}
int
nvbios_therm_sensor_parse(struct nouveau_bios *bios,
enum nvbios_therm_domain domain,
struct nvbios_therm_sensor *sensor)
{
s8 thrs_section, sensor_section, offset;
u8 ver, len, i;
u16 entry;
/* we only support the core domain for now */
if (domain != NVBIOS_THERM_DOMAIN_CORE)
return -EINVAL;
/* Read the entries from the table */
thrs_section = 0;
sensor_section = -1;
i = 0;
while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
s16 value = nv_ro16(bios, entry + 1);
switch (nv_ro08(bios, entry + 0)) {
case 0x0:
thrs_section = value;
if (value > 0)
return 0; /* we do not try to support ambient */
break;
case 0x01:
sensor_section++;
if (sensor_section == 0) {
offset = ((s8) nv_ro08(bios, entry + 2)) / 2;
sensor->offset_constant = offset;
}
break;
case 0x04:
if (thrs_section == 0) {
sensor->thrs_critical.temp = (value & 0xff0) >> 4;
sensor->thrs_critical.hysteresis = value & 0xf;
}
break;
case 0x07:
if (thrs_section == 0) {
sensor->thrs_down_clock.temp = (value & 0xff0) >> 4;
sensor->thrs_down_clock.hysteresis = value & 0xf;
}
break;
case 0x08:
if (thrs_section == 0) {
sensor->thrs_fan_boost.temp = (value & 0xff0) >> 4;
sensor->thrs_fan_boost.hysteresis = value & 0xf;
}
break;
case 0x10:
if (sensor_section == 0)
sensor->offset_num = value;
break;
case 0x11:
if (sensor_section == 0)
sensor->offset_den = value;
break;
case 0x12:
if (sensor_section == 0)
sensor->slope_mult = value;
break;
case 0x13:
if (sensor_section == 0)
sensor->slope_div = value;
break;
case 0x32:
if (thrs_section == 0) {
sensor->thrs_shutdown.temp = (value & 0xff0) >> 4;
sensor->thrs_shutdown.hysteresis = value & 0xf;
}
break;
}
}
return 0;
}
int
nvbios_therm_fan_parse(struct nouveau_bios *bios,
struct nvbios_therm_fan *fan)
{
struct nouveau_therm_trip_point *cur_trip = NULL;
u8 ver, len, i;
u16 entry;
uint8_t duty_lut[] = { 0, 0, 25, 0, 40, 0, 50, 0,
75, 0, 85, 0, 100, 0, 100, 0 };
i = 0;
fan->nr_fan_trip = 0;
fan->fan_mode = NVBIOS_THERM_FAN_OTHER;
while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
s16 value = nv_ro16(bios, entry + 1);
switch (nv_ro08(bios, entry + 0)) {
case 0x22:
fan->min_duty = value & 0xff;
fan->max_duty = (value & 0xff00) >> 8;
break;
case 0x24:
fan->nr_fan_trip++;
if (fan->fan_mode > NVBIOS_THERM_FAN_TRIP)
fan->fan_mode = NVBIOS_THERM_FAN_TRIP;
cur_trip = &fan->trip[fan->nr_fan_trip - 1];
cur_trip->hysteresis = value & 0xf;
cur_trip->temp = (value & 0xff0) >> 4;
cur_trip->fan_duty = duty_lut[(value & 0xf000) >> 12];
break;
case 0x25:
cur_trip = &fan->trip[fan->nr_fan_trip - 1];
cur_trip->fan_duty = value;
break;
case 0x26:
if (!fan->pwm_freq)
fan->pwm_freq = value;
break;
case 0x3b:
fan->bump_period = value;
break;
case 0x3c:
fan->slow_down_period = value;
break;
case 0x46:
if (fan->fan_mode > NVBIOS_THERM_FAN_LINEAR)
fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
fan->linear_min_temp = nv_ro08(bios, entry + 1);
fan->linear_max_temp = nv_ro08(bios, entry + 2);
break;
}
}
/* starting from fermi, fan management is always linear */
if (nv_device(bios)->card_type >= NV_C0 &&
fan->fan_mode == NVBIOS_THERM_FAN_OTHER) {
fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
}
return 0;
}

127
drivers/gpu/drm/nouveau/core/subdev/bios/timing.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/ramcfg.h>
#include <subdev/bios/timing.h>
u16
nvbios_timingTe(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 timing = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 1)
timing = nv_ro16(bios, bit_P.offset + 4);
else
if (bit_P.version == 2)
timing = nv_ro16(bios, bit_P.offset + 8);
if (timing) {
*ver = nv_ro08(bios, timing + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 2);
*len = nv_ro08(bios, timing + 3);
*snr = 0;
*ssz = 0;
return timing;
case 0x20:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 5);
*len = nv_ro08(bios, timing + 2);
*snr = nv_ro08(bios, timing + 4);
*ssz = nv_ro08(bios, timing + 3);
return timing;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_timingEe(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
if (timing && idx < *cnt) {
timing += *hdr + idx * (*len + (snr * ssz));
*hdr = *len;
*cnt = snr;
*len = ssz;
return timing;
}
return 0x0000;
}
u16
nvbios_timingEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ramcfg *p)
{
u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
switch (!!data * *ver) {
case 0x20:
p->timing[0] = nv_ro32(bios, data + 0x00);
p->timing[1] = nv_ro32(bios, data + 0x04);
p->timing[2] = nv_ro32(bios, data + 0x08);
p->timing[3] = nv_ro32(bios, data + 0x0c);
p->timing[4] = nv_ro32(bios, data + 0x10);
p->timing[5] = nv_ro32(bios, data + 0x14);
p->timing[6] = nv_ro32(bios, data + 0x18);
p->timing[7] = nv_ro32(bios, data + 0x1c);
p->timing[8] = nv_ro32(bios, data + 0x20);
p->timing[9] = nv_ro32(bios, data + 0x24);
p->timing[10] = nv_ro32(bios, data + 0x28);
p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
temp = nv_ro16(bios, data + 0x2c);
p->timing_20_2c_003f = (temp & 0x003f) >> 0;
p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
temp = nv_ro16(bios, data + 0x31);
p->timing_20_31_0007 = (temp & 0x0007) >> 0;
p->timing_20_31_0078 = (temp & 0x0078) >> 3;
p->timing_20_31_0780 = (temp & 0x0780) >> 7;
p->timing_20_31_0800 = (temp & 0x0800) >> 11;
p->timing_20_31_7000 = (temp & 0x7000) >> 12;
p->timing_20_31_8000 = (temp & 0x8000) >> 15;
break;
default:
data = 0;
break;
}
return data;
}

112
drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/vmap.h>
u16
nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 vmap = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2) {
vmap = nv_ro16(bios, bit_P.offset + 0x20);
if (vmap) {
*ver = nv_ro08(bios, vmap + 0);
switch (*ver) {
case 0x10:
case 0x20:
*hdr = nv_ro08(bios, vmap + 1);
*cnt = nv_ro08(bios, vmap + 3);
*len = nv_ro08(bios, vmap + 2);
return vmap;
default:
break;
}
}
}
}
return 0x0000;
}
u16
nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *info)
{
u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!vmap * *ver) {
case 0x10:
case 0x20:
break;
}
return vmap;
}
u16
nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len);
if (vmap && idx < cnt) {
vmap = vmap + hdr + (idx * *len);
return vmap;
}
return 0x0000;
}
u16
nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *info)
{
u16 vmap = nvbios_vmap_entry(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!vmap * *ver) {
case 0x10:
info->link = 0xff;
info->min = nv_ro32(bios, vmap + 0x00);
info->max = nv_ro32(bios, vmap + 0x04);
info->arg[0] = nv_ro32(bios, vmap + 0x08);
info->arg[1] = nv_ro32(bios, vmap + 0x0c);
info->arg[2] = nv_ro32(bios, vmap + 0x10);
break;
case 0x20:
info->unk0 = nv_ro08(bios, vmap + 0x00);
info->link = nv_ro08(bios, vmap + 0x01);
info->min = nv_ro32(bios, vmap + 0x02);
info->max = nv_ro32(bios, vmap + 0x06);
info->arg[0] = nv_ro32(bios, vmap + 0x0a);
info->arg[1] = nv_ro32(bios, vmap + 0x0e);
info->arg[2] = nv_ro32(bios, vmap + 0x12);
info->arg[3] = nv_ro32(bios, vmap + 0x16);
info->arg[4] = nv_ro32(bios, vmap + 0x1a);
info->arg[5] = nv_ro32(bios, vmap + 0x1e);
break;
}
return vmap;
}

137
drivers/gpu/drm/nouveau/core/subdev/bios/volt.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/volt.h>
u16
nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 volt = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
volt = nv_ro16(bios, bit_P.offset + 0x0c);
else
if (bit_P.version == 1)
volt = nv_ro16(bios, bit_P.offset + 0x10);
if (volt) {
*ver = nv_ro08(bios, volt + 0);
switch (*ver) {
case 0x12:
*hdr = 5;
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 1);
return volt;
case 0x20:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 3);
return volt;
case 0x30:
case 0x40:
case 0x50:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 3);
*len = nv_ro08(bios, volt + 2);
return volt;
}
}
}
return 0x0000;
}
u16
nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *info)
{
u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!volt * *ver) {
case 0x12:
info->vidmask = nv_ro08(bios, volt + 0x04);
break;
case 0x20:
info->vidmask = nv_ro08(bios, volt + 0x05);
break;
case 0x30:
info->vidmask = nv_ro08(bios, volt + 0x04);
break;
case 0x40:
info->base = nv_ro32(bios, volt + 0x04);
info->step = nv_ro16(bios, volt + 0x08);
info->vidmask = nv_ro08(bios, volt + 0x0b);
/*XXX*/
info->min = 0;
info->max = info->base;
break;
case 0x50:
info->vidmask = nv_ro08(bios, volt + 0x06);
info->min = nv_ro32(bios, volt + 0x0a);
info->max = nv_ro32(bios, volt + 0x0e);
info->base = nv_ro32(bios, volt + 0x12) & 0x00ffffff;
info->step = nv_ro16(bios, volt + 0x16);
break;
}
return volt;
}
u16
nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len);
if (volt && idx < cnt) {
volt = volt + hdr + (idx * *len);
return volt;
}
return 0x0000;
}
u16
nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *info)
{
u16 volt = nvbios_volt_entry(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!volt * *ver) {
case 0x12:
case 0x20:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01);
break;
case 0x30:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01) >> 2;
break;
case 0x40:
case 0x50:
break;
}
return volt;
}

76
drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/gpio.h>
#include <subdev/bios/xpio.h>
static u16
dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len);
if (data && *ver >= 0x40 && *hdr >= 0x06) {
u16 xpio = nv_ro16(bios, data + 0x04);
if (xpio) {
*ver = nv_ro08(bios, data + 0x00);
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
return xpio;
}
}
return 0x0000;
}
u16
dcb_xpio_table(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len);
if (data && idx < *cnt) {
u16 xpio = nv_ro16(bios, data + *hdr + (idx * *len));
if (xpio) {
*ver = nv_ro08(bios, data + 0x00);
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
return xpio;
}
}
return 0x0000;
}
u16
dcb_xpio_parse(struct nouveau_bios *bios, u8 idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_xpio *info)
{
u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len);
if (data && *len >= 6) {
info->type = nv_ro08(bios, data + 0x04);
info->addr = nv_ro08(bios, data + 0x05);
info->flags = nv_ro08(bios, data + 0x06);
}
return 0x0000;
}

145
drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <subdev/timer.h>
#include <subdev/bus.h>
struct nouveau_hwsq {
struct nouveau_bus *pbus;
u32 addr;
u32 data;
struct {
u8 data[512];
u8 size;
} c;
};
static void
hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
{
memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
hwsq->c.size += size;
}
int
nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
{
struct nouveau_hwsq *hwsq;
hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
if (hwsq) {
hwsq->pbus = pbus;
hwsq->addr = ~0;
hwsq->data = ~0;
memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
hwsq->c.size = 0;
}
return hwsq ? 0 : -ENOMEM;
}
int
nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
{
struct nouveau_hwsq *hwsq = *phwsq;
int ret = 0, i;
if (hwsq) {
struct nouveau_bus *pbus = hwsq->pbus;
hwsq->c.size = (hwsq->c.size + 4) / 4;
if (hwsq->c.size <= pbus->hwsq_size) {
if (exec)
ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data,
hwsq->c.size);
if (ret)
nv_error(pbus, "hwsq exec failed: %d\n", ret);
} else {
nv_error(pbus, "hwsq ucode too large\n");
ret = -ENOSPC;
}
for (i = 0; ret && i < hwsq->c.size; i++)
nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
*phwsq = NULL;
kfree(hwsq);
}
return ret;
}
void
nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
{
nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
if (hwsq->data != data) {
if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,
data >> 16, data >> 24 });
} else {
hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });
}
}
if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {
hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,
addr >> 16, addr >> 24 });
} else {
hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });
}
hwsq->addr = addr;
hwsq->data = data;
}
void
nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
{
nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
flag += 0x80;
if (data >= 0)
flag += 0x20;
if (data >= 1)
flag += 0x20;
hwsq_cmd(hwsq, 1, (u8[]){ flag });
}
void
nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
{
nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
}
void
nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
{
u8 shift = 0, usec = nsec / 1000;
while (usec & ~3) {
usec >>= 2;
shift++;
}
nv_debug(hwsq->pbus, " DELAY = %d ns\n", nsec);
hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
}

113
drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h Normal file
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#ifndef __NVKM_BUS_HWSQ_H__
#define __NVKM_BUS_HWSQ_H__
#include <subdev/bus.h>
struct hwsq {
struct nouveau_subdev *subdev;
struct nouveau_hwsq *hwsq;
int sequence;
};
struct hwsq_reg {
int sequence;
bool force;
u32 addr[2];
u32 data;
};
static inline struct hwsq_reg
hwsq_reg2(u32 addr1, u32 addr2)
{
return (struct hwsq_reg) {
.sequence = 0,
.force = 0,
.addr = { addr1, addr2 },
.data = 0xdeadbeef,
};
}
static inline struct hwsq_reg
hwsq_reg(u32 addr)
{
return hwsq_reg2(addr, addr);
}
static inline int
hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
int ret;
ret = nouveau_hwsq_init(pbus, &ram->hwsq);
if (ret)
return ret;
ram->sequence++;
ram->subdev = subdev;
return 0;
}
static inline int
hwsq_exec(struct hwsq *ram, bool exec)
{
int ret = 0;
if (ram->subdev) {
ret = nouveau_hwsq_fini(&ram->hwsq, exec);
ram->subdev = NULL;
}
return ret;
}
static inline u32
hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
{
if (reg->sequence != ram->sequence)
reg->data = nv_rd32(ram->subdev, reg->addr[0]);
return reg->data;
}
static inline void
hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
{
reg->sequence = ram->sequence;
reg->data = data;
if (reg->addr[0] != reg->addr[1])
nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
}
static inline void
hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
{
reg->force = true;
}
static inline u32
hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
{
u32 temp = hwsq_rd32(ram, reg);
if (temp != ((temp & ~mask) | data) || reg->force)
hwsq_wr32(ram, reg, (temp & ~mask) | data);
return temp;
}
static inline void
hwsq_setf(struct hwsq *ram, u8 flag, int data)
{
nouveau_hwsq_setf(ram->hwsq, flag, data);
}
static inline void
hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
{
nouveau_hwsq_wait(ram->hwsq, flag, data);
}
static inline void
hwsq_nsec(struct hwsq *ram, u32 nsec)
{
nouveau_hwsq_nsec(ram->hwsq, nsec);
}
#endif

95
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
static void
nv04_bus_intr(struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x00000001) {
nv_error(pbus, "BUS ERROR\n");
stat &= ~0x00000001;
nv_wr32(pbus, 0x001100, 0x00000001);
}
if (stat & 0x00000110) {
subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00000110;
nv_wr32(pbus, 0x001100, 0x00000110);
}
if (stat) {
nv_error(pbus, "unknown intr 0x%08x\n", stat);
nv_mask(pbus, 0x001140, stat, 0x00000000);
}
}
static int
nv04_bus_init(struct nouveau_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
nv_wr32(priv, 0x001100, 0xffffffff);
nv_wr32(priv, 0x001140, 0x00000111);
return nouveau_bus_init(&priv->base);
}
int
nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_bus_impl *impl = (void *)oclass;
struct nv04_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = impl->intr;
priv->base.hwsq_exec = impl->hwsq_exec;
priv->base.hwsq_size = impl->hwsq_size;
return 0;
}
struct nouveau_oclass *
nv04_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x04),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv04_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nv04_bus_intr,
}.base;

23
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h Normal file
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#ifndef __NVKM_BUS_NV04_H__
#define __NVKM_BUS_NV04_H__
#include <subdev/bus.h>
struct nv04_bus_priv {
struct nouveau_bus base;
};
int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
int nv50_bus_init(struct nouveau_object *);
void nv50_bus_intr(struct nouveau_subdev *);
struct nv04_bus_impl {
struct nouveau_oclass base;
void (*intr)(struct nouveau_subdev *);
int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
u32 hwsq_size;
};
#endif

92
drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
static void
nv31_bus_intr(struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
if (gpio) {
subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);
if (subdev && subdev->intr)
subdev->intr(subdev);
}
if (stat & 0x00000008) { /* NV41- */
u32 addr = nv_rd32(pbus, 0x009084);
u32 data = nv_rd32(pbus, 0x009088);
nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
(addr & 0x00000002) ? "write" : "read", data,
(addr & 0x00fffffc));
stat &= ~0x00000008;
nv_wr32(pbus, 0x001100, 0x00000008);
}
if (stat & 0x00070000) {
subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00070000;
nv_wr32(pbus, 0x001100, 0x00070000);
}
if (stat) {
nv_error(pbus, "unknown intr 0x%08x\n", stat);
nv_mask(pbus, 0x001140, stat, 0x00000000);
}
}
static int
nv31_bus_init(struct nouveau_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
if (ret)
return ret;
nv_wr32(priv, 0x001100, 0xffffffff);
nv_wr32(priv, 0x001140, 0x00070008);
return 0;
}
struct nouveau_oclass *
nv31_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x31),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv31_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nv31_bus_intr,
}.base;

105
drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include <subdev/timer.h>
#include "nv04.h"
static int
nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
nv_wr32(pbus, 0x001304, 0x00000000);
for (i = 0; i < size; i++)
nv_wr32(priv, 0x001400 + (i * 4), data[i]);
nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
nv_wr32(pbus, 0x00130c, 0x00000003);
return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
}
void
nv50_bus_intr(struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x00000008) {
u32 addr = nv_rd32(pbus, 0x009084);
u32 data = nv_rd32(pbus, 0x009088);
nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
(addr & 0x00000002) ? "write" : "read", data,
(addr & 0x00fffffc));
stat &= ~0x00000008;
nv_wr32(pbus, 0x001100, 0x00000008);
}
if (stat & 0x00010000) {
subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
if (subdev && subdev->intr)
subdev->intr(subdev);
stat &= ~0x00010000;
nv_wr32(pbus, 0x001100, 0x00010000);
}
if (stat) {
nv_error(pbus, "unknown intr 0x%08x\n", stat);
nv_mask(pbus, 0x001140, stat, 0);
}
}
int
nv50_bus_init(struct nouveau_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
if (ret)
return ret;
nv_wr32(priv, 0x001100, 0xffffffff);
nv_wr32(priv, 0x001140, 0x00010008);
return 0;
}
struct nouveau_oclass *
nv50_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv50_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nv50_bus_intr,
.hwsq_exec = nv50_bus_hwsq_exec,
.hwsq_size = 64,
}.base;

59
drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include <subdev/timer.h>
#include "nv04.h"
static int
nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
nv_wr32(pbus, 0x001304, 0x00000000);
nv_wr32(pbus, 0x001318, 0x00000000);
for (i = 0; i < size; i++)
nv_wr32(priv, 0x080000 + (i * 4), data[i]);
nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
nv_wr32(pbus, 0x00130c, 0x00000001);
return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
}
struct nouveau_oclass *
nv94_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x94),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv50_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nv50_bus_intr,
.hwsq_exec = nv94_bus_hwsq_exec,
.hwsq_size = 128,
}.base;

81
drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c Normal file
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/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
static void
nvc0_bus_intr(struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
if (stat & 0x0000000e) {
u32 addr = nv_rd32(pbus, 0x009084);
u32 data = nv_rd32(pbus, 0x009088);
nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
(addr & 0x00000002) ? "write" : "read", data,
(addr & 0x00fffffc),
(stat & 0x00000002) ? "!ENGINE " : "",
(stat & 0x00000004) ? "IBUS " : "",
(stat & 0x00000008) ? "TIMEOUT " : "");
nv_wr32(pbus, 0x009084, 0x00000000);
nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
stat &= ~0x0000000e;
}
if (stat) {
nv_error(pbus, "unknown intr 0x%08x\n", stat);
nv_mask(pbus, 0x001140, stat, 0x00000000);
}
}
static int
nvc0_bus_init(struct nouveau_object *object)
{
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
if (ret)
return ret;
nv_wr32(priv, 0x001100, 0xffffffff);
nv_wr32(priv, 0x001140, 0x0000000e);
return 0;
}
struct nouveau_oclass *
nvc0_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nvc0_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nvc0_bus_intr,
}.base;

500
drivers/gpu/drm/nouveau/core/subdev/clock/base.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <subdev/clock.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <subdev/fb.h>
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
/******************************************************************************
* misc
*****************************************************************************/
static u32
nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nvbios_boostE boostE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
if (data) {
struct nvbios_boostS boostS;
u8 idx = 0, sver, shdr;
u16 subd;
input = max(boostE.min, input);
input = min(boostE.max, input);
do {
sver = ver;
shdr = hdr;
subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
cnt, len, &boostS);
if (subd && boostS.domain == domain) {
if (adjust)
input = input * boostS.percent / 100;
input = max(boostS.min, input);
input = min(boostS.max, input);
break;
}
} while (subd);
}
return input;
}
/******************************************************************************
* C-States
*****************************************************************************/
static int
nouveau_cstate_prog(struct nouveau_clock *clk,
struct nouveau_pstate *pstate, int cstatei)
{
struct nouveau_therm *ptherm = nouveau_therm(clk);
struct nouveau_volt *volt = nouveau_volt(clk);
struct nouveau_cstate *cstate;
int ret;
if (!list_empty(&pstate->list)) {
cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
} else {
cstate = &pstate->base;
}
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise fan speed: %d\n", ret);
return ret;
}
ret = volt->set_id(volt, cstate->voltage, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise voltage: %d\n", ret);
return ret;
}
ret = clk->calc(clk, cstate);
if (ret == 0) {
ret = clk->prog(clk);
clk->tidy(clk);
}
ret = volt->set_id(volt, cstate->voltage, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower voltage: %d\n", ret);
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower fan speed: %d\n", ret);
return 0;
}
static void
nouveau_cstate_del(struct nouveau_cstate *cstate)
{
list_del(&cstate->head);
kfree(cstate);
}
static int
nouveau_cstate_new(struct nouveau_clock *clk, int idx,
struct nouveau_pstate *pstate)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains;
struct nouveau_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
u16 data;
data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
if (!data)
return -ENOENT;
cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (!cstate)
return -ENOMEM;
*cstate = pstate->base;
cstate->voltage = cstepX.voltage;
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
u32 freq = nouveau_clock_adjust(clk, true,
pstate->pstate,
domain->bios,
cstepX.freq);
cstate->domain[domain->name] = freq;
}
domain++;
}
list_add(&cstate->head, &pstate->list);
return 0;
}
/******************************************************************************
* P-States
*****************************************************************************/
static int
nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
{
struct nouveau_fb *pfb = nouveau_fb(clk);
struct nouveau_pstate *pstate;
int ret, idx = 0;
list_for_each_entry(pstate, &clk->states, head) {
if (idx++ == pstatei)
break;
}
nv_debug(clk, "setting performance state %d\n", pstatei);
clk->pstate = pstatei;
if (pfb->ram->calc) {
int khz = pstate->base.domain[nv_clk_src_mem];
do {
ret = pfb->ram->calc(pfb, khz);
if (ret == 0)
ret = pfb->ram->prog(pfb);
} while (ret > 0);
pfb->ram->tidy(pfb);
}
return nouveau_cstate_prog(clk, pstate, 0);
}
static int
nouveau_pstate_calc(struct nouveau_clock *clk)
{
int pstate, ret = 0;
nv_trace(clk, "P %d U %d A %d T %d D %d\n", clk->pstate,
clk->ustate, clk->astate, clk->tstate, clk->dstate);
if (clk->state_nr && clk->ustate != -1) {
pstate = (clk->ustate < 0) ? clk->astate : clk->ustate;
pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
pstate = max(pstate, clk->dstate);
} else {
pstate = clk->pstate = -1;
}
nv_trace(clk, "-> %d\n", pstate);
if (pstate != clk->pstate)
ret = nouveau_pstate_prog(clk, pstate);
return ret;
}
static void
nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
{
struct nouveau_clocks *clock = clk->domains - 1;
struct nouveau_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
int i = -1;
if (pstate->pstate != 0xff)
snprintf(name, sizeof(name), "%02x", pstate->pstate);
while ((++clock)->name != nv_clk_src_max) {
u32 lo = pstate->base.domain[clock->name];
u32 hi = lo;
if (hi == 0)
continue;
nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
list_for_each_entry(cstate, &pstate->list, head) {
u32 freq = cstate->domain[clock->name];
lo = min(lo, freq);
hi = max(hi, freq);
nv_debug(clk, "%10d KHz\n", freq);
}
if (clock->mname && ++i < ARRAY_SIZE(info)) {
lo /= clock->mdiv;
hi /= clock->mdiv;
if (lo == hi) {
snprintf(info[i], sizeof(info[i]), "%s %d MHz",
clock->mname, lo);
} else {
snprintf(info[i], sizeof(info[i]),
"%s %d-%d MHz", clock->mname, lo, hi);
}
}
}
nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
}
static void
nouveau_pstate_del(struct nouveau_pstate *pstate)
{
struct nouveau_cstate *cstate, *temp;
list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
nouveau_cstate_del(cstate);
}
list_del(&pstate->head);
kfree(pstate);
}
static int
nouveau_pstate_new(struct nouveau_clock *clk, int idx)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains - 1;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
struct nvbios_cstepE cstepE;
struct nvbios_perfE perfE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
if (!data)
return -EINVAL;
if (perfE.pstate == 0xff)
return 0;
pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
cstate = &pstate->base;
if (!pstate)
return -ENOMEM;
INIT_LIST_HEAD(&pstate->list);
pstate->pstate = perfE.pstate;
pstate->fanspeed = perfE.fanspeed;
cstate->voltage = perfE.voltage;
cstate->domain[nv_clk_src_core] = perfE.core;
cstate->domain[nv_clk_src_shader] = perfE.shader;
cstate->domain[nv_clk_src_mem] = perfE.memory;
cstate->domain[nv_clk_src_vdec] = perfE.vdec;
cstate->domain[nv_clk_src_dom6] = perfE.disp;
while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
struct nvbios_perfS perfS;
u8 sver = ver, shdr = hdr;
u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
&sver, &shdr, cnt, len, &perfS);
if (perfSe == 0 || sver != 0x40)
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
perfS.v40.freq = nouveau_clock_adjust(clk, false,
pstate->pstate,
domain->bios,
perfS.v40.freq);
}
cstate->domain[domain->name] = perfS.v40.freq;
}
data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
if (data) {
int idx = cstepE.index;
do {
nouveau_cstate_new(clk, idx, pstate);
} while(idx--);
}
nouveau_pstate_info(clk, pstate);
list_add_tail(&pstate->head, &clk->states);
clk->state_nr++;
return 0;
}
/******************************************************************************
* Adjustment triggers
*****************************************************************************/
static int
nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
{
struct nouveau_pstate *pstate;
int i = 0;
if (!clk->allow_reclock)
return -ENOSYS;
if (req != -1 && req != -2) {
list_for_each_entry(pstate, &clk->states, head) {
if (pstate->pstate == req)
break;
i++;
}
if (pstate->pstate != req)
return -EINVAL;
req = i;
}
clk->ustate = req;
return 0;
}
int
nouveau_clock_ustate(struct nouveau_clock *clk, int req)
{
int ret = nouveau_clock_ustate_update(clk, req);
if (ret)
return ret;
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
clk->astate = min(clk->astate, clk->state_nr - 1);
clk->astate = max(clk->astate, 0);
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
clk->tstate = min(clk->tstate, 0);
clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
clk->dstate = min(clk->dstate, clk->state_nr - 1);
clk->dstate = max(clk->dstate, 0);
return nouveau_pstate_calc(clk);
}
/******************************************************************************
* subdev base class implementation
*****************************************************************************/
int
_nouveau_clock_init(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_clocks *clock = clk->domains;
int ret;
memset(&clk->bstate, 0x00, sizeof(clk->bstate));
INIT_LIST_HEAD(&clk->bstate.list);
clk->bstate.pstate = 0xff;
while (clock->name != nv_clk_src_max) {
ret = clk->read(clk, clock->name);
if (ret < 0) {
nv_error(clk, "%02x freq unknown\n", clock->name);
return ret;
}
clk->bstate.base.domain[clock->name] = ret;
clock++;
}
nouveau_pstate_info(clk, &clk->bstate);
clk->astate = clk->state_nr - 1;
clk->tstate = 0;
clk->dstate = 0;
clk->pstate = -1;
nouveau_pstate_calc(clk);
return 0;
}
void
_nouveau_clock_dtor(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_pstate *pstate, *temp;
list_for_each_entry_safe(pstate, temp, &clk->states, head) {
nouveau_pstate_del(pstate);
}
nouveau_subdev_destroy(&clk->base);
}
int
nouveau_clock_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
struct nouveau_clocks *clocks,
bool allow_reclock,
int length, void **object)
{
struct nouveau_device *device = nv_device(parent);
struct nouveau_clock *clk;
int ret, idx, arglen;
const char *mode;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
"clock", length, object);
clk = *object;
if (ret)
return ret;
INIT_LIST_HEAD(&clk->states);
clk->domains = clocks;
clk->ustate = -1;
idx = 0;
do {
ret = nouveau_pstate_new(clk, idx++);
} while (ret == 0);
clk->allow_reclock = allow_reclock;
mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
if (!strncasecmpz(mode, "disabled", arglen)) {
clk->ustate = -1;
} else {
char save = mode[arglen];
long v;
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v))
nouveau_clock_ustate_update(clk, v);
((char *)mode)[arglen] = save;
}
}
return 0;
}

105
drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/clock.h>
#include <subdev/devinit/nv04.h>
#include "pll.h"
struct nv04_clock_priv {
struct nouveau_clock base;
};
int
nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
int clk, struct nouveau_pll_vals *pv)
{
int N1, M1, N2, M2, P;
int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
if (ret) {
pv->refclk = info->refclk;
pv->N1 = N1;
pv->M1 = M1;
pv->N2 = N2;
pv->M2 = M2;
pv->log2P = P;
}
return ret;
}
int
nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
struct nouveau_pll_vals *pv)
{
struct nouveau_devinit *devinit = nouveau_devinit(clk);
int cv = nouveau_bios(clk)->version.chip;
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
cv >= 0x40) {
if (reg1 > 0x405c)
setPLL_double_highregs(devinit, reg1, pv);
else
setPLL_double_lowregs(devinit, reg1, pv);
} else
setPLL_single(devinit, reg1, pv);
return 0;
}
static struct nouveau_clocks
nv04_domain[] = {
{ nv_clk_src_max }
};
static int
nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, false,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nv04_clock_pll_calc;
priv->base.pll_prog = nv04_clock_pll_prog;
return 0;
}
struct nouveau_oclass
nv04_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

240
drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
struct nv40_clock_priv {
struct nouveau_clock base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
static struct nouveau_clocks
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_max }
};
static u32
read_pll_1(struct nv40_clock_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
int P = (ctrl & 0x00070000) >> 16;
int N = (ctrl & 0x0000ff00) >> 8;
int M = (ctrl & 0x000000ff) >> 0;
u32 ref = 27000, clk = 0;
if (ctrl & 0x80000000)
clk = ref * N / M;
return clk >> P;
}
static u32
read_pll_2(struct nv40_clock_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
u32 coef = nv_rd32(priv, reg + 0x04);
int N2 = (coef & 0xff000000) >> 24;
int M2 = (coef & 0x00ff0000) >> 16;
int N1 = (coef & 0x0000ff00) >> 8;
int M1 = (coef & 0x000000ff) >> 0;
int P = (ctrl & 0x00070000) >> 16;
u32 ref = 27000, clk = 0;
if ((ctrl & 0x80000000) && M1) {
clk = ref * N1 / M1;
if ((ctrl & 0x40000100) == 0x40000000) {
if (M2)
clk = clk * N2 / M2;
else
clk = 0;
}
}
return clk >> P;
}
static u32
read_clk(struct nv40_clock_priv *priv, u32 src)
{
switch (src) {
case 3:
return read_pll_2(priv, 0x004000);
case 2:
return read_pll_1(priv, 0x004008);
default:
break;
}
return 0;
}
static int
nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nv40_clock_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000; /*XXX: PCIE/AGP differ*/
case nv_clk_src_core:
return read_clk(priv, (mast & 0x00000003) >> 0);
case nv_clk_src_shader:
return read_clk(priv, (mast & 0x00000030) >> 4);
case nv_clk_src_mem:
return read_pll_2(priv, 0x4020);
default:
break;
}
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
return -EINVAL;
}
static int
nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
if (ret)
return ret;
if (clk < pll.vco1.max_freq)
pll.vco2.max_freq = 0;
ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
if (ret == 0)
return -ERANGE;
return ret;
}
static int
nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nv40_clock_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
int sclk = cstate->domain[nv_clk_src_shader];
int N1, M1, N2, M2, log2P;
int ret;
/* core/geometric clock */
ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
if (N2 == M2) {
priv->npll_ctrl = 0x80000100 | (log2P << 16);
priv->npll_coef = (N1 << 8) | M1;
} else {
priv->npll_ctrl = 0xc0000000 | (log2P << 16);
priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
}
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
&N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
priv->ctrl = 0x00000223;
} else {
priv->spll = 0x00000000;
priv->ctrl = 0x00000333;
}
return 0;
}
static int
nv40_clock_prog(struct nouveau_clock *clk)
{
struct nv40_clock_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
nv_wr32(priv, 0x004004, priv->npll_coef);
nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
mdelay(5);
nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl);
return 0;
}
static void
nv40_clock_tidy(struct nouveau_clock *clk)
{
}
static int
nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, true,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.pll_calc = nv04_clock_pll_calc;
priv->base.pll_prog = nv04_clock_pll_prog;
priv->base.read = nv40_clock_read;
priv->base.calc = nv40_clock_calc;
priv->base.prog = nv40_clock_prog;
priv->base.tidy = nv40_clock_tidy;
return 0;
}
struct nouveau_oclass
nv40_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

559
drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c Normal file
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@@ -0,0 +1,559 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "nv50.h"
#include "pll.h"
#include "seq.h"
static u32
read_div(struct nv50_clock_priv *priv)
{
switch (nv_device(priv)->chipset) {
case 0x50: /* it exists, but only has bit 31, not the dividers.. */
case 0x84:
case 0x86:
case 0x98:
case 0xa0:
return nv_rd32(priv, 0x004700);
case 0x92:
case 0x94:
case 0x96:
return nv_rd32(priv, 0x004800);
default:
return 0x00000000;
}
}
static u32
read_pll_src(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
switch (nv_device(priv)->chipset) {
case 0x50:
case 0xa0:
switch (base) {
case 0x4020:
case 0x4028: id = !!(rsel & 0x00000004); break;
case 0x4008: id = !!(rsel & 0x00000008); break;
case 0x4030: id = 0; break;
default:
nv_error(priv, "ref: bad pll 0x%06x\n", base);
return 0;
}
coef = nv_rd32(priv, 0x00e81c + (id * 0x0c));
ref *= (coef & 0x01000000) ? 2 : 4;
P = (coef & 0x00070000) >> 16;
N = ((coef & 0x0000ff00) >> 8) + 1;
M = ((coef & 0x000000ff) >> 0) + 1;
break;
case 0x84:
case 0x86:
case 0x92:
coef = nv_rd32(priv, 0x00e81c);
P = (coef & 0x00070000) >> 16;
N = (coef & 0x0000ff00) >> 8;
M = (coef & 0x000000ff) >> 0;
break;
case 0x94:
case 0x96:
case 0x98:
rsel = nv_rd32(priv, 0x00c050);
switch (base) {
case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
case 0x4030: rsel = 3; break;
default:
nv_error(priv, "ref: bad pll 0x%06x\n", base);
return 0;
}
switch (rsel) {
case 0: id = 1; break;
case 1: return clk->read(clk, nv_clk_src_crystal);
case 2: return clk->read(clk, nv_clk_src_href);
case 3: id = 0; break;
}
coef = nv_rd32(priv, 0x00e81c + (id * 0x28));
P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7;
P += (coef & 0x00070000) >> 16;
N = (coef & 0x0000ff00) >> 8;
M = (coef & 0x000000ff) >> 0;
break;
default:
BUG_ON(1);
}
if (M)
return (ref * N / M) >> P;
return 0;
}
static u32
read_pll_ref(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
case 0x004028:
src = !!(mast & 0x00200000);
break;
case 0x004020:
src = !!(mast & 0x00400000);
break;
case 0x004008:
src = !!(mast & 0x00010000);
break;
case 0x004030:
src = !!(mast & 0x02000000);
break;
case 0x00e810:
return clk->read(clk, nv_clk_src_crystal);
default:
nv_error(priv, "bad pll 0x%06x\n", base);
return 0;
}
if (src)
return clk->read(clk, nv_clk_src_href);
return read_pll_src(priv, base);
}
static u32
read_pll(struct nv50_clock_priv *priv, u32 base)
{
struct nouveau_clock *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
u32 ref = read_pll_ref(priv, base);
u32 freq = 0;
int N1, N2, M1, M2;
if (base == 0x004028 && (mast & 0x00100000)) {
/* wtf, appears to only disable post-divider on nva0 */
if (nv_device(priv)->chipset != 0xa0)
return clk->read(clk, nv_clk_src_dom6);
}
N2 = (coef & 0xff000000) >> 24;
M2 = (coef & 0x00ff0000) >> 16;
N1 = (coef & 0x0000ff00) >> 8;
M1 = (coef & 0x000000ff);
if ((ctrl & 0x80000000) && M1) {
freq = ref * N1 / M1;
if ((ctrl & 0x40000100) == 0x40000000) {
if (M2)
freq = freq * N2 / M2;
else
freq = 0;
}
}
return freq;
}
static int
nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nv50_clock_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
u32 P = 0;
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000; /* PCIE reference clock */
case nv_clk_src_hclk:
return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000);
case nv_clk_src_hclkm3:
return clk->read(clk, nv_clk_src_hclk) * 3;
case nv_clk_src_hclkm3d2:
return clk->read(clk, nv_clk_src_hclk) * 3 / 2;
case nv_clk_src_host:
switch (mast & 0x30000000) {
case 0x00000000: return clk->read(clk, nv_clk_src_href);
case 0x10000000: break;
case 0x20000000: /* !0x50 */
case 0x30000000: return clk->read(clk, nv_clk_src_hclk);
}
break;
case nv_clk_src_core:
if (!(mast & 0x00100000))
P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16;
switch (mast & 0x00000003) {
case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000001: return clk->read(clk, nv_clk_src_dom6);
case 0x00000002: return read_pll(priv, 0x004020) >> P;
case 0x00000003: return read_pll(priv, 0x004028) >> P;
}
break;
case nv_clk_src_shader:
P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16;
switch (mast & 0x00000030) {
case 0x00000000:
if (mast & 0x00000080)
return clk->read(clk, nv_clk_src_host) >> P;
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000010: break;
case 0x00000020: return read_pll(priv, 0x004028) >> P;
case 0x00000030: return read_pll(priv, 0x004020) >> P;
}
break;
case nv_clk_src_mem:
P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16;
if (nv_rd32(priv, 0x004008) & 0x00000200) {
switch (mast & 0x0000c000) {
case 0x00000000:
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00008000:
case 0x0000c000:
return clk->read(clk, nv_clk_src_href) >> P;
}
} else {
return read_pll(priv, 0x004008) >> P;
}
break;
case nv_clk_src_vdec:
P = (read_div(priv) & 0x00000700) >> 8;
switch (nv_device(priv)->chipset) {
case 0x84:
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0xa0:
switch (mast & 0x00000c00) {
case 0x00000000:
if (nv_device(priv)->chipset == 0xa0) /* wtf?? */
return clk->read(clk, nv_clk_src_core) >> P;
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000400:
return 0;
case 0x00000800:
if (mast & 0x01000000)
return read_pll(priv, 0x004028) >> P;
return read_pll(priv, 0x004030) >> P;
case 0x00000c00:
return clk->read(clk, nv_clk_src_core) >> P;
}
break;
case 0x98:
switch (mast & 0x00000c00) {
case 0x00000000:
return clk->read(clk, nv_clk_src_core) >> P;
case 0x00000400:
return 0;
case 0x00000800:
return clk->read(clk, nv_clk_src_hclkm3d2) >> P;
case 0x00000c00:
return clk->read(clk, nv_clk_src_mem) >> P;
}
break;
}
break;
case nv_clk_src_dom6:
switch (nv_device(priv)->chipset) {
case 0x50:
case 0xa0:
return read_pll(priv, 0x00e810) >> 2;
case 0x84:
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0x98:
P = (read_div(priv) & 0x00000007) >> 0;
switch (mast & 0x0c000000) {
case 0x00000000: return clk->read(clk, nv_clk_src_href);
case 0x04000000: break;
case 0x08000000: return clk->read(clk, nv_clk_src_hclk);
case 0x0c000000:
return clk->read(clk, nv_clk_src_hclkm3) >> P;
}
break;
default:
break;
}
default:
break;
}
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
return -EINVAL;
}
static u32
calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
if (ret)
return 0;
pll.vco2.max_freq = 0;
pll.refclk = read_pll_ref(priv, reg);
if (!pll.refclk)
return 0;
return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P);
}
static inline u32
calc_div(u32 src, u32 target, int *div)
{
u32 clk0 = src, clk1 = src;
for (*div = 0; *div <= 7; (*div)++) {
if (clk0 <= target) {
clk1 = clk0 << (*div ? 1 : 0);
break;
}
clk0 >>= 1;
}
if (target - clk0 <= clk1 - target)
return clk0;
(*div)--;
return clk1;
}
static inline u32
clk_same(u32 a, u32 b)
{
return ((a / 1000) == (b / 1000));
}
static int
nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nv50_clock_priv *priv = (void *)clk;
struct nv50_clock_hwsq *hwsq = &priv->hwsq;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
const int dom6 = cstate->domain[nv_clk_src_dom6];
u32 mastm = 0, mastv = 0;
u32 divsm = 0, divsv = 0;
int N, M, P1, P2;
int freq, out;
/* prepare a hwsq script from which we'll perform the reclock */
out = clk_init(hwsq, nv_subdev(clk));
if (out)
return out;
clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
clk_nsec(hwsq, 8000);
clk_setf(hwsq, 0x10, 0x00); /* disable fb */
clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
/* vdec: avoid modifying xpll until we know exactly how the other
* clock domains work, i suspect at least some of them can also be
* tied to xpll...
*/
if (vdec) {
/* see how close we can get using nvclk as a source */
freq = calc_div(core, vdec, &P1);
/* see how close we can get using xpll/hclk as a source */
if (nv_device(priv)->chipset != 0x98)
out = read_pll(priv, 0x004030);
else
out = clk->read(clk, nv_clk_src_hclkm3d2);
out = calc_div(out, vdec, &P2);
/* select whichever gets us closest */
if (abs(vdec - freq) <= abs(vdec - out)) {
if (nv_device(priv)->chipset != 0x98)
mastv |= 0x00000c00;
divsv |= P1 << 8;
} else {
mastv |= 0x00000800;
divsv |= P2 << 8;
}
mastm |= 0x00000c00;
divsm |= 0x00000700;
}
/* dom6: nfi what this is, but we're limited to various combinations
* of the host clock frequency
*/
if (dom6) {
if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) {
mastv |= 0x00000000;
} else
if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) {
mastv |= 0x08000000;
} else {
freq = clk->read(clk, nv_clk_src_hclk) * 3;
freq = calc_div(freq, dom6, &P1);
mastv |= 0x0c000000;
divsv |= P1;
}
mastm |= 0x0c000000;
divsm |= 0x00000007;
}
/* vdec/dom6: switch to "safe" clocks temporarily, update dividers
* and then switch to target clocks
*/
clk_mask(hwsq, mast, mastm, 0x00000000);
clk_mask(hwsq, divs, divsm, divsv);
clk_mask(hwsq, mast, mastm, mastv);
/* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
* sclk to hclk) before reprogramming
*/
if (nv_device(priv)->chipset < 0x92)
clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
else
clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
/* core: for the moment at least, always use nvpll */
freq = calc_pll(priv, 0x4028, core, &N, &M, &P1);
if (freq == 0)
return -ERANGE;
clk_mask(hwsq, nvpll[0], 0xc03f0100,
0x80000000 | (P1 << 19) | (P1 << 16));
clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
/* shader: tie to nvclk if possible, otherwise use spll. have to be
* very careful that the shader clock is at least twice the core, or
* some chipsets will be very unhappy. i expect most or all of these
* cases will be handled by tying to nvclk, but it's possible there's
* corners
*/
if (P1-- && shader == (core << 1)) {
clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
clk_mask(hwsq, mast, 0x00100033, 0x00000023);
} else {
freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
if (freq == 0)
return -ERANGE;
clk_mask(hwsq, spll[0], 0xc03f0100,
0x80000000 | (P1 << 19) | (P1 << 16));
clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
clk_mask(hwsq, mast, 0x00100033, 0x00000033);
}
/* restore normal operation */
clk_setf(hwsq, 0x10, 0x01); /* enable fb */
clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
return 0;
}
static int
nv50_clock_prog(struct nouveau_clock *clk)
{
struct nv50_clock_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
nv50_clock_tidy(struct nouveau_clock *clk)
{
struct nv50_clock_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_clock_oclass *pclass = (void *)oclass;
struct nv50_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->hwsq.r_fifo = hwsq_reg(0x002504);
priv->hwsq.r_spll[0] = hwsq_reg(0x004020);
priv->hwsq.r_spll[1] = hwsq_reg(0x004024);
priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
switch (nv_device(priv)->chipset) {
case 0x92:
case 0x94:
case 0x96:
priv->hwsq.r_divs = hwsq_reg(0x004800);
break;
default:
priv->hwsq.r_divs = hwsq_reg(0x004700);
break;
}
priv->hwsq.r_mast = hwsq_reg(0x00c040);
priv->base.read = nv50_clock_read;
priv->base.calc = nv50_clock_calc;
priv->base.prog = nv50_clock_prog;
priv->base.tidy = nv50_clock_tidy;
return 0;
}
static struct nouveau_clocks
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_max }
};
struct nouveau_oclass *
nv50_clock_oclass = &(struct nv50_clock_oclass) {
.base.handle = NV_SUBDEV(CLOCK, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
.domains = nv50_domains,
}.base;

31
drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h Normal file
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@@ -0,0 +1,31 @@
#ifndef __NVKM_CLK_NV50_H__
#define __NVKM_CLK_NV50_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#include <subdev/clock.h>
struct nv50_clock_hwsq {
struct hwsq base;
struct hwsq_reg r_fifo;
struct hwsq_reg r_spll[2];
struct hwsq_reg r_nvpll[2];
struct hwsq_reg r_divs;
struct hwsq_reg r_mast;
};
struct nv50_clock_priv {
struct nouveau_clock base;
struct nv50_clock_hwsq hwsq;
};
int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
struct nv50_clock_oclass {
struct nouveau_oclass base;
struct nouveau_clocks *domains;
};
#endif

48
drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c Normal file
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@@ -0,0 +1,48 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nv50.h"
static struct nouveau_clocks
nv84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_mem , 0xff, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0xff },
{ nv_clk_src_max }
};
struct nouveau_oclass *
nv84_clock_oclass = &(struct nv50_clock_oclass) {
.base.handle = NV_SUBDEV(CLOCK, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
.domains = nv84_domains,
}.base;

327
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c Normal file
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@@ -0,0 +1,327 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
#include "nva3.h"
struct nva3_clock_priv {
struct nouveau_clock base;
struct nva3_clock_info eng[nv_clk_src_max];
};
static u32 read_clk(struct nva3_clock_priv *, int, bool);
static u32 read_pll(struct nva3_clock_priv *, int, u32);
static u32
read_vco(struct nva3_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
if ((sctl & 0x00000030) != 0x00000030)
return read_pll(priv, 0x41, 0x00e820);
return read_pll(priv, 0x42, 0x00e8a0);
}
static u32
read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
{
u32 sctl, sdiv, sclk;
/* refclk for the 0xe8xx plls is a fixed frequency */
if (clk >= 0x40) {
if (nv_device(priv)->chipset == 0xaf) {
/* no joke.. seriously.. sigh.. */
return nv_rd32(priv, 0x00471c) * 1000;
}
return nv_device(priv)->crystal;
}
sctl = nv_rd32(priv, 0x4120 + (clk * 4));
if (!ignore_en && !(sctl & 0x00000100))
return 0;
switch (sctl & 0x00003000) {
case 0x00000000:
return nv_device(priv)->crystal;
case 0x00002000:
if (sctl & 0x00000040)
return 108000;
return 100000;
case 0x00003000:
sclk = read_vco(priv, clk);
sdiv = ((sctl & 0x003f0000) >> 16) + 2;
return (sclk * 2) / sdiv;
default:
return 0;
}
}
static u32
read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
if (!(ctrl & 0x00000008)) {
if (ctrl & 0x00000001) {
u32 coef = nv_rd32(priv, pll + 4);
M = (coef & 0x000000ff) >> 0;
N = (coef & 0x0000ff00) >> 8;
P = (coef & 0x003f0000) >> 16;
/* no post-divider on these.. */
if ((pll & 0x00ff00) == 0x00e800)
P = 1;
sclk = read_clk(priv, 0x00 + clk, false);
}
} else {
sclk = read_clk(priv, 0x10 + clk, false);
}
if (M * P)
return sclk * N / (M * P);
return 0;
}
static int
nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nva3_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_core:
return read_pll(priv, 0x00, 0x4200);
case nv_clk_src_shader:
return read_pll(priv, 0x01, 0x4220);
case nv_clk_src_mem:
return read_pll(priv, 0x02, 0x4000);
case nv_clk_src_disp:
return read_clk(priv, 0x20, false);
case nv_clk_src_vdec:
return read_clk(priv, 0x21, false);
case nv_clk_src_daemon:
return read_clk(priv, 0x25, false);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
int
nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
struct nva3_clock_info *info)
{
struct nouveau_bios *bios = nouveau_bios(clock);
struct nva3_clock_priv *priv = (void *)clock;
struct nvbios_pll limits;
u32 oclk, sclk, sdiv;
int P, N, M, diff;
int ret;
info->pll = 0;
info->clk = 0;
switch (khz) {
case 27000:
info->clk = 0x00000100;
return khz;
case 100000:
info->clk = 0x00002100;
return khz;
case 108000:
info->clk = 0x00002140;
return khz;
default:
sclk = read_vco(priv, clk);
sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
/* if the clock has a PLL attached, and we can get a within
* [-2, 3) MHz of a divider, we'll disable the PLL and use
* the divider instead.
*
* divider can go as low as 2, limited here because NVIDIA
* and the VBIOS on my NVA8 seem to prefer using the PLL
* for 810MHz - is there a good reason?
*/
if (sdiv > 4) {
oclk = (sclk * 2) / sdiv;
diff = khz - oclk;
if (!pll || (diff >= -2000 && diff < 3000)) {
info->clk = (((sdiv - 2) << 16) | 0x00003100);
return oclk;
}
}
if (!pll)
return -ERANGE;
break;
}
ret = nvbios_pll_parse(bios, pll, &limits);
if (ret)
return ret;
limits.refclk = read_clk(priv, clk - 0x10, true);
if (!limits.refclk)
return -EINVAL;
ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
if (ret >= 0) {
info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
info->pll = (P << 16) | (N << 8) | M;
}
return ret ? ret : -ERANGE;
}
static int
calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
int clk, u32 pll, int idx)
{
int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
&priv->eng[idx]);
if (ret >= 0)
return 0;
return ret;
}
static void
prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
{
struct nva3_clock_info *info = &priv->eng[idx];
const u32 src0 = 0x004120 + (clk * 4);
const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0;
const u32 coef = pll + 4;
if (info->pll) {
nv_mask(priv, src0, 0x00000101, 0x00000101);
nv_wr32(priv, coef, info->pll);
nv_mask(priv, ctrl, 0x00000015, 0x00000015);
nv_mask(priv, ctrl, 0x00000010, 0x00000000);
nv_wait(priv, ctrl, 0x00020000, 0x00020000);
nv_mask(priv, ctrl, 0x00000010, 0x00000010);
nv_mask(priv, ctrl, 0x00000008, 0x00000000);
nv_mask(priv, src1, 0x00000100, 0x00000000);
nv_mask(priv, src1, 0x00000001, 0x00000000);
} else {
nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
nv_mask(priv, ctrl, 0x00000018, 0x00000018);
udelay(20);
nv_mask(priv, ctrl, 0x00000001, 0x00000000);
nv_mask(priv, src0, 0x00000100, 0x00000000);
nv_mask(priv, src0, 0x00000001, 0x00000000);
}
}
static void
prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
{
struct nva3_clock_info *info = &priv->eng[idx];
nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}
static int
nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nva3_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
return ret;
return 0;
}
static int
nva3_clock_prog(struct nouveau_clock *clk)
{
struct nva3_clock_priv *priv = (void *)clk;
prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
prog_clk(priv, 0x20, nv_clk_src_disp);
prog_clk(priv, 0x21, nv_clk_src_vdec);
return 0;
}
static void
nva3_clock_tidy(struct nouveau_clock *clk)
{
}
static struct nouveau_clocks
nva3_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0x03 },
{ nv_clk_src_disp , 0x04 },
{ nv_clk_src_max }
};
static int
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nva3_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, false,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nva3_clock_read;
priv->base.calc = nva3_clock_calc;
priv->base.prog = nva3_clock_prog;
priv->base.tidy = nva3_clock_tidy;
return 0;
}
struct nouveau_oclass
nva3_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

14
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h Normal file
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@@ -0,0 +1,14 @@
#ifndef __NVKM_CLK_NVA3_H__
#define __NVKM_CLK_NVA3_H__
#include <subdev/clock.h>
struct nva3_clock_info {
u32 clk;
u32 pll;
};
int nva3_clock_info(struct nouveau_clock *, int, u32, u32,
struct nva3_clock_info *);
#endif

446
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c Normal file
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@@ -0,0 +1,446 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include <subdev/clock.h>
#include "pll.h"
struct nvaa_clock_priv {
struct nouveau_clock base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, scoef;
u32 cpost, spost;
u32 vdiv;
};
static u32
read_div(struct nouveau_clock *clk)
{
return nv_rd32(clk, 0x004600);
}
static u32
read_pll(struct nouveau_clock *clk, u32 base)
{
u32 ctrl = nv_rd32(clk, base + 0);
u32 coef = nv_rd32(clk, base + 4);
u32 ref = clk->read(clk, nv_clk_src_href);
u32 post_div = 0;
u32 clock = 0;
int N1, M1;
switch (base){
case 0x4020:
post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16);
break;
case 0x4028:
post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16;
break;
default:
break;
}
N1 = (coef & 0x0000ff00) >> 8;
M1 = (coef & 0x000000ff);
if ((ctrl & 0x80000000) && M1) {
clock = ref * N1 / M1;
clock = clock / post_div;
}
return clock;
}
static int
nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nvaa_clock_priv *priv = (void *)clk;
u32 mast = nv_rd32(clk, 0x00c054);
u32 P = 0;
switch (src) {
case nv_clk_src_crystal:
return nv_device(priv)->crystal;
case nv_clk_src_href:
return 100000; /* PCIE reference clock */
case nv_clk_src_hclkm4:
return clk->read(clk, nv_clk_src_href) * 4;
case nv_clk_src_hclkm2d3:
return clk->read(clk, nv_clk_src_href) * 2 / 3;
case nv_clk_src_host:
switch (mast & 0x000c0000) {
case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3);
case 0x00040000: break;
case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4);
case 0x000c0000: return clk->read(clk, nv_clk_src_cclk);
}
break;
case nv_clk_src_core:
P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16;
switch (mast & 0x00000003) {
case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000001: return 0;
case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P;
case 0x00000003: return read_pll(clk, 0x004028) >> P;
}
break;
case nv_clk_src_cclk:
if ((mast & 0x03000000) != 0x03000000)
return clk->read(clk, nv_clk_src_core);
if ((mast & 0x00000200) == 0x00000000)
return clk->read(clk, nv_clk_src_core);
switch (mast & 0x00000c00) {
case 0x00000000: return clk->read(clk, nv_clk_src_href);
case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4);
case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3);
default: return 0;
}
case nv_clk_src_shader:
P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16;
switch (mast & 0x00000030) {
case 0x00000000:
if (mast & 0x00000040)
return clk->read(clk, nv_clk_src_href) >> P;
return clk->read(clk, nv_clk_src_crystal) >> P;
case 0x00000010: break;
case 0x00000020: return read_pll(clk, 0x004028) >> P;
case 0x00000030: return read_pll(clk, 0x004020) >> P;
}
break;
case nv_clk_src_mem:
return 0;
break;
case nv_clk_src_vdec:
P = (read_div(clk) & 0x00000700) >> 8;
switch (mast & 0x00400000) {
case 0x00400000:
return clk->read(clk, nv_clk_src_core) >> P;
break;
default:
return 500000 >> P;
break;
}
break;
default:
break;
}
nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
return 0;
}
static u32
calc_pll(struct nvaa_clock_priv *priv, u32 reg,
u32 clock, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
struct nouveau_clock *clk = &priv->base;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
if (ret)
return 0;
pll.vco2.max_freq = 0;
pll.refclk = clk->read(clk, nv_clk_src_href);
if (!pll.refclk)
return 0;
return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
}
static inline u32
calc_P(u32 src, u32 target, int *div)
{
u32 clk0 = src, clk1 = src;
for (*div = 0; *div <= 7; (*div)++) {
if (clk0 <= target) {
clk1 = clk0 << (*div ? 1 : 0);
break;
}
clk0 >>= 1;
}
if (target - clk0 <= clk1 - target)
return clk0;
(*div)--;
return clk1;
}
static int
nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nvaa_clock_priv *priv = (void *)clk;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
u32 out = 0, clock = 0;
int N, M, P1, P2 = 0;
int divs = 0;
/* cclk: find suitable source, disable PLL if we can */
if (core < clk->read(clk, nv_clk_src_hclkm4))
out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs);
/* Calculate clock * 2, so shader clock can use it too */
clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
if (abs(core - out) <=
abs(core - (clock >> 1))) {
priv->csrc = nv_clk_src_hclkm4;
priv->cctrl = divs << 16;
} else {
/* NVCTRL is actually used _after_ NVPOST, and after what we
* call NVPLL. To make matters worse, NVPOST is an integer
* divider instead of a right-shift number. */
if(P1 > 2) {
P2 = P1 - 2;
P1 = 2;
}
priv->csrc = nv_clk_src_core;
priv->ccoef = (N << 8) | M;
priv->cctrl = (P2 + 1) << 16;
priv->cpost = (1 << P1) << 16;
}
/* sclk: nvpll + divisor, href or spll */
out = 0;
if (shader == clk->read(clk, nv_clk_src_href)) {
priv->ssrc = nv_clk_src_href;
} else {
clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
if (priv->csrc == nv_clk_src_core) {
out = calc_P((core << 1), shader, &divs);
}
if (abs(shader - out) <=
abs(shader - clock) &&
(divs + P2) <= 7) {
priv->ssrc = nv_clk_src_core;
priv->sctrl = (divs + P2) << 16;
} else {
priv->ssrc = nv_clk_src_shader;
priv->scoef = (N << 8) | M;
priv->sctrl = P1 << 16;
}
}
/* vclk */
out = calc_P(core, vdec, &divs);
clock = calc_P(500000, vdec, &P1);
if(abs(vdec - out) <=
abs(vdec - clock)) {
priv->vsrc = nv_clk_src_cclk;
priv->vdiv = divs << 16;
} else {
priv->vsrc = nv_clk_src_vdec;
priv->vdiv = P1 << 16;
}
/* Print strategy! */
nv_debug(priv, "nvpll: %08x %08x %08x\n",
priv->ccoef, priv->cpost, priv->cctrl);
nv_debug(priv, " spll: %08x %08x %08x\n",
priv->scoef, priv->spost, priv->sctrl);
nv_debug(priv, " vdiv: %08x\n", priv->vdiv);
if (priv->csrc == nv_clk_src_hclkm4)
nv_debug(priv, "core: hrefm4\n");
else
nv_debug(priv, "core: nvpll\n");
if (priv->ssrc == nv_clk_src_hclkm4)
nv_debug(priv, "shader: hrefm4\n");
else if (priv->ssrc == nv_clk_src_core)
nv_debug(priv, "shader: nvpll\n");
else
nv_debug(priv, "shader: spll\n");
if (priv->vsrc == nv_clk_src_hclkm4)
nv_debug(priv, "vdec: 500MHz\n");
else
nv_debug(priv, "vdec: core\n");
return 0;
}
static int
nvaa_clock_prog(struct nouveau_clock *clk)
{
struct nvaa_clock_priv *priv = (void *)clk;
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
unsigned long flags;
u32 pllmask = 0, mast, ptherm_gate;
int ret = -EBUSY;
/* halt and idle execution engines */
ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
/* Wait until the interrupt handler is finished */
if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
goto resume;
if (pfifo)
pfifo->pause(pfifo, &flags);
if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
goto resume;
if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
goto resume;
/* First switch to safe clocks: href */
mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
mast &= ~0x00400e73;
mast |= 0x03000000;
switch (priv->csrc) {
case nv_clk_src_hclkm4:
nv_mask(clk, 0x4028, 0x00070000, priv->cctrl);
mast |= 0x00000002;
break;
case nv_clk_src_core:
nv_wr32(clk, 0x402c, priv->ccoef);
nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl);
nv_wr32(clk, 0x4040, priv->cpost);
pllmask |= (0x3 << 8);
mast |= 0x00000003;
break;
default:
nv_warn(priv,"Reclocking failed: unknown core clock\n");
goto resume;
}
switch (priv->ssrc) {
case nv_clk_src_href:
nv_mask(clk, 0x4020, 0x00070000, 0x00000000);
/* mast |= 0x00000000; */
break;
case nv_clk_src_core:
nv_mask(clk, 0x4020, 0x00070000, priv->sctrl);
mast |= 0x00000020;
break;
case nv_clk_src_shader:
nv_wr32(clk, 0x4024, priv->scoef);
nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl);
nv_wr32(clk, 0x4070, priv->spost);
pllmask |= (0x3 << 12);
mast |= 0x00000030;
break;
default:
nv_warn(priv,"Reclocking failed: unknown sclk clock\n");
goto resume;
}
if (!nv_wait(clk, 0x004080, pllmask, pllmask)) {
nv_warn(priv,"Reclocking failed: unstable PLLs\n");
goto resume;
}
switch (priv->vsrc) {
case nv_clk_src_cclk:
mast |= 0x00400000;
default:
nv_wr32(clk, 0x4600, priv->vdiv);
}
nv_wr32(clk, 0xc054, mast);
ret = 0;
resume:
if (pfifo)
pfifo->start(pfifo, &flags);
nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
nv_wr32(clk, 0x020060, ptherm_gate);
/* Disable some PLLs and dividers when unused */
if (priv->csrc != nv_clk_src_core) {
nv_wr32(clk, 0x4040, 0x00000000);
nv_mask(clk, 0x4028, 0x80000000, 0x00000000);
}
if (priv->ssrc != nv_clk_src_shader) {
nv_wr32(clk, 0x4070, 0x00000000);
nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
}
return ret;
}
static void
nvaa_clock_tidy(struct nouveau_clock *clk)
{
}
static struct nouveau_clocks
nvaa_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
{ nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
{ nv_clk_src_max }
};
static int
nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvaa_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, true,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nvaa_clock_read;
priv->base.calc = nvaa_clock_calc;
priv->base.prog = nvaa_clock_prog;
priv->base.tidy = nvaa_clock_tidy;
return 0;
}
struct nouveau_oclass *
nvaa_clock_oclass = &(struct nouveau_oclass) {
.handle = NV_SUBDEV(CLOCK, 0xaa),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvaa_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

462
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c Normal file
View File

@@ -0,0 +1,462 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
struct nvc0_clock_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct nvc0_clock_priv {
struct nouveau_clock base;
struct nvc0_clock_info eng[16];
};
static u32 read_div(struct nvc0_clock_priv *, int, u32, u32);
static u32
read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
{
struct nouveau_clock *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
return clk->read(clk, nv_clk_src_sppll1);
}
static u32
read_pll(struct nvc0_clock_priv *priv, u32 pll)
{
struct nouveau_clock *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
u32 N = (coef & 0x0000ff00) >> 8;
u32 M = (coef & 0x000000ff) >> 0;
u32 sclk;
if (!(ctrl & 0x00000001))
return 0;
switch (pll) {
case 0x00e800:
case 0x00e820:
sclk = nv_device(priv)->crystal;
P = 1;
break;
case 0x132000:
sclk = clk->read(clk, nv_clk_src_mpllsrc);
break;
case 0x132020:
sclk = clk->read(clk, nv_clk_src_mpllsrcref);
break;
case 0x137000:
case 0x137020:
case 0x137040:
case 0x1370e0:
sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
break;
default:
return 0;
}
return sclk * N / M / P;
}
static u32
read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
switch (ssrc & 0x00000003) {
case 0:
if ((ssrc & 0x00030000) != 0x00030000)
return nv_device(priv)->crystal;
return 108000;
case 2:
return 100000;
case 3:
if (sctl & 0x80000000) {
u32 sclk = read_vco(priv, dsrc + (doff * 4));
u32 sdiv = (sctl & 0x0000003f) + 2;
return (sclk * 2) / sdiv;
}
return read_vco(priv, dsrc + (doff * 4));
default:
return 0;
}
}
static u32
read_clk(struct nvc0_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
u32 sclk, sdiv;
if (ssel & (1 << clk)) {
if (clk < 7)
sclk = read_pll(priv, 0x137000 + (clk * 0x20));
else
sclk = read_pll(priv, 0x1370e0);
sdiv = ((sctl & 0x00003f00) >> 8) + 2;
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = ((sctl & 0x0000003f) >> 0) + 2;
}
if (sctl & 0x80000000)
return (sclk * 2) / sdiv;
return sclk;
}
static int
nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
struct nvc0_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return device->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_sppll0:
return read_pll(priv, 0x00e800);
case nv_clk_src_sppll1:
return read_pll(priv, 0x00e820);
case nv_clk_src_mpllsrcref:
return read_div(priv, 0, 0x137320, 0x137330);
case nv_clk_src_mpllsrc:
return read_pll(priv, 0x132020);
case nv_clk_src_mpll:
return read_pll(priv, 0x132000);
case nv_clk_src_mdiv:
return read_div(priv, 0, 0x137300, 0x137310);
case nv_clk_src_mem:
if (nv_rd32(priv, 0x1373f0) & 0x00000002)
return clk->read(clk, nv_clk_src_mpll);
return clk->read(clk, nv_clk_src_mdiv);
case nv_clk_src_gpc:
return read_clk(priv, 0x00);
case nv_clk_src_rop:
return read_clk(priv, 0x01);
case nv_clk_src_hubk07:
return read_clk(priv, 0x02);
case nv_clk_src_hubk06:
return read_clk(priv, 0x07);
case nv_clk_src_hubk01:
return read_clk(priv, 0x08);
case nv_clk_src_copy:
return read_clk(priv, 0x09);
case nv_clk_src_daemon:
return read_clk(priv, 0x0c);
case nv_clk_src_vdec:
return read_clk(priv, 0x0e);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static u32
calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
div = 2;
*ddiv = div - 2;
return (ref * 2) / div;
}
static u32
calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
/* use one of the fixed frequencies if possible */
*ddiv = 0x00000000;
switch (freq) {
case 27000:
case 108000:
*dsrc = 0x00000000;
if (freq == 108000)
*dsrc |= 0x00030000;
return freq;
case 100000:
*dsrc = 0x00000002;
return freq;
default:
*dsrc = 0x00000003;
break;
}
/* otherwise, calculate the closest divider */
sclk = read_vco(priv, 0x137160 + (clk * 4));
if (clk < 7)
sclk = calc_div(priv, clk, sclk, freq, ddiv);
return sclk;
}
static u32
calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
if (ret)
return 0;
limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
if (!limits.refclk)
return 0;
ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
*coef = (P << 16) | (N << 8) | M;
return ret;
}
static int
calc_clk(struct nvc0_clock_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
struct nvc0_clock_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
/* invalid clock domain */
if (!freq)
return 0;
/* first possible path, using only dividers */
clk0 = calc_src(priv, clk, freq, &src0, &div0);
clk0 = calc_div(priv, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk <= 7)
clk1 = calc_pll(priv, clk, freq, &info->coef);
else
clk1 = cstate->domain[nv_clk_src_hubk06];
clk1 = calc_div(priv, clk, clk1, freq, &div1P);
}
/* select the method which gets closest to target freq */
if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
info->dsrc = src0;
if (div0) {
info->ddiv |= 0x80000000;
info->ddiv |= div0 << 8;
info->ddiv |= div0;
}
if (div1D) {
info->mdiv |= 0x80000000;
info->mdiv |= div1D;
}
info->ssel = info->coef = 0;
info->freq = clk0;
} else {
if (div1P) {
info->mdiv |= 0x80000000;
info->mdiv |= div1P << 8;
}
info->ssel = (1 << clk);
info->freq = clk1;
}
return 0;
}
static int
nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nvc0_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
(ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
return ret;
return 0;
}
static void
nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
}
}
static void
nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
if (info->coef) {
nv_wr32(priv, addr + 0x04, info->coef);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
}
}
}
static void
nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
}
}
static void
nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk)
{
struct nvc0_clock_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
nvc0_clock_prog(struct nouveau_clock *clk)
{
struct nvc0_clock_priv *priv = (void *)clk;
struct {
void (*exec)(struct nvc0_clock_priv *, int);
} stage[] = {
{ nvc0_clock_prog_0 }, /* div programming */
{ nvc0_clock_prog_1 }, /* select div mode */
{ nvc0_clock_prog_2 }, /* (maybe) program pll */
{ nvc0_clock_prog_3 }, /* (maybe) select pll mode */
{ nvc0_clock_prog_4 }, /* final divider */
};
int i, j;
for (i = 0; i < ARRAY_SIZE(stage); i++) {
for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
if (!priv->eng[j].freq)
continue;
stage[i].exec(priv, j);
}
}
return 0;
}
static void
nvc0_clock_tidy(struct nouveau_clock *clk)
{
struct nvc0_clock_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
static struct nouveau_clocks
nvc0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_hubk06 , 0x00 },
{ nv_clk_src_hubk01 , 0x01 },
{ nv_clk_src_copy , 0x02 },
{ nv_clk_src_gpc , 0x03, 0, "core", 2000 },
{ nv_clk_src_rop , 0x04 },
{ nv_clk_src_mem , 0x05, 0, "memory", 1000 },
{ nv_clk_src_vdec , 0x06 },
{ nv_clk_src_daemon , 0x0a },
{ nv_clk_src_hubk07 , 0x0b },
{ nv_clk_src_max }
};
static int
nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, false,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nvc0_clock_read;
priv->base.calc = nvc0_clock_calc;
priv->base.prog = nvc0_clock_prog;
priv->base.tidy = nvc0_clock_tidy;
return 0;
}
struct nouveau_oclass
nvc0_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

498
drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c Normal file
View File

@@ -0,0 +1,498 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
struct nve0_clock_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct nve0_clock_priv {
struct nouveau_clock base;
struct nve0_clock_info eng[16];
};
static u32 read_div(struct nve0_clock_priv *, int, u32, u32);
static u32 read_pll(struct nve0_clock_priv *, u32);
static u32
read_vco(struct nve0_clock_priv *priv, u32 dsrc)
{
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return read_pll(priv, 0x00e800);
return read_pll(priv, 0x00e820);
}
static u32
read_pll(struct nve0_clock_priv *priv, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
u32 N = (coef & 0x0000ff00) >> 8;
u32 M = (coef & 0x000000ff) >> 0;
u32 sclk;
u16 fN = 0xf000;
if (!(ctrl & 0x00000001))
return 0;
switch (pll) {
case 0x00e800:
case 0x00e820:
sclk = nv_device(priv)->crystal;
P = 1;
break;
case 0x132000:
sclk = read_pll(priv, 0x132020);
P = (coef & 0x10000000) ? 2 : 1;
break;
case 0x132020:
sclk = read_div(priv, 0, 0x137320, 0x137330);
fN = nv_rd32(priv, pll + 0x10) >> 16;
break;
case 0x137000:
case 0x137020:
case 0x137040:
case 0x1370e0:
sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
break;
default:
return 0;
}
if (P == 0)
P = 1;
sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
return sclk / (M * P);
}
static u32
read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
switch (ssrc & 0x00000003) {
case 0:
if ((ssrc & 0x00030000) != 0x00030000)
return nv_device(priv)->crystal;
return 108000;
case 2:
return 100000;
case 3:
if (sctl & 0x80000000) {
u32 sclk = read_vco(priv, dsrc + (doff * 4));
u32 sdiv = (sctl & 0x0000003f) + 2;
return (sclk * 2) / sdiv;
}
return read_vco(priv, dsrc + (doff * 4));
default:
return 0;
}
}
static u32
read_mem(struct nve0_clock_priv *priv)
{
switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
case 1: return read_pll(priv, 0x132020);
case 2: return read_pll(priv, 0x132000);
default:
return 0;
}
}
static u32
read_clk(struct nve0_clock_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 sclk, sdiv;
if (clk < 7) {
u32 ssel = nv_rd32(priv, 0x137100);
if (ssel & (1 << clk)) {
sclk = read_pll(priv, 0x137000 + (clk * 0x20));
sdiv = 1;
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = 0;
}
} else {
u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04));
if ((ssrc & 0x00000003) == 0x00000003) {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
if (ssrc & 0x00000100) {
if (ssrc & 0x40000000)
sclk = read_pll(priv, 0x1370e0);
sdiv = 1;
} else {
sdiv = 0;
}
} else {
sclk = read_div(priv, clk, 0x137160, 0x1371d0);
sdiv = 0;
}
}
if (sctl & 0x80000000) {
if (sdiv)
sdiv = ((sctl & 0x00003f00) >> 8) + 2;
else
sdiv = ((sctl & 0x0000003f) >> 0) + 2;
return (sclk * 2) / sdiv;
}
return sclk;
}
static int
nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
struct nve0_clock_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
return device->crystal;
case nv_clk_src_href:
return 100000;
case nv_clk_src_mem:
return read_mem(priv);
case nv_clk_src_gpc:
return read_clk(priv, 0x00);
case nv_clk_src_rop:
return read_clk(priv, 0x01);
case nv_clk_src_hubk07:
return read_clk(priv, 0x02);
case nv_clk_src_hubk06:
return read_clk(priv, 0x07);
case nv_clk_src_hubk01:
return read_clk(priv, 0x08);
case nv_clk_src_daemon:
return read_clk(priv, 0x0c);
case nv_clk_src_vdec:
return read_clk(priv, 0x0e);
default:
nv_error(clk, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static u32
calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
div = 2;
*ddiv = div - 2;
return (ref * 2) / div;
}
static u32
calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
/* use one of the fixed frequencies if possible */
*ddiv = 0x00000000;
switch (freq) {
case 27000:
case 108000:
*dsrc = 0x00000000;
if (freq == 108000)
*dsrc |= 0x00030000;
return freq;
case 100000:
*dsrc = 0x00000002;
return freq;
default:
*dsrc = 0x00000003;
break;
}
/* otherwise, calculate the closest divider */
sclk = read_vco(priv, 0x137160 + (clk * 4));
if (clk < 7)
sclk = calc_div(priv, clk, sclk, freq, ddiv);
return sclk;
}
static u32
calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
if (ret)
return 0;
limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
if (!limits.refclk)
return 0;
ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
*coef = (P << 16) | (N << 8) | M;
return ret;
}
static int
calc_clk(struct nve0_clock_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
struct nve0_clock_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
/* invalid clock domain */
if (!freq)
return 0;
/* first possible path, using only dividers */
clk0 = calc_src(priv, clk, freq, &src0, &div0);
clk0 = calc_div(priv, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
if (clk0 != freq && (0x0000ff87 & (1 << clk))) {
if (clk <= 7)
clk1 = calc_pll(priv, clk, freq, &info->coef);
else
clk1 = cstate->domain[nv_clk_src_hubk06];
clk1 = calc_div(priv, clk, clk1, freq, &div1P);
}
/* select the method which gets closest to target freq */
if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
info->dsrc = src0;
if (div0) {
info->ddiv |= 0x80000000;
info->ddiv |= div0 << 8;
info->ddiv |= div0;
}
if (div1D) {
info->mdiv |= 0x80000000;
info->mdiv |= div1D;
}
info->ssel = 0;
info->freq = clk0;
} else {
if (div1P) {
info->mdiv |= 0x80000000;
info->mdiv |= div1P << 8;
}
info->ssel = (1 << clk);
info->dsrc = 0x40000100;
info->freq = clk1;
}
return 0;
}
static int
nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
struct nve0_clock_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
(ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
(ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
(ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
(ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
(ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
(ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
return ret;
return 0;
}
static void
nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (!info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
}
}
static void
nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk)
{
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
}
static void
nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
if (info->coef) {
nv_wr32(priv, addr + 0x04, info->coef);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
}
}
static void
nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static void
nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
}
}
static void
nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
{
struct nve0_clock_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
}
}
static int
nve0_clock_prog(struct nouveau_clock *clk)
{
struct nve0_clock_priv *priv = (void *)clk;
struct {
u32 mask;
void (*exec)(struct nve0_clock_priv *, int);
} stage[] = {
{ 0x007f, nve0_clock_prog_0 }, /* div programming */
{ 0x007f, nve0_clock_prog_1_0 }, /* select div mode */
{ 0xff80, nve0_clock_prog_1_1 },
{ 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */
{ 0xff80, nve0_clock_prog_3 }, /* final divider */
{ 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */
{ 0xff80, nve0_clock_prog_4_1 },
};
int i, j;
for (i = 0; i < ARRAY_SIZE(stage); i++) {
for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
if (!(stage[i].mask & (1 << j)))
continue;
if (!priv->eng[j].freq)
continue;
stage[i].exec(priv, j);
}
}
return 0;
}
static void
nve0_clock_tidy(struct nouveau_clock *clk)
{
struct nve0_clock_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
static struct nouveau_clocks
nve0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 },
{ nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_mem , 0x03, 0, "memory", 500 },
{ nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
{ nv_clk_src_hubk01 , 0x05 },
{ nv_clk_src_vdec , 0x06 },
{ nv_clk_src_daemon , 0x07 },
{ nv_clk_src_max }
};
static int
nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nve0_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, true,
&priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nve0_clock_read;
priv->base.calc = nve0_clock_calc;
priv->base.prog = nve0_clock_prog;
priv->base.tidy = nve0_clock_tidy;
return 0;
}
struct nouveau_oclass
nve0_clock_oclass = {
.handle = NV_SUBDEV(CLOCK, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_clock_ctor,
.dtor = _nouveau_clock_dtor,
.init = _nouveau_clock_init,
.fini = _nouveau_clock_fini,
},
};

9
drivers/gpu/drm/nouveau/core/subdev/clock/pll.h Normal file
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@@ -0,0 +1,9 @@
#ifndef __NOUVEAU_PLL_H__
#define __NOUVEAU_PLL_H__
int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P);
int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
int *N, int *fN, int *M, int *P);
#endif

246
drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c Normal file
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@@ -0,0 +1,246 @@
/*
* Copyright 1993-2003 NVIDIA, Corporation
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
static int
getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN, int *pM, int *pP)
{
/* Find M, N and P for a single stage PLL
*
* Note that some bioses (NV3x) have lookup tables of precomputed MNP
* values, but we're too lazy to use those atm
*
* "clk" parameter in kHz
* returns calculated clock
*/
struct nouveau_bios *bios = nouveau_bios(subdev);
int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
int minM = info->vco1.min_m, maxM = info->vco1.max_m;
int minN = info->vco1.min_n, maxN = info->vco1.max_n;
int minU = info->vco1.min_inputfreq;
int maxU = info->vco1.max_inputfreq;
int minP = info->min_p;
int maxP = info->max_p_usable;
int crystal = info->refclk;
int M, N, thisP, P;
int clkP, calcclk;
int delta, bestdelta = INT_MAX;
int bestclk = 0;
/* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
/* possibly correlated with introduction of 27MHz crystal */
if (bios->version.major < 0x60) {
int cv = bios->version.chip;
if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
if (clk > 250000)
maxM = 6;
if (clk > 340000)
maxM = 2;
} else if (cv < 0x40) {
if (clk > 150000)
maxM = 6;
if (clk > 200000)
maxM = 4;
if (clk > 340000)
maxM = 2;
}
}
P = 1 << maxP;
if ((clk * P) < minvco) {
minvco = clk * maxP;
maxvco = minvco * 2;
}
if (clk + clk/200 > maxvco) /* +0.5% */
maxvco = clk + clk/200;
/* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
for (thisP = minP; thisP <= maxP; thisP++) {
P = 1 << thisP;
clkP = clk * P;
if (clkP < minvco)
continue;
if (clkP > maxvco)
return bestclk;
for (M = minM; M <= maxM; M++) {
if (crystal/M < minU)
return bestclk;
if (crystal/M > maxU)
continue;
/* add crystal/2 to round better */
N = (clkP * M + crystal/2) / crystal;
if (N < minN)
continue;
if (N > maxN)
break;
/* more rounding additions */
calcclk = ((N * crystal + P/2) / P + M/2) / M;
delta = abs(calcclk - clk);
/* we do an exhaustive search rather than terminating
* on an optimality condition...
*/
if (delta < bestdelta) {
bestdelta = delta;
bestclk = calcclk;
*pN = N;
*pM = M;
*pP = thisP;
if (delta == 0) /* except this one */
return bestclk;
}
}
}
return bestclk;
}
static int
getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
{
/* Find M, N and P for a two stage PLL
*
* Note that some bioses (NV30+) have lookup tables of precomputed MNP
* values, but we're too lazy to use those atm
*
* "clk" parameter in kHz
* returns calculated clock
*/
int chip_version = nouveau_bios(subdev)->version.chip;
int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq;
int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m;
int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n;
int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m;
int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n;
int maxlog2P = info->max_p_usable;
int crystal = info->refclk;
bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
int M1, N1, M2, N2, log2P;
int clkP, calcclk1, calcclk2, calcclkout;
int delta, bestdelta = INT_MAX;
int bestclk = 0;
int vco2 = (maxvco2 - maxvco2/200) / 2;
for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++)
;
clkP = clk << log2P;
if (maxvco2 < clk + clk/200) /* +0.5% */
maxvco2 = clk + clk/200;
for (M1 = minM1; M1 <= maxM1; M1++) {
if (crystal/M1 < minU1)
return bestclk;
if (crystal/M1 > maxU1)
continue;
for (N1 = minN1; N1 <= maxN1; N1++) {
calcclk1 = crystal * N1 / M1;
if (calcclk1 < minvco1)
continue;
if (calcclk1 > maxvco1)
break;
for (M2 = minM2; M2 <= maxM2; M2++) {
if (calcclk1/M2 < minU2)
break;
if (calcclk1/M2 > maxU2)
continue;
/* add calcclk1/2 to round better */
N2 = (clkP * M2 + calcclk1/2) / calcclk1;
if (N2 < minN2)
continue;
if (N2 > maxN2)
break;
if (!fixedgain2) {
if (chip_version < 0x60)
if (N2/M2 < 4 || N2/M2 > 10)
continue;
calcclk2 = calcclk1 * N2 / M2;
if (calcclk2 < minvco2)
break;
if (calcclk2 > maxvco2)
continue;
} else
calcclk2 = calcclk1;
calcclkout = calcclk2 >> log2P;
delta = abs(calcclkout - clk);
/* we do an exhaustive search rather than terminating
* on an optimality condition...
*/
if (delta < bestdelta) {
bestdelta = delta;
bestclk = calcclkout;
*pN1 = N1;
*pM1 = M1;
*pN2 = N2;
*pM2 = M2;
*pP = log2P;
if (delta == 0) /* except this one */
return bestclk;
}
}
}
}
return bestclk;
}
int
nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P)
{
int ret;
if (!info->vco2.max_freq || !N2) {
ret = getMNP_single(subdev, info, freq, N1, M1, P);
if (N2) {
*N2 = 1;
*M2 = 1;
}
} else {
ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
}
if (!ret)
nv_error(subdev, "unable to compute acceptable pll values\n");
return ret;
}

89
drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c Normal file
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@@ -0,0 +1,89 @@
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
int
nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info,
u32 freq, int *pN, int *pfN, int *pM, int *P)
{
u32 best_err = ~0, err;
int M, lM, hM, N, fN;
*P = info->vco1.max_freq / freq;
if (*P > info->max_p)
*P = info->max_p;
if (*P < info->min_p)
*P = info->min_p;
lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq;
lM = max(lM, (int)info->vco1.min_m);
hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq;
hM = min(hM, (int)info->vco1.max_m);
lM = min(lM, hM);
for (M = lM; M <= hM; M++) {
u32 tmp = freq * *P * M;
N = tmp / info->refclk;
fN = tmp % info->refclk;
if (!pfN) {
if (fN >= info->refclk / 2)
N++;
} else {
if (fN < info->refclk / 2)
N--;
fN = tmp - (N * info->refclk);
}
if (N < info->vco1.min_n)
continue;
if (N > info->vco1.max_n)
break;
err = abs(freq - (info->refclk * N / M / *P));
if (err < best_err) {
best_err = err;
*pN = N;
*pM = M;
}
if (pfN) {
*pfN = ((fN << 13) + info->refclk / 2) / info->refclk;
*pfN = (*pfN - 4096) & 0xffff;
return freq;
}
}
if (unlikely(best_err == ~0)) {
nv_error(subdev, "unable to find matching pll values\n");
return -EINVAL;
}
return info->refclk * *pN / *pM / *P;
}

17
drivers/gpu/drm/nouveau/core/subdev/clock/seq.h Normal file
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#ifndef __NVKM_CLK_SEQ_H__
#define __NVKM_CLK_SEQ_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#define clk_init(s,p) hwsq_init(&(s)->base, (p))
#define clk_exec(s,e) hwsq_exec(&(s)->base, (e))
#define clk_have(s,r) ((s)->r_##r.addr != 0x000000)
#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r)
#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n))
#endif

101
drivers/gpu/drm/nouveau/core/subdev/devinit/base.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include <subdev/vga.h>
#include "priv.h"
int
_nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
{
struct nouveau_devinit *devinit = (void *)object;
/* force full reinit on resume */
if (suspend)
devinit->post = true;
/* unlock the extended vga crtc regs */
nv_lockvgac(devinit, false);
return nouveau_subdev_fini(&devinit->base, suspend);
}
int
_nouveau_devinit_init(struct nouveau_object *object)
{
struct nouveau_devinit_impl *impl = (void *)object->oclass;
struct nouveau_devinit *devinit = (void *)object;
int ret;
ret = nouveau_subdev_init(&devinit->base);
if (ret)
return ret;
ret = nvbios_init(&devinit->base, devinit->post);
if (ret)
return ret;
if (impl->disable)
nv_device(devinit)->disable_mask |= impl->disable(devinit);
return 0;
}
void
_nouveau_devinit_dtor(struct nouveau_object *object)
{
struct nouveau_devinit *devinit = (void *)object;
/* lock crtc regs */
nv_lockvgac(devinit, true);
nouveau_subdev_destroy(&devinit->base);
}
int
nouveau_devinit_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int size, void **pobject)
{
struct nouveau_devinit_impl *impl = (void *)oclass;
struct nouveau_device *device = nv_device(parent);
struct nouveau_devinit *devinit;
int ret;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
"init", size, pobject);
devinit = *pobject;
if (ret)
return ret;
devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false);
devinit->meminit = impl->meminit;
devinit->pll_set = impl->pll_set;
devinit->mmio = impl->mmio;
return 0;
}

100
drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <core/device.h>
#define NV04_PFB_BOOT_0 0x00100000
# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
#define NV04_PFB_DEBUG_0 0x00100080
# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001
# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010
# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00
# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000
# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000
# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000
# define NV04_PFB_DEBUG_0_CASOE 0x00100000
# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000
# define NV04_PFB_DEBUG_0_REFINC 0x20000000
# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000
#define NV04_PFB_CFG0 0x00100200
# define NV04_PFB_CFG0_SCRAMBLE 0x20000000
#define NV04_PFB_CFG1 0x00100204
#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))
#define NV10_PFB_REFCTRL 0x00100210
# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)
static inline struct io_mapping *
fbmem_init(struct nouveau_device *dev)
{
return io_mapping_create_wc(nv_device_resource_start(dev, 1),
nv_device_resource_len(dev, 1));
}
static inline void
fbmem_fini(struct io_mapping *fb)
{
io_mapping_free(fb);
}
static inline u32
fbmem_peek(struct io_mapping *fb, u32 off)
{
u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
u32 val = ioread32(p + (off & ~PAGE_MASK));
io_mapping_unmap_atomic(p);
return val;
}
static inline void
fbmem_poke(struct io_mapping *fb, u32 off, u32 val)
{
u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
iowrite32(val, p + (off & ~PAGE_MASK));
wmb();
io_mapping_unmap_atomic(p);
}
static inline bool
fbmem_readback(struct io_mapping *fb, u32 off, u32 val)
{
fbmem_poke(fb, off, val);
return val == fbmem_peek(fb, off);
}

56
drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c Normal file
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@@ -0,0 +1,56 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static u64
gm107_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r021c00 = nv_rd32(priv, 0x021c00);
u32 r021c04 = nv_rd32(priv, 0x021c04);
u64 disable = 0ULL;
if (r021c00 & 0x00000001)
disable |= (1ULL << NVDEV_ENGINE_COPY0);
if (r021c00 & 0x00000004)
disable |= (1ULL << NVDEV_ENGINE_COPY2);
if (r021c04 & 0x00000001)
disable |= (1ULL << NVDEV_ENGINE_DISP);
return disable;
}
struct nouveau_oclass *
gm107_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x07),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nvc0_devinit_pll_set,
.disable = gm107_devinit_disable,
}.base;

467
drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c Normal file
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@@ -0,0 +1,467 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <subdev/vga.h>
#include "fbmem.h"
#include "nv04.h"
static void
nv04_devinit_meminit(struct nouveau_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
u32 patt = 0xdeadbeef;
struct io_mapping *fb;
int i;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(priv));
if (!fb) {
nv_error(priv, "failed to map fb\n");
return;
}
/* Sequencer and refresh off */
nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
nv_mask(priv, NV04_PFB_BOOT_0, ~0,
NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
fbmem_poke(fb, 0x400000, patt + 1);
if (fbmem_peek(fb, 0) == patt + 1) {
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_TYPE,
NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
nv_mask(priv, NV04_PFB_DEBUG_0,
NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
} else
if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128 |
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
} else
if (fbmem_peek(fb, 0) != patt) {
if (fbmem_readback(fb, 0x800000, patt))
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
else
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
} else
if (!fbmem_readback(fb, 0x800000, patt)) {
nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
}
/* Refresh on, sequencer on */
nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
fbmem_fini(fb);
}
static int
powerctrl_1_shift(int chip_version, int reg)
{
int shift = -4;
if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
return shift;
switch (reg) {
case 0x680520:
shift += 4;
case 0x680508:
shift += 4;
case 0x680504:
shift += 4;
case 0x680500:
shift += 4;
}
/*
* the shift for vpll regs is only used for nv3x chips with a single
* stage pll
*/
if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
chip_version == 0x36 || chip_version >= 0x40))
shift = -4;
return shift;
}
void
setPLL_single(struct nouveau_devinit *devinit, u32 reg,
struct nouveau_pll_vals *pv)
{
int chip_version = nouveau_bios(devinit)->version.chip;
uint32_t oldpll = nv_rd32(devinit, reg);
int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
uint32_t saved_powerctrl_1 = 0;
int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
if (oldpll == pll)
return; /* already set */
if (shift_powerctrl_1 >= 0) {
saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
nv_wr32(devinit, 0x001584,
(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
1 << shift_powerctrl_1);
}
if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
/* upclock -- write new post divider first */
nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));
else
/* downclock -- write new NM first */
nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);
if ((chip_version < 0x17 || chip_version == 0x1a) &&
chip_version != 0x11)
/* wait a bit on older chips */
msleep(64);
nv_rd32(devinit, reg);
/* then write the other half as well */
nv_wr32(devinit, reg, pll);
if (shift_powerctrl_1 >= 0)
nv_wr32(devinit, 0x001584, saved_powerctrl_1);
}
static uint32_t
new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
{
bool head_a = (reg1 == 0x680508);
if (ss) /* single stage pll mode */
ramdac580 |= head_a ? 0x00000100 : 0x10000000;
else
ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
return ramdac580;
}
void
setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
struct nouveau_pll_vals *pv)
{
int chip_version = nouveau_bios(devinit)->version.chip;
bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
uint32_t oldpll1 = nv_rd32(devinit, reg1);
uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0;
uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
uint32_t oldramdac580 = 0, ramdac580 = 0;
bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
/* model specific additions to generic pll1 and pll2 set up above */
if (nv3035) {
pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
(pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
pll2 = 0;
}
if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
oldramdac580 = nv_rd32(devinit, 0x680580);
ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
if (oldramdac580 != ramdac580)
oldpll1 = ~0; /* force mismatch */
if (single_stage)
/* magic value used by nvidia in single stage mode */
pll2 |= 0x011f;
}
if (chip_version > 0x70)
/* magic bits set by the blob (but not the bios) on g71-73 */
pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
if (oldpll1 == pll1 && oldpll2 == pll2)
return; /* already set */
if (shift_powerctrl_1 >= 0) {
saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
nv_wr32(devinit, 0x001584,
(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
1 << shift_powerctrl_1);
}
if (chip_version >= 0x40) {
int shift_c040 = 14;
switch (reg1) {
case 0x680504:
shift_c040 += 2;
case 0x680500:
shift_c040 += 2;
case 0x680520:
shift_c040 += 2;
case 0x680508:
shift_c040 += 2;
}
savedc040 = nv_rd32(devinit, 0xc040);
if (shift_c040 != 14)
nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040));
}
if (oldramdac580 != ramdac580)
nv_wr32(devinit, 0x680580, ramdac580);
if (!nv3035)
nv_wr32(devinit, reg2, pll2);
nv_wr32(devinit, reg1, pll1);
if (shift_powerctrl_1 >= 0)
nv_wr32(devinit, 0x001584, saved_powerctrl_1);
if (chip_version >= 0x40)
nv_wr32(devinit, 0xc040, savedc040);
}
void
setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
struct nouveau_pll_vals *pv)
{
/* When setting PLLs, there is a merry game of disabling and enabling
* various bits of hardware during the process. This function is a
* synthesis of six nv4x traces, nearly each card doing a subtly
* different thing. With luck all the necessary bits for each card are
* combined herein. Without luck it deviates from each card's formula
* so as to not work on any :)
*/
uint32_t Preg = NMNMreg - 4;
bool mpll = Preg == 0x4020;
uint32_t oldPval = nv_rd32(devinit, Preg);
uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
0xc << 28 | pv->log2P << 16;
uint32_t saved4600 = 0;
/* some cards have different maskc040s */
uint32_t maskc040 = ~(3 << 14), savedc040;
bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
return;
if (Preg == 0x4000)
maskc040 = ~0x333;
if (Preg == 0x4058)
maskc040 = ~(0xc << 24);
if (mpll) {
struct nvbios_pll info;
uint8_t Pval2;
if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
return;
Pval2 = pv->log2P + info.bias_p;
if (Pval2 > info.max_p)
Pval2 = info.max_p;
Pval |= 1 << 28 | Pval2 << 20;
saved4600 = nv_rd32(devinit, 0x4600);
nv_wr32(devinit, 0x4600, saved4600 | 8 << 28);
}
if (single_stage)
Pval |= mpll ? 1 << 12 : 1 << 8;
nv_wr32(devinit, Preg, oldPval | 1 << 28);
nv_wr32(devinit, Preg, Pval & ~(4 << 28));
if (mpll) {
Pval |= 8 << 20;
nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28));
nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28));
}
savedc040 = nv_rd32(devinit, 0xc040);
nv_wr32(devinit, 0xc040, savedc040 & maskc040);
nv_wr32(devinit, NMNMreg, NMNM);
if (NMNMreg == 0x4024)
nv_wr32(devinit, 0x403c, NMNM);
nv_wr32(devinit, Preg, Pval);
if (mpll) {
Pval &= ~(8 << 20);
nv_wr32(devinit, 0x4020, Pval);
nv_wr32(devinit, 0x4038, Pval);
nv_wr32(devinit, 0x4600, saved4600);
}
nv_wr32(devinit, 0xc040, savedc040);
if (mpll) {
nv_wr32(devinit, 0x4020, Pval & ~(1 << 28));
nv_wr32(devinit, 0x4038, Pval & ~(1 << 28));
}
}
int
nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
{
struct nouveau_bios *bios = nouveau_bios(devinit);
struct nouveau_pll_vals pv;
struct nvbios_pll info;
int cv = bios->version.chip;
int N1, M1, N2, M2, P;
int ret;
ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
if (ret)
return ret;
ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
&N1, &M1, &N2, &M2, &P);
if (!ret)
return -EINVAL;
pv.refclk = info.refclk;
pv.N1 = N1;
pv.M1 = M1;
pv.N2 = N2;
pv.M2 = M2;
pv.log2P = P;
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
cv >= 0x40) {
if (type > 0x405c)
setPLL_double_highregs(devinit, type, &pv);
else
setPLL_double_lowregs(devinit, type, &pv);
} else
setPLL_single(devinit, type, &pv);
return 0;
}
int
nv04_devinit_fini(struct nouveau_object *object, bool suspend)
{
struct nv04_devinit_priv *priv = (void *)object;
int ret;
/* make i2c busses accessible */
nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
ret = nouveau_devinit_fini(&priv->base, suspend);
if (ret)
return ret;
/* unslave crtcs */
if (priv->owner < 0)
priv->owner = nv_rdvgaowner(priv);
nv_wrvgaowner(priv, 0);
return 0;
}
int
nv04_devinit_init(struct nouveau_object *object)
{
struct nv04_devinit_priv *priv = (void *)object;
if (!priv->base.post) {
u32 htotal = nv_rdvgac(priv, 0, 0x06);
htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
if (!htotal) {
nv_info(priv, "adaptor not initialised\n");
priv->base.post = true;
}
}
return nouveau_devinit_init(&priv->base);
}
void
nv04_devinit_dtor(struct nouveau_object *object)
{
struct nv04_devinit_priv *priv = (void *)object;
/* restore vga owner saved at first init */
nv_wrvgaowner(priv, priv->owner);
nouveau_devinit_destroy(&priv->base);
}
int
nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_devinit_priv *priv;
int ret;
ret = nouveau_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->owner = -1;
return 0;
}
struct nouveau_oclass *
nv04_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x04),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
.meminit = nv04_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
}.base;

23
drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h Normal file
View File

@@ -0,0 +1,23 @@
#ifndef __NVKM_DEVINIT_NV04_H__
#define __NVKM_DEVINIT_NV04_H__
#include "priv.h"
struct nv04_devinit_priv {
struct nouveau_devinit base;
u8 owner;
};
int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nv04_devinit_dtor(struct nouveau_object *);
int nv04_devinit_init(struct nouveau_object *);
int nv04_devinit_fini(struct nouveau_object *, bool);
int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32);
void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
#endif

139
drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c Normal file
View File

@@ -0,0 +1,139 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <subdev/bios.h>
#include <subdev/bios/bmp.h>
#include <subdev/vga.h>
#include "fbmem.h"
#include "nv04.h"
static void
nv05_devinit_meminit(struct nouveau_devinit *devinit)
{
static const u8 default_config_tab[][2] = {
{ 0x24, 0x00 },
{ 0x28, 0x00 },
{ 0x24, 0x01 },
{ 0x1f, 0x00 },
{ 0x0f, 0x00 },
{ 0x17, 0x00 },
{ 0x06, 0x00 },
{ 0x00, 0x00 }
};
struct nv04_devinit_priv *priv = (void *)devinit;
struct nouveau_bios *bios = nouveau_bios(priv);
struct io_mapping *fb;
u32 patt = 0xdeadbeef;
u16 data;
u8 strap, ramcfg[2];
int i, v;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(priv));
if (!fb) {
nv_error(priv, "failed to map fb\n");
return;
}
strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2;
if ((data = bmp_mem_init_table(bios))) {
ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
} else {
ramcfg[0] = default_config_tab[strap][0];
ramcfg[1] = default_config_tab[strap][1];
}
/* Sequencer off */
nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
goto out;
nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
/* If present load the hardcoded scrambling table */
if (data) {
for (i = 0, data += 0x10; i < 8; i++, data += 4) {
u32 scramble = nv_ro32(bios, data);
nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble);
}
}
/* Set memory type/width/length defaults depending on the straps */
nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
if (ramcfg[1] & 0x80)
nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
nv_mask(priv, NV04_PFB_CFG1, 0, 1);
/* Probe memory bus width */
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
if (fbmem_peek(fb, 0xc) != patt)
nv_mask(priv, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
/* Probe memory length */
v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
(!fbmem_readback(fb, 0x1000000, ++patt) ||
!fbmem_readback(fb, 0, ++patt)))
nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
!fbmem_readback(fb, 0x800000, ++patt))
nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
if (!fbmem_readback(fb, 0x400000, ++patt))
nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
out:
/* Sequencer on */
nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
fbmem_fini(fb);
}
struct nouveau_oclass *
nv05_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x05),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
.meminit = nv05_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
}.base;

110
drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c Normal file
View File

@@ -0,0 +1,110 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <subdev/vga.h>
#include "fbmem.h"
#include "nv04.h"
static void
nv10_devinit_meminit(struct nouveau_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
static const int mem_width[] = { 0x10, 0x00, 0x20 };
int mem_width_count;
uint32_t patt = 0xdeadbeef;
struct io_mapping *fb;
int i, j, k;
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17)
mem_width_count = 3;
else
mem_width_count = 2;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(priv));
if (!fb) {
nv_error(priv, "failed to map fb\n");
return;
}
nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Probe memory bus width */
for (i = 0; i < mem_width_count; i++) {
nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]);
for (j = 0; j < 4; j++) {
for (k = 0; k < 4; k++)
fbmem_poke(fb, 0x1c, 0);
fbmem_poke(fb, 0x1c, patt);
fbmem_poke(fb, 0x3c, 0);
if (fbmem_peek(fb, 0x1c) == patt)
goto mem_width_found;
}
}
mem_width_found:
patt <<= 1;
/* Probe amount of installed memory */
for (i = 0; i < 4; i++) {
int off = nv_rd32(priv, 0x10020c) - 0x100000;
fbmem_poke(fb, off, patt);
fbmem_poke(fb, 0, 0);
fbmem_peek(fb, 0);
fbmem_peek(fb, 0);
fbmem_peek(fb, 0);
fbmem_peek(fb, 0);
if (fbmem_peek(fb, off) == patt)
goto amount_found;
}
/* IC missing - disable the upper half memory space. */
nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0);
amount_found:
fbmem_fini(fb);
}
struct nouveau_oclass *
nv10_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x10),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
.meminit = nv10_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
}.base;

37
drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
struct nouveau_oclass *
nv1a_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x1a),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
.pll_set = nv04_devinit_pll_set,
}.base;

74
drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "fbmem.h"
static void
nv20_devinit_meminit(struct nouveau_devinit *devinit)
{
struct nv04_devinit_priv *priv = (void *)devinit;
struct nouveau_device *device = nv_device(priv);
uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
uint32_t amount, off;
struct io_mapping *fb;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(priv));
if (!fb) {
nv_error(priv, "failed to map fb\n");
return;
}
nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Allow full addressing */
nv_mask(priv, NV04_PFB_CFG0, 0, mask);
amount = nv_rd32(priv, 0x10020c);
for (off = amount; off > 0x2000000; off -= 0x2000000)
fbmem_poke(fb, off - 4, off);
amount = nv_rd32(priv, 0x10020c);
if (amount != fbmem_peek(fb, amount - 4))
/* IC missing - disable the upper half memory space. */
nv_mask(priv, NV04_PFB_CFG0, mask, 0);
fbmem_fini(fb);
}
struct nouveau_oclass *
nv20_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x20),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_devinit_ctor,
.dtor = nv04_devinit_dtor,
.init = nv04_devinit_init,
.fini = nv04_devinit_fini,
},
.meminit = nv20_devinit_meminit,
.pll_set = nv04_devinit_pll_set,
}.base;

163
drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c Normal file
View File

@@ -0,0 +1,163 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/vga.h>
#include "nv50.h"
int
nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll info;
int N1, M1, N2, M2, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
if (ret) {
nv_error(devinit, "failed to retrieve pll data, %d\n", ret);
return ret;
}
ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
if (!ret) {
nv_error(devinit, "failed pll calculation\n");
return ret;
}
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
nv_wr32(priv, info.reg + 0, 0x10000611);
nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
nv_mask(priv, info.reg + 8, 0x7fff00ff, (P << 28) |
(M2 << 16) | N2);
break;
case PLL_MEMORY:
nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
(info.bias_p << 19) |
(P << 16));
nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
break;
default:
nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
break;
}
return 0;
}
static u64
nv50_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000))
disable |= (1ULL << NVDEV_ENGINE_MPEG);
return disable;
}
int
nv50_devinit_init(struct nouveau_object *object)
{
struct nouveau_bios *bios = nouveau_bios(object);
struct nv50_devinit_priv *priv = (void *)object;
struct nvbios_outp info;
struct dcb_output outp;
u8 ver = 0xff, hdr, cnt, len;
int ret, i = 0;
if (!priv->base.post) {
if (!nv_rdvgac(priv, 0, 0x00) &&
!nv_rdvgac(priv, 0, 0x1a)) {
nv_info(priv, "adaptor not initialised\n");
priv->base.post = true;
}
}
ret = nouveau_devinit_init(&priv->base);
if (ret)
return ret;
/* if we ran the init tables, we have to execute the first script
* pointer of each dcb entry's display encoder table in order
* to properly initialise each encoder.
*/
while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
&ver, &hdr, &cnt, &len, &info)) {
struct nvbios_init init = {
.subdev = nv_subdev(priv),
.bios = bios,
.offset = info.script[0],
.outp = &outp,
.crtc = -1,
.execute = 1,
};
nvbios_exec(&init);
}
i++;
}
return 0;
}
int
nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_devinit_priv *priv;
int ret;
ret = nouveau_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
return 0;
}
struct nouveau_oclass *
nv50_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
.disable = nv50_devinit_disable,
}.base;

21
drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h Normal file
View File

@@ -0,0 +1,21 @@
#ifndef __NVKM_DEVINIT_NV50_H__
#define __NVKM_DEVINIT_NV50_H__
#include "priv.h"
struct nv50_devinit_priv {
struct nouveau_devinit base;
u32 r001540;
};
int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
int nv50_devinit_init(struct nouveau_object *);
int nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32);
int nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32);
int nvc0_devinit_pll_set(struct nouveau_devinit *, u32, u32);
#endif

63
drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c Normal file
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@@ -0,0 +1,63 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static u64
nv84_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
u32 r00154c = nv_rd32(priv, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_MPEG);
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_BSP);
disable |= (1ULL << NVDEV_ENGINE_CRYPT);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_CRYPT);
return disable;
}
struct nouveau_oclass *
nv84_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
.disable = nv84_devinit_disable,
}.base;

62
drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static u64
nv98_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
u32 r00154c = nv_rd32(priv, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_BSP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_CRYPT);
return disable;
}
struct nouveau_oclass *
nv98_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0x98),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nv50_devinit_pll_set,
.disable = nv98_devinit_disable,
}.base;

145
drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
int
nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
if (ret)
return ret;
ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
nv_wr32(priv, info.reg + 0, 0x50000610);
nv_mask(priv, info.reg + 4, 0x003fffff,
(P << 16) | (M << 8) | N);
nv_wr32(priv, info.reg + 8, fN);
break;
default:
nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
ret = -EINVAL;
break;
}
return ret;
}
static u64
nva3_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
u32 r00154c = nv_rd32(priv, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (!(r00154c & 0x00000200))
disable |= (1ULL << NVDEV_ENGINE_COPY0);
return disable;
}
static u32
nva3_devinit_mmio_part[] = {
0x100720, 0x1008bc, 4,
0x100a20, 0x100adc, 4,
0x100d80, 0x100ddc, 4,
0x110000, 0x110f9c, 4,
0x111000, 0x11103c, 8,
0x111080, 0x1110fc, 4,
0x111120, 0x1111fc, 4,
0x111300, 0x1114bc, 4,
0,
};
static u32
nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 *mmio = nva3_devinit_mmio_part;
/* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
* instructions which touch registers that may not even exist on
* some configurations (Quadro 400), which causes the register
* interface to screw up for some amount of time after attempting to
* write to one of these, and results in all sorts of things going
* horribly wrong.
*
* the binary driver avoids touching these registers at all, however,
* the video bios doesn't care and does what the scripts say. it's
* presumed that the io-port access to priv registers isn't effected
* by the screw-up bug mentioned above.
*
* really, a new opcode should've been invented to handle these
* requirements, but whatever, it's too late for that now.
*/
while (mmio[0]) {
if (addr >= mmio[0] && addr <= mmio[1]) {
u32 part = (addr / mmio[2]) & 7;
if (!priv->r001540)
priv->r001540 = nv_rd32(priv, 0x001540);
if (part >= hweight8((priv->r001540 >> 16) & 0xff))
return ~0;
return addr;
}
mmio += 3;
}
return addr;
}
struct nouveau_oclass *
nva3_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nva3_devinit_pll_set,
.disable = nva3_devinit_disable,
.mmio = nva3_devinit_mmio,
}.base;

63
drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static u64
nvaf_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r001540 = nv_rd32(priv, 0x001540);
u32 r00154c = nv_rd32(priv, 0x00154c);
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVDEV_ENGINE_VIC);
if (!(r00154c & 0x00000200))
disable |= (1ULL << NVDEV_ENGINE_COPY0);
return disable;
}
struct nouveau_oclass *
nvaf_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xaf),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nva3_devinit_pll_set,
.disable = nvaf_devinit_disable,
}.base;

118
drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
int
nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
{
struct nv50_devinit_priv *priv = (void *)devinit;
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll info;
int N, fN, M, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
if (ret)
return ret;
ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
case PLL_VPLL2:
case PLL_VPLL3:
nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
nv_wr32(priv, info.reg + 0x10, fN << 16);
break;
default:
nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
ret = -EINVAL;
break;
}
return ret;
}
static u64
nvc0_devinit_disable(struct nouveau_devinit *devinit)
{
struct nv50_devinit_priv *priv = (void *)devinit;
u32 r022500 = nv_rd32(priv, 0x022500);
u64 disable = 0ULL;
if (r022500 & 0x00000001)
disable |= (1ULL << NVDEV_ENGINE_DISP);
if (r022500 & 0x00000002) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
}
if (r022500 & 0x00000004)
disable |= (1ULL << NVDEV_ENGINE_BSP);
if (r022500 & 0x00000008)
disable |= (1ULL << NVDEV_ENGINE_VENC);
if (r022500 & 0x00000100)
disable |= (1ULL << NVDEV_ENGINE_COPY0);
if (r022500 & 0x00000200)
disable |= (1ULL << NVDEV_ENGINE_COPY1);
return disable;
}
static int
nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_devinit_priv *priv;
int ret;
ret = nouveau_devinit_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
if (nv_rd32(priv, 0x022500) & 0x00000001)
priv->base.post = true;
return 0;
}
struct nouveau_oclass *
nvc0_devinit_oclass = &(struct nouveau_devinit_impl) {
.base.handle = NV_SUBDEV(DEVINIT, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_devinit_ctor,
.dtor = _nouveau_devinit_dtor,
.init = nv50_devinit_init,
.fini = _nouveau_devinit_fini,
},
.pll_set = nvc0_devinit_pll_set,
.disable = nvc0_devinit_disable,
}.base;

38
drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h Normal file
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#ifndef __NVKM_DEVINIT_PRIV_H__
#define __NVKM_DEVINIT_PRIV_H__
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/clock/pll.h>
#include <subdev/devinit.h>
struct nouveau_devinit_impl {
struct nouveau_oclass base;
void (*meminit)(struct nouveau_devinit *);
int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
u64 (*disable)(struct nouveau_devinit *);
u32 (*mmio)(struct nouveau_devinit *, u32);
};
#define nouveau_devinit_create(p,e,o,d) \
nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_devinit_destroy(p) ({ \
struct nouveau_devinit *d = (p); \
_nouveau_devinit_dtor(nv_object(d)); \
})
#define nouveau_devinit_init(p) ({ \
struct nouveau_devinit *d = (p); \
_nouveau_devinit_init(nv_object(d)); \
})
#define nouveau_devinit_fini(p,s) ({ \
struct nouveau_devinit *d = (p); \
_nouveau_devinit_fini(nv_object(d), (s)); \
})
int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_devinit_dtor(struct nouveau_object *);
int _nouveau_devinit_init(struct nouveau_object *);
int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
#endif

166
drivers/gpu/drm/nouveau/core/subdev/fb/base.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include "priv.h"
int
nouveau_fb_bios_memtype(struct nouveau_bios *bios)
{
struct bit_entry M;
u8 ramcfg;
ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2;
if (!bit_entry(bios, 'M', &M) && M.version == 2 && M.length >= 5) {
u16 table = nv_ro16(bios, M.offset + 3);
u8 version = nv_ro08(bios, table + 0);
u8 header = nv_ro08(bios, table + 1);
u8 record = nv_ro08(bios, table + 2);
u8 entries = nv_ro08(bios, table + 3);
if (table && version == 0x10 && ramcfg < entries) {
u16 entry = table + header + (ramcfg * record);
switch (nv_ro08(bios, entry) & 0x0f) {
case 0: return NV_MEM_TYPE_DDR2;
case 1: return NV_MEM_TYPE_DDR3;
case 2: return NV_MEM_TYPE_GDDR3;
case 3: return NV_MEM_TYPE_GDDR5;
default:
break;
}
}
}
return NV_MEM_TYPE_UNKNOWN;
}
int
_nouveau_fb_fini(struct nouveau_object *object, bool suspend)
{
struct nouveau_fb *pfb = (void *)object;
int ret;
ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
if (ret && suspend)
return ret;
return nouveau_subdev_fini(&pfb->base, suspend);
}
int
_nouveau_fb_init(struct nouveau_object *object)
{
struct nouveau_fb *pfb = (void *)object;
int ret, i;
ret = nouveau_subdev_init(&pfb->base);
if (ret)
return ret;
ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
if (ret)
return ret;
for (i = 0; i < pfb->tile.regions; i++)
pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
return 0;
}
void
_nouveau_fb_dtor(struct nouveau_object *object)
{
struct nouveau_fb *pfb = (void *)object;
int i;
for (i = 0; i < pfb->tile.regions; i++)
pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
nouveau_mm_fini(&pfb->tags);
nouveau_mm_fini(&pfb->vram);
nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram);
nouveau_subdev_destroy(&pfb->base);
}
int
nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, int length, void **pobject)
{
struct nouveau_fb_impl *impl = (void *)oclass;
static const char *name[] = {
[NV_MEM_TYPE_UNKNOWN] = "unknown",
[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
[NV_MEM_TYPE_SGRAM ] = "SGRAM",
[NV_MEM_TYPE_SDRAM ] = "SDRAM",
[NV_MEM_TYPE_DDR1 ] = "DDR1",
[NV_MEM_TYPE_DDR2 ] = "DDR2",
[NV_MEM_TYPE_DDR3 ] = "DDR3",
[NV_MEM_TYPE_GDDR2 ] = "GDDR2",
[NV_MEM_TYPE_GDDR3 ] = "GDDR3",
[NV_MEM_TYPE_GDDR4 ] = "GDDR4",
[NV_MEM_TYPE_GDDR5 ] = "GDDR5",
};
struct nouveau_object *ram;
struct nouveau_fb *pfb;
int ret;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
length, pobject);
pfb = *pobject;
if (ret)
return ret;
pfb->memtype_valid = impl->memtype;
ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb),
impl->ram, NULL, 0, &ram);
if (ret) {
nv_fatal(pfb, "error detecting memory configuration!!\n");
return ret;
}
atomic_dec(&ram->parent->refcount);
atomic_dec(&ram->engine->refcount);
pfb->ram = (void *)ram;
if (!nouveau_mm_initialised(&pfb->vram)) {
ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
if (ret)
return ret;
}
if (!nouveau_mm_initialised(&pfb->tags)) {
ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ?
++pfb->ram->tags : 0, 1);
if (ret)
return ret;
}
nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]);
nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20));
nv_info(pfb, " ZCOMP: %d tags\n", pfb->ram->tags);
return 0;
}

122
drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <subdev/bios.h>
#include "priv.h"
/* binary driver only executes this path if the condition (a) is true
* for any configuration (combination of rammap+ramcfg+timing) that
* can be reached on a given card. for now, we will execute the branch
* unconditionally in the hope that a "false everywhere" in the bios
* tables doesn't actually mean "don't touch this".
*/
#define NOTE00(a) 1
int
nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
{
int pd, lf, xd, vh, vr, vo, l3;
int WL, CL, WR, at[2], dt, ds;
int rq = ram->freq < 1000000; /* XXX */
switch (ram->ramcfg.version) {
case 0x11:
pd = ram->next->bios.ramcfg_11_01_80;
lf = ram->next->bios.ramcfg_11_01_40;
xd = !ram->next->bios.ramcfg_11_01_20;
vh = ram->next->bios.ramcfg_11_02_10;
vr = ram->next->bios.ramcfg_11_02_04;
vo = ram->next->bios.ramcfg_11_06;
l3 = !ram->next->bios.ramcfg_11_07_02;
break;
default:
return -ENOSYS;
}
switch (ram->timing.version) {
case 0x20:
WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
CL = (ram->next->bios.timing[1] & 0x0000001f);
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
at[0] = ram->next->bios.timing_20_2e_c0;
at[1] = ram->next->bios.timing_20_2e_30;
dt = ram->next->bios.timing_20_2e_03;
ds = ram->next->bios.timing_20_2f_03;
break;
default:
return -ENOSYS;
}
if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)
return -EINVAL;
CL -= 5;
WR -= 4;
ram->mr[0] &= ~0xf7f;
ram->mr[0] |= (WR & 0x0f) << 8;
ram->mr[0] |= (CL & 0x0f) << 3;
ram->mr[0] |= (WL & 0x07) << 0;
ram->mr[1] &= ~0x0bf;
ram->mr[1] |= (xd & 0x01) << 7;
ram->mr[1] |= (at[0] & 0x03) << 4;
ram->mr[1] |= (dt & 0x03) << 2;
ram->mr[1] |= (ds & 0x03) << 0;
/* this seems wrong, alternate field used for the broadcast
* on nuts vs non-nuts configs.. meh, it matches for now.
*/
ram->mr1_nuts = ram->mr[1];
if (nuts) {
ram->mr[1] &= ~0x030;
ram->mr[1] |= (at[1] & 0x03) << 4;
}
ram->mr[3] &= ~0x020;
ram->mr[3] |= (rq & 0x01) << 5;
ram->mr[5] &= ~0x004;
ram->mr[5] |= (l3 << 2);
if (!vo)
vo = (ram->mr[6] & 0xff0) >> 4;
if (ram->mr[6] & 0x001)
pd = 1; /* binary driver does this.. bug? */
ram->mr[6] &= ~0xff1;
ram->mr[6] |= (vo & 0xff) << 4;
ram->mr[6] |= (pd & 0x01) << 0;
if (NOTE00(vr)) {
ram->mr[7] &= ~0x300;
ram->mr[7] |= (vr & 0x03) << 8;
}
ram->mr[7] &= ~0x088;
ram->mr[7] |= (vh & 0x01) << 7;
ram->mr[7] |= (lf & 0x01) << 3;
ram->mr[8] &= ~0x003;
ram->mr[8] |= (WR & 0x10) >> 3;
ram->mr[8] |= (CL & 0x10) >> 4;
return 0;
}

56
drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvc0.h"
struct gk20a_fb_priv {
struct nouveau_fb base;
};
static int
gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct gk20a_fb_priv *priv;
int ret;
ret = nouveau_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
return 0;
}
struct nouveau_oclass *
gk20a_fb_oclass = &(struct nouveau_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gk20a_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = _nouveau_fb_init,
.fini = _nouveau_fb_fini,
},
.memtype = nvc0_fb_memtype_valid,
.ram = &gk20a_ram_oclass,
}.base;

38
drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
struct nouveau_oclass *
gm107_fb_oclass = &(struct nouveau_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0x07),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_fb_ctor,
.dtor = nvc0_fb_dtor,
.init = nvc0_fb_init,
.fini = _nouveau_fb_fini,
},
.memtype = nvc0_fb_memtype_valid,
.ram = &gm107_ram_oclass,
}.base;

89
drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#define NV04_PFB_CFG0 0x00100200
bool
nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
{
if (!(tile_flags & 0xff00))
return true;
return false;
}
static int
nv04_fb_init(struct nouveau_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
* nvidia reading PFB_CFG_0, then writing back its original value.
* (which was 0x701114 in this case)
*/
nv_wr32(priv, NV04_PFB_CFG0, 0x1114);
return 0;
}
int
nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_fb_impl *impl = (void *)oclass;
struct nv04_fb_priv *priv;
int ret;
ret = nouveau_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.tile.regions = impl->tile.regions;
priv->base.tile.init = impl->tile.init;
priv->base.tile.comp = impl->tile.comp;
priv->base.tile.fini = impl->tile.fini;
priv->base.tile.prog = impl->tile.prog;
return 0;
}
struct nouveau_oclass *
nv04_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x04),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv04_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv04_ram_oclass,
}.base.base;

55
drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h Normal file
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#ifndef __NVKM_FB_NV04_H__
#define __NVKM_FB_NV04_H__
#include "priv.h"
struct nv04_fb_priv {
struct nouveau_fb base;
};
int nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
struct nv04_fb_impl {
struct nouveau_fb_impl base;
struct {
int regions;
void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nouveau_fb_tile *);
void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags,
struct nouveau_fb_tile *);
void (*fini)(struct nouveau_fb *, int i,
struct nouveau_fb_tile *);
void (*prog)(struct nouveau_fb *, int i,
struct nouveau_fb_tile *);
} tile;
};
void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nouveau_fb_tile *);
void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nouveau_fb_tile *);
void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
int nv30_fb_init(struct nouveau_object *);
void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nouveau_fb_tile *);
void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
struct nouveau_fb_tile *);
int nv41_fb_init(struct nouveau_object *);
void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
int nv44_fb_init(struct nouveau_object *);
void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nouveau_fb_tile *);
#endif

71
drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nouveau_fb_tile *tile)
{
tile->addr = 0x80000000 | addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
}
void
nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
tile->addr = 0;
tile->limit = 0;
tile->pitch = 0;
tile->zcomp = 0;
}
void
nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100240 + (i * 0x10));
}
struct nouveau_oclass *
nv10_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x10),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = _nouveau_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv10_ram_oclass,
.tile.regions = 8,
.tile.init = nv10_fb_tile_init,
.tile.fini = nv10_fb_tile_fini,
.tile.prog = nv10_fb_tile_prog,
}.base.base;

44
drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c Normal file
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@@ -0,0 +1,44 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
struct nouveau_oclass *
nv1a_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x1a),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = _nouveau_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv1a_ram_oclass,
.tile.regions = 8,
.tile.init = nv10_fb_tile_init,
.tile.fini = nv10_fb_tile_fini,
.tile.prog = nv10_fb_tile_prog,
}.base.base;

95
drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nouveau_fb_tile *tile)
{
tile->addr = 0x00000001 | addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
if (flags & 4) {
pfb->tile.comp(pfb, i, size, flags, tile);
tile->addr |= 2;
}
}
static void
nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
else tile->zcomp = 0x04000000; /* Z24S8 */
tile->zcomp |= tile->tag->offset;
tile->zcomp |= 0x80000000; /* enable */
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x08000000;
#endif
}
}
void
nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
tile->addr = 0;
tile->limit = 0;
tile->pitch = 0;
tile->zcomp = 0;
nouveau_mm_free(&pfb->tags, &tile->tag);
}
void
nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100240 + (i * 0x10));
nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
}
struct nouveau_oclass *
nv20_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x20),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = _nouveau_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
.tile.regions = 8,
.tile.init = nv20_fb_tile_init,
.tile.comp = nv20_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

61
drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
static void
nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
else tile->zcomp = 0x00200000; /* Z24S8 */
tile->zcomp |= tile->tag->offset;
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x01000000;
#endif
}
}
struct nouveau_oclass *
nv25_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x25),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = _nouveau_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
.tile.regions = 8,
.tile.init = nv20_fb_tile_init,
.tile.comp = nv25_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

139
drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nouveau_fb_tile *tile)
{
/* for performance, select alternate bank offset for zeta */
if (!(flags & 4)) {
tile->addr = (0 << 4);
} else {
if (pfb->tile.comp) /* z compression */
pfb->tile.comp(pfb, i, size, flags, tile);
tile->addr = (1 << 4);
}
tile->addr |= 0x00000001; /* enable */
tile->addr |= addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
}
static void
nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
else tile->zcomp |= 0x02000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12;
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x10000000;
#endif
}
}
static int
calc_bias(struct nv04_fb_priv *priv, int k, int i, int j)
{
struct nouveau_device *device = nv_device(priv);
int b = (device->chipset > 0x30 ?
nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
0) & 0xf;
return 2 * (b & 0x8 ? b - 0x10 : b);
}
static int
calc_ref(struct nv04_fb_priv *priv, int l, int k, int i)
{
int j, x = 0;
for (j = 0; j < 4; j++) {
int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j);
x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
}
return x;
}
int
nv30_fb_init(struct nouveau_object *object)
{
struct nouveau_device *device = nv_device(object);
struct nv04_fb_priv *priv = (void *)object;
int ret, i, j;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
/* Init the memory timing regs at 0x10037c/0x1003ac */
if (device->chipset == 0x30 ||
device->chipset == 0x31 ||
device->chipset == 0x35) {
/* Related to ROP count */
int n = (device->chipset == 0x31 ? 2 : 4);
int l = nv_rd32(priv, 0x1003d0);
for (i = 0; i < n; i++) {
for (j = 0; j < 3; j++)
nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j,
calc_ref(priv, l, 0, j));
for (j = 0; j < 2; j++)
nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j,
calc_ref(priv, l, 1, j));
}
}
return 0;
}
struct nouveau_oclass *
nv30_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x30),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv30_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv30_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

62
drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
static void
nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
else tile->zcomp |= 0x08000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13;
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x40000000;
#endif
}
}
struct nouveau_oclass *
nv35_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x35),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv30_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv35_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

62
drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
static void
nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x40);
u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
else tile->zcomp |= 0x20000000; /* Z24S8 */
tile->zcomp |= ((tile->tag->offset ) >> 6);
tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14;
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x80000000;
#endif
}
}
struct nouveau_oclass *
nv36_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x36),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv30_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv20_ram_oclass,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv36_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

76
drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
struct nouveau_fb_tile *tile)
{
u32 tiles = DIV_ROUND_UP(size, 0x80);
u32 tags = round_up(tiles / pfb->ram->parts, 0x100);
if ( (flags & 2) &&
!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */
tile->zcomp |= ((tile->tag->offset ) >> 8);
tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
#ifdef __BIG_ENDIAN
tile->zcomp |= 0x40000000;
#endif
}
}
static int
nv40_fb_init(struct nouveau_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
nv_mask(priv, 0x10033c, 0x00008000, 0x00000000);
return 0;
}
struct nouveau_oclass *
nv40_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x40),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv40_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv40_ram_oclass,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;

17
drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h Normal file
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#ifndef __NVKM_FB_NV40_H__
#define __NVKM_FB_NV40_H__
#include "priv.h"
struct nv40_ram {
struct nouveau_ram base;
u32 ctrl;
u32 coef;
};
int nv40_ram_calc(struct nouveau_fb *, u32);
int nv40_ram_prog(struct nouveau_fb *);
void nv40_ram_tidy(struct nouveau_fb *);
#endif

69
drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100600 + (i * 0x10));
nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
}
int
nv41_fb_init(struct nouveau_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
nv_wr32(priv, 0x100800, 0x00000001);
return 0;
}
struct nouveau_oclass *
nv41_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x41),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv41_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv41_ram_oclass,
.tile.regions = 12,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;

78
drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
static void
nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nouveau_fb_tile *tile)
{
tile->addr = 0x00000001; /* mode = vram */
tile->addr |= addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
}
void
nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
{
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100600 + (i * 0x10));
}
int
nv44_fb_init(struct nouveau_object *object)
{
struct nv04_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
nv_wr32(priv, 0x100850, 0x80000000);
nv_wr32(priv, 0x100800, 0x00000001);
return 0;
}
struct nouveau_oclass *
nv44_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x44),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv44_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv44_ram_oclass,
.tile.regions = 12,
.tile.init = nv44_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;

58
drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
void
nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nouveau_fb_tile *tile)
{
/* for performance, select alternate bank offset for zeta */
if (!(flags & 4)) tile->addr = (0 << 3);
else tile->addr = (1 << 3);
tile->addr |= 0x00000001; /* mode = vram */
tile->addr |= addr;
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
}
struct nouveau_oclass *
nv46_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x46),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv44_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv44_ram_oclass,
.tile.regions = 15,
.tile.init = nv46_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;

45
drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c Normal file
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@@ -0,0 +1,45 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
struct nouveau_oclass *
nv47_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x47),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv41_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv41_ram_oclass,
.tile.regions = 15,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;

45
drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c Normal file
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@@ -0,0 +1,45 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
struct nouveau_oclass *
nv49_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x49),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv41_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv49_ram_oclass,
.tile.regions = 15,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;

44
drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c Normal file
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@@ -0,0 +1,44 @@
/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
struct nouveau_oclass *
nv4e_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x4e),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nouveau_fb_dtor,
.init = nv44_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram = &nv4e_ram_oclass,
.tile.regions = 12,
.tile.init = nv46_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;

313
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/client.h>
#include <core/enum.h>
#include <core/engctx.h>
#include <core/object.h>
#include <subdev/bios.h>
#include "nv50.h"
int
nv50_fb_memtype[0x80] = {
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
};
bool
nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
{
return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
}
static const struct nouveau_enum vm_dispatch_subclients[] = {
{ 0x00000000, "GRCTX", NULL },
{ 0x00000001, "NOTIFY", NULL },
{ 0x00000002, "QUERY", NULL },
{ 0x00000003, "COND", NULL },
{ 0x00000004, "M2M_IN", NULL },
{ 0x00000005, "M2M_OUT", NULL },
{ 0x00000006, "M2M_NOTIFY", NULL },
{}
};
static const struct nouveau_enum vm_ccache_subclients[] = {
{ 0x00000000, "CB", NULL },
{ 0x00000001, "TIC", NULL },
{ 0x00000002, "TSC", NULL },
{}
};
static const struct nouveau_enum vm_prop_subclients[] = {
{ 0x00000000, "RT0", NULL },
{ 0x00000001, "RT1", NULL },
{ 0x00000002, "RT2", NULL },
{ 0x00000003, "RT3", NULL },
{ 0x00000004, "RT4", NULL },
{ 0x00000005, "RT5", NULL },
{ 0x00000006, "RT6", NULL },
{ 0x00000007, "RT7", NULL },
{ 0x00000008, "ZETA", NULL },
{ 0x00000009, "LOCAL", NULL },
{ 0x0000000a, "GLOBAL", NULL },
{ 0x0000000b, "STACK", NULL },
{ 0x0000000c, "DST2D", NULL },
{}
};
static const struct nouveau_enum vm_pfifo_subclients[] = {
{ 0x00000000, "PUSHBUF", NULL },
{ 0x00000001, "SEMAPHORE", NULL },
{}
};
static const struct nouveau_enum vm_bar_subclients[] = {
{ 0x00000000, "FB", NULL },
{ 0x00000001, "IN", NULL },
{}
};
static const struct nouveau_enum vm_client[] = {
{ 0x00000000, "STRMOUT", NULL },
{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
{ 0x00000004, "PFIFO_WRITE", NULL },
{ 0x00000005, "CCACHE", vm_ccache_subclients },
{ 0x00000006, "PPPP", NULL },
{ 0x00000007, "CLIPID", NULL },
{ 0x00000008, "PFIFO_READ", NULL },
{ 0x00000009, "VFETCH", NULL },
{ 0x0000000a, "TEXTURE", NULL },
{ 0x0000000b, "PROP", vm_prop_subclients },
{ 0x0000000c, "PVP", NULL },
{ 0x0000000d, "PBSP", NULL },
{ 0x0000000e, "PCRYPT", NULL },
{ 0x0000000f, "PCOUNTER", NULL },
{ 0x00000011, "PDAEMON", NULL },
{}
};
static const struct nouveau_enum vm_engine[] = {
{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x00000004, "PEEPHOLE", NULL },
{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
{ 0x00000006, "BAR", vm_bar_subclients },
{ 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
{ 0x0000000b, "PCOUNTER", NULL },
{ 0x0000000c, "SEMAPHORE_BG", NULL },
{ 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
{ 0x0000000e, "PDAEMON", NULL },
{}
};
static const struct nouveau_enum vm_fault[] = {
{ 0x00000000, "PT_NOT_PRESENT", NULL },
{ 0x00000001, "PT_TOO_SHORT", NULL },
{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
{ 0x00000004, "PAGE_READ_ONLY", NULL },
{ 0x00000006, "NULL_DMAOBJ", NULL },
{ 0x00000007, "WRONG_MEMTYPE", NULL },
{ 0x0000000b, "VRAM_LIMIT", NULL },
{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
{}
};
static void
nv50_fb_intr(struct nouveau_subdev *subdev)
{
struct nouveau_device *device = nv_device(subdev);
struct nouveau_engine *engine;
struct nv50_fb_priv *priv = (void *)subdev;
const struct nouveau_enum *en, *cl;
struct nouveau_object *engctx = NULL;
u32 trap[6], idx, chan;
u8 st0, st1, st2, st3;
int i;
idx = nv_rd32(priv, 0x100c90);
if (!(idx & 0x80000000))
return;
idx &= 0x00ffffff;
for (i = 0; i < 6; i++) {
nv_wr32(priv, 0x100c90, idx | i << 24);
trap[i] = nv_rd32(priv, 0x100c94);
}
nv_wr32(priv, 0x100c90, idx | 0x80000000);
/* decode status bits into something more useful */
if (device->chipset < 0xa3 ||
device->chipset == 0xaa || device->chipset == 0xac) {
st0 = (trap[0] & 0x0000000f) >> 0;
st1 = (trap[0] & 0x000000f0) >> 4;
st2 = (trap[0] & 0x00000f00) >> 8;
st3 = (trap[0] & 0x0000f000) >> 12;
} else {
st0 = (trap[0] & 0x000000ff) >> 0;
st1 = (trap[0] & 0x0000ff00) >> 8;
st2 = (trap[0] & 0x00ff0000) >> 16;
st3 = (trap[0] & 0xff000000) >> 24;
}
chan = (trap[2] << 16) | trap[1];
en = nouveau_enum_find(vm_engine, st0);
if (en && en->data2) {
const struct nouveau_enum *orig_en = en;
while (en->name && en->value == st0 && en->data2) {
engine = nouveau_engine(subdev, en->data2);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
break;
}
en++;
}
if (!engctx)
en = orig_en;
}
nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
(trap[5] & 0x00000100) ? "read" : "write",
trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
nouveau_client_name(engctx));
nouveau_engctx_put(engctx);
if (en)
pr_cont("%s/", en->name);
else
pr_cont("%02x/", st0);
cl = nouveau_enum_find(vm_client, st2);
if (cl)
pr_cont("%s/", cl->name);
else
pr_cont("%02x/", st2);
if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
else cl = NULL;
if (cl)
pr_cont("%s", cl->name);
else
pr_cont("%02x", st3);
pr_cont(" reason: ");
en = nouveau_enum_find(vm_fault, st1);
if (en)
pr_cont("%s\n", en->name);
else
pr_cont("0x%08x\n", st1);
}
int
nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
struct nv50_fb_priv *priv;
int ret;
ret = nouveau_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
if (priv->r100c08_page) {
priv->r100c08 = nv_device_map_page(device, priv->r100c08_page);
if (!priv->r100c08)
nv_warn(priv, "failed 0x100c08 page map\n");
} else {
nv_warn(priv, "failed 0x100c08 page alloc\n");
}
nv_subdev(priv)->intr = nv50_fb_intr;
return 0;
}
void
nv50_fb_dtor(struct nouveau_object *object)
{
struct nouveau_device *device = nv_device(object);
struct nv50_fb_priv *priv = (void *)object;
if (priv->r100c08_page) {
nv_device_unmap_page(device, priv->r100c08);
__free_page(priv->r100c08_page);
}
nouveau_fb_destroy(&priv->base);
}
int
nv50_fb_init(struct nouveau_object *object)
{
struct nv50_fb_impl *impl = (void *)object->oclass;
struct nv50_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
/* Not a clue what this is exactly. Without pointing it at a
* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
* cause IOMMU "read from address 0" errors (rh#561267)
*/
nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
/* This is needed to get meaningful information from 100c90
* on traps. No idea what these values mean exactly. */
nv_wr32(priv, 0x100c90, impl->trap);
return 0;
}
struct nouveau_oclass *
nv50_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x50),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nv50_ram_oclass,
.trap = 0x000707ff,
}.base.base;

33
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h Normal file
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#ifndef __NVKM_FB_NV50_H__
#define __NVKM_FB_NV50_H__
#include "priv.h"
struct nv50_fb_priv {
struct nouveau_fb base;
struct page *r100c08_page;
dma_addr_t r100c08;
};
int nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nv50_fb_dtor(struct nouveau_object *);
int nv50_fb_init(struct nouveau_object *);
struct nv50_fb_impl {
struct nouveau_fb_impl base;
u32 trap;
};
#define nv50_ram_create(p,e,o,d) \
nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d)
int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin,
u32 memtype, struct nouveau_mem **);
void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **);
void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *);
extern int nv50_fb_memtype[0x80];
#endif

39
drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
struct nouveau_oclass *
nv84_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x84),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nv50_ram_oclass,
.trap = 0x001d07ff,
}.base.base;

39
drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
struct nouveau_oclass *
nva3_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xa3),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nva3_ram_oclass,
.trap = 0x000d0fff,
}.base.base;

39
drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
struct nouveau_oclass *
nvaa_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaa),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nvaa_ram_oclass,
.trap = 0x001d07ff,
}.base.base;

39
drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
struct nouveau_oclass *
nvaf_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaf),
.base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nouveau_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram = &nvaa_ram_oclass,
.trap = 0x089d1fff,
}.base.base;

116
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c Normal file
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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
extern const u8 nvc0_pte_storage_type_map[256];
bool
nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
{
u8 memtype = (tile_flags & 0x0000ff00) >> 8;
return likely((nvc0_pte_storage_type_map[memtype] != 0xff));
}
static void
nvc0_fb_intr(struct nouveau_subdev *subdev)
{
struct nvc0_fb_priv *priv = (void *)subdev;
u32 intr = nv_rd32(priv, 0x000100);
if (intr & 0x08000000) {
nv_debug(priv, "PFFB intr\n");
intr &= ~0x08000000;
}
if (intr & 0x00002000) {
nv_debug(priv, "PBFB intr\n");
intr &= ~0x00002000;
}
}
int
nvc0_fb_init(struct nouveau_object *object)
{
struct nvc0_fb_priv *priv = (void *)object;
int ret;
ret = nouveau_fb_init(&priv->base);
if (ret)
return ret;
if (priv->r100c10_page)
nv_wr32(priv, 0x100c10, priv->r100c10 >> 8);
return 0;
}
void
nvc0_fb_dtor(struct nouveau_object *object)
{
struct nouveau_device *device = nv_device(object);
struct nvc0_fb_priv *priv = (void *)object;
if (priv->r100c10_page) {
nv_device_unmap_page(device, priv->r100c10);
__free_page(priv->r100c10_page);
}
nouveau_fb_destroy(&priv->base);
}
int
nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nv_device(parent);
struct nvc0_fb_priv *priv;
int ret;
ret = nouveau_fb_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
if (priv->r100c10_page) {
priv->r100c10 = nv_device_map_page(device, priv->r100c10_page);
if (!priv->r100c10)
return -EFAULT;
}
nv_subdev(priv)->intr = nvc0_fb_intr;
return 0;
}
struct nouveau_oclass *
nvc0_fb_oclass = &(struct nouveau_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_fb_ctor,
.dtor = nvc0_fb_dtor,
.init = nvc0_fb_init,
.fini = _nouveau_fb_fini,
},
.memtype = nvc0_fb_memtype_valid,
.ram = &nvc0_ram_oclass,
}.base;

31
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h Normal file
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#ifndef __NVKM_RAM_NVC0_H__
#define __NVKM_RAM_NVC0_H__
#include "priv.h"
#include "nv50.h"
struct nvc0_fb_priv {
struct nouveau_fb base;
struct page *r100c10_page;
dma_addr_t r100c10;
};
int nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nvc0_fb_dtor(struct nouveau_object *);
int nvc0_fb_init(struct nouveau_object *);
bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32);
#define nvc0_ram_create(p,e,o,m,d) \
nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
int nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, u32, int, void **);
int nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32,
struct nouveau_mem **);
void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **);
int nve0_ram_init(struct nouveau_object*);
#endif

38
drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c Normal file
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@@ -0,0 +1,38 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
struct nouveau_oclass *
nve0_fb_oclass = &(struct nouveau_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xe0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_fb_ctor,
.dtor = nvc0_fb_dtor,
.init = nvc0_fb_init,
.fini = _nouveau_fb_fini,
},
.memtype = nvc0_fb_memtype_valid,
.ram = &nve0_ram_oclass,
}.base;

74
drivers/gpu/drm/nouveau/core/subdev/fb/priv.h Normal file
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#ifndef __NVKM_FB_PRIV_H__
#define __NVKM_FB_PRIV_H__
#include <subdev/fb.h>
#define nouveau_ram_create(p,e,o,d) \
nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d)
#define nouveau_ram_destroy(p) \
nouveau_object_destroy(&(p)->base)
#define nouveau_ram_init(p) \
nouveau_object_init(&(p)->base)
#define nouveau_ram_fini(p,s) \
nouveau_object_fini(&(p)->base, (s))
#define nouveau_ram_create_(p,e,o,s,d) \
nouveau_object_create_((p), (e), (o), 0, (s), (void **)d)
#define _nouveau_ram_dtor nouveau_object_destroy
#define _nouveau_ram_init nouveau_object_init
#define _nouveau_ram_fini nouveau_object_fini
extern struct nouveau_oclass nv04_ram_oclass;
extern struct nouveau_oclass nv10_ram_oclass;
extern struct nouveau_oclass nv1a_ram_oclass;
extern struct nouveau_oclass nv20_ram_oclass;
extern struct nouveau_oclass nv40_ram_oclass;
extern struct nouveau_oclass nv41_ram_oclass;
extern struct nouveau_oclass nv44_ram_oclass;
extern struct nouveau_oclass nv49_ram_oclass;
extern struct nouveau_oclass nv4e_ram_oclass;
extern struct nouveau_oclass nv50_ram_oclass;
extern struct nouveau_oclass nva3_ram_oclass;
extern struct nouveau_oclass nvaa_ram_oclass;
extern struct nouveau_oclass nvc0_ram_oclass;
extern struct nouveau_oclass nve0_ram_oclass;
extern struct nouveau_oclass gk20a_ram_oclass;
extern struct nouveau_oclass gm107_ram_oclass;
int nouveau_sddr3_calc(struct nouveau_ram *ram);
int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts);
#define nouveau_fb_create(p,e,c,d) \
nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
#define nouveau_fb_destroy(p) ({ \
struct nouveau_fb *pfb = (p); \
_nouveau_fb_dtor(nv_object(pfb)); \
})
#define nouveau_fb_init(p) ({ \
struct nouveau_fb *pfb = (p); \
_nouveau_fb_init(nv_object(pfb)); \
})
#define nouveau_fb_fini(p,s) ({ \
struct nouveau_fb *pfb = (p); \
_nouveau_fb_fini(nv_object(pfb), (s)); \
})
int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_fb_dtor(struct nouveau_object *);
int _nouveau_fb_init(struct nouveau_object *);
int _nouveau_fb_fini(struct nouveau_object *, bool);
struct nouveau_fb_impl {
struct nouveau_oclass base;
struct nouveau_oclass *ram;
bool (*memtype)(struct nouveau_fb *, u32);
};
bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
struct nouveau_bios;
int nouveau_fb_bios_memtype(struct nouveau_bios *);
#endif

118
drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h Normal file
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#ifndef __NVKM_FBRAM_FUC_H__
#define __NVKM_FBRAM_FUC_H__
#include <subdev/pwr.h>
struct ramfuc {
struct nouveau_memx *memx;
struct nouveau_fb *pfb;
int sequence;
};
struct ramfuc_reg {
int sequence;
bool force;
u32 addr[2];
u32 data;
};
static inline struct ramfuc_reg
ramfuc_reg2(u32 addr1, u32 addr2)
{
return (struct ramfuc_reg) {
.sequence = 0,
.addr = { addr1, addr2 },
.data = 0xdeadbeef,
};
}
static noinline struct ramfuc_reg
ramfuc_reg(u32 addr)
{
return ramfuc_reg2(addr, addr);
}
static inline int
ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb)
{
struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
int ret;
ret = nouveau_memx_init(ppwr, &ram->memx);
if (ret)
return ret;
ram->sequence++;
ram->pfb = pfb;
return 0;
}
static inline int
ramfuc_exec(struct ramfuc *ram, bool exec)
{
int ret = 0;
if (ram->pfb) {
ret = nouveau_memx_fini(&ram->memx, exec);
ram->pfb = NULL;
}
return ret;
}
static inline u32
ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg)
{
if (reg->sequence != ram->sequence)
reg->data = nv_rd32(ram->pfb, reg->addr[0]);
return reg->data;
}
static inline void
ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data)
{
reg->sequence = ram->sequence;
reg->data = data;
if (reg->addr[0] != reg->addr[1])
nouveau_memx_wr32(ram->memx, reg->addr[1], reg->data);
nouveau_memx_wr32(ram->memx, reg->addr[0], reg->data);
}
static inline void
ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg)
{
reg->force = true;
}
static inline u32
ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data)
{
u32 temp = ramfuc_rd32(ram, reg);
if (temp != ((temp & ~mask) | data) || reg->force) {
ramfuc_wr32(ram, reg, (temp & ~mask) | data);
reg->force = false;
}
return temp;
}
static inline void
ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec)
{
nouveau_memx_wait(ram->memx, addr, mask, data, nsec);
}
static inline void
ramfuc_nsec(struct ramfuc *ram, u32 nsec)
{
nouveau_memx_nsec(ram->memx, nsec);
}
#define ram_init(s,p) ramfuc_init(&(s)->base, (p))
#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e))
#define ram_have(s,r) ((s)->r_##r.addr != 0x000000)
#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r)
#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r)
#define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d))
#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n))
#define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n))
#endif

152
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c Normal file
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/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/fb.h>
struct gk20a_mem {
struct nouveau_mem base;
void *cpuaddr;
dma_addr_t handle;
};
#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base)
static void
gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
{
struct device *dev = nv_device_base(nv_device(pfb));
struct gk20a_mem *mem = to_gk20a_mem(*pmem);
*pmem = NULL;
if (unlikely(mem == NULL))
return;
if (likely(mem->cpuaddr))
dma_free_coherent(dev, mem->base.size << PAGE_SHIFT,
mem->cpuaddr, mem->handle);
kfree(mem->base.pages);
kfree(mem);
}
static int
gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
u32 memtype, struct nouveau_mem **pmem)
{
struct device *dev = nv_device_base(nv_device(pfb));
struct gk20a_mem *mem;
u32 type = memtype & 0xff;
u32 npages, order;
int i;
nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size,
align, ncmin);
npages = size >> PAGE_SHIFT;
if (npages == 0)
npages = 1;
if (align == 0)
align = PAGE_SIZE;
align >>= PAGE_SHIFT;
/* round alignment to the next power of 2, if needed */
order = fls(align);
if ((align & (align - 1)) == 0)
order--;
align = BIT(order);
/* ensure returned address is correctly aligned */
npages = max(align, npages);
mem = kzalloc(sizeof(*mem), GFP_KERNEL);
if (!mem)
return -ENOMEM;
mem->base.size = npages;
mem->base.memtype = type;
mem->base.pages = kzalloc(sizeof(dma_addr_t) * npages, GFP_KERNEL);
if (!mem->base.pages) {
kfree(mem);
return -ENOMEM;
}
*pmem = &mem->base;
mem->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT,
&mem->handle, GFP_KERNEL);
if (!mem->cpuaddr) {
nv_error(pfb, "%s: cannot allocate memory!\n", __func__);
gk20a_ram_put(pfb, pmem);
return -ENOMEM;
}
align <<= PAGE_SHIFT;
/* alignment check */
if (unlikely(mem->handle & (align - 1)))
nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n",
&mem->handle, align);
nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n",
npages << PAGE_SHIFT, align, &mem->handle, mem->cpuaddr);
for (i = 0; i < npages; i++)
mem->base.pages[i] = mem->handle + (PAGE_SIZE * i);
mem->base.offset = (u64)mem->base.pages[0];
return 0;
}
static int
gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 datasize,
struct nouveau_object **pobject)
{
struct nouveau_ram *ram;
int ret;
ret = nouveau_ram_create(parent, engine, oclass, &ram);
*pobject = nv_object(ram);
if (ret)
return ret;
ram->type = NV_MEM_TYPE_STOLEN;
ram->size = get_num_physpages() << PAGE_SHIFT;
ram->get = gk20a_ram_get;
ram->put = gk20a_ram_put;
return 0;
}
struct nouveau_oclass
gk20a_ram_oclass = {
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gk20a_ram_ctor,
.dtor = _nouveau_ram_dtor,
.init = _nouveau_ram_init,
.fini = _nouveau_ram_fini,
},
};

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