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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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28
drivers/gpu/drm/i2c/Kconfig Normal file
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menu "I2C encoder or helper chips"
depends on DRM && DRM_KMS_HELPER && I2C
config DRM_I2C_CH7006
tristate "Chrontel ch7006 TV encoder"
default m if DRM_NOUVEAU
help
Support for Chrontel ch7006 and similar TV encoders, found
on some nVidia video cards.
This driver is currently only useful if you're also using
the nouveau driver.
config DRM_I2C_SIL164
tristate "Silicon Image sil164 TMDS transmitter"
default m if DRM_NOUVEAU
help
Support for sil164 and similar single-link (or dual-link
when used in pairs) TMDS transmitters, used in some nVidia
video cards.
config DRM_I2C_NXP_TDA998X
tristate "NXP Semiconductors TDA998X HDMI encoder"
default m if DRM_TILCDC
help
Support for NXP Semiconductors TDA998X HDMI encoders.
endmenu

10
drivers/gpu/drm/i2c/Makefile Normal file
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ccflags-y := -Iinclude/drm
ch7006-y := ch7006_drv.o ch7006_mode.o
obj-$(CONFIG_DRM_I2C_CH7006) += ch7006.o
sil164-y := sil164_drv.o
obj-$(CONFIG_DRM_I2C_SIL164) += sil164.o
tda998x-y := tda998x_drv.o
obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o

552
drivers/gpu/drm/i2c/ch7006_drv.c Normal file
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/*
* Copyright (C) 2009 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/module.h>
#include "ch7006_priv.h"
/* DRM encoder functions */
static void ch7006_encoder_set_config(struct drm_encoder *encoder,
void *params)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
priv->params = *(struct ch7006_encoder_params *)params;
}
static void ch7006_encoder_destroy(struct drm_encoder *encoder)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
drm_property_destroy(encoder->dev, priv->scale_property);
kfree(priv);
to_encoder_slave(encoder)->slave_priv = NULL;
drm_i2c_encoder_destroy(encoder);
}
static void ch7006_encoder_dpms(struct drm_encoder *encoder, int mode)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_state *state = &priv->state;
ch7006_dbg(client, "\n");
if (mode == priv->last_dpms)
return;
priv->last_dpms = mode;
ch7006_setup_power_state(encoder);
ch7006_load_reg(client, state, CH7006_POWER);
}
static void ch7006_encoder_save(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
ch7006_dbg(client, "\n");
ch7006_state_save(client, &priv->saved_state);
}
static void ch7006_encoder_restore(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
ch7006_dbg(client, "\n");
ch7006_state_load(client, &priv->saved_state);
}
static bool ch7006_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
/* The ch7006 is painfully picky with the input timings so no
* custom modes for now... */
priv->mode = ch7006_lookup_mode(encoder, mode);
return !!priv->mode;
}
static int ch7006_encoder_mode_valid(struct drm_encoder *encoder,
struct drm_display_mode *mode)
{
if (ch7006_lookup_mode(encoder, mode))
return MODE_OK;
else
return MODE_BAD;
}
static void ch7006_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *drm_mode,
struct drm_display_mode *adjusted_mode)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_encoder_params *params = &priv->params;
struct ch7006_state *state = &priv->state;
uint8_t *regs = state->regs;
struct ch7006_mode *mode = priv->mode;
struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
int start_active;
ch7006_dbg(client, "\n");
regs[CH7006_DISPMODE] = norm->dispmode | mode->dispmode;
regs[CH7006_BWIDTH] = 0;
regs[CH7006_INPUT_FORMAT] = bitf(CH7006_INPUT_FORMAT_FORMAT,
params->input_format);
regs[CH7006_CLKMODE] = CH7006_CLKMODE_SUBC_LOCK
| bitf(CH7006_CLKMODE_XCM, params->xcm)
| bitf(CH7006_CLKMODE_PCM, params->pcm);
if (params->clock_mode)
regs[CH7006_CLKMODE] |= CH7006_CLKMODE_MASTER;
if (params->clock_edge)
regs[CH7006_CLKMODE] |= CH7006_CLKMODE_POS_EDGE;
start_active = (drm_mode->htotal & ~0x7) - (drm_mode->hsync_start & ~0x7);
regs[CH7006_POV] = bitf(CH7006_POV_START_ACTIVE_8, start_active);
regs[CH7006_START_ACTIVE] = bitf(CH7006_START_ACTIVE_0, start_active);
regs[CH7006_INPUT_SYNC] = 0;
if (params->sync_direction)
regs[CH7006_INPUT_SYNC] |= CH7006_INPUT_SYNC_OUTPUT;
if (params->sync_encoding)
regs[CH7006_INPUT_SYNC] |= CH7006_INPUT_SYNC_EMBEDDED;
if (drm_mode->flags & DRM_MODE_FLAG_PVSYNC)
regs[CH7006_INPUT_SYNC] |= CH7006_INPUT_SYNC_PVSYNC;
if (drm_mode->flags & DRM_MODE_FLAG_PHSYNC)
regs[CH7006_INPUT_SYNC] |= CH7006_INPUT_SYNC_PHSYNC;
regs[CH7006_DETECT] = 0;
regs[CH7006_BCLKOUT] = 0;
regs[CH7006_SUBC_INC3] = 0;
if (params->pout_level)
regs[CH7006_SUBC_INC3] |= CH7006_SUBC_INC3_POUT_3_3V;
regs[CH7006_SUBC_INC4] = 0;
if (params->active_detect)
regs[CH7006_SUBC_INC4] |= CH7006_SUBC_INC4_DS_INPUT;
regs[CH7006_PLL_CONTROL] = priv->saved_state.regs[CH7006_PLL_CONTROL];
ch7006_setup_levels(encoder);
ch7006_setup_subcarrier(encoder);
ch7006_setup_pll(encoder);
ch7006_setup_power_state(encoder);
ch7006_setup_properties(encoder);
ch7006_state_load(client, state);
}
static enum drm_connector_status ch7006_encoder_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_state *state = &priv->state;
int det;
ch7006_dbg(client, "\n");
ch7006_save_reg(client, state, CH7006_DETECT);
ch7006_save_reg(client, state, CH7006_POWER);
ch7006_save_reg(client, state, CH7006_CLKMODE);
ch7006_write(client, CH7006_POWER, CH7006_POWER_RESET |
bitfs(CH7006_POWER_LEVEL, NORMAL));
ch7006_write(client, CH7006_CLKMODE, CH7006_CLKMODE_MASTER);
ch7006_write(client, CH7006_DETECT, CH7006_DETECT_SENSE);
ch7006_write(client, CH7006_DETECT, 0);
det = ch7006_read(client, CH7006_DETECT);
ch7006_load_reg(client, state, CH7006_CLKMODE);
ch7006_load_reg(client, state, CH7006_POWER);
ch7006_load_reg(client, state, CH7006_DETECT);
if ((det & (CH7006_DETECT_SVIDEO_Y_TEST|
CH7006_DETECT_SVIDEO_C_TEST|
CH7006_DETECT_CVBS_TEST)) == 0)
priv->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
else if ((det & (CH7006_DETECT_SVIDEO_Y_TEST|
CH7006_DETECT_SVIDEO_C_TEST)) == 0)
priv->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
else if ((det & CH7006_DETECT_CVBS_TEST) == 0)
priv->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
else
priv->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
drm_object_property_set_value(&connector->base,
encoder->dev->mode_config.tv_subconnector_property,
priv->subconnector);
return priv->subconnector ? connector_status_connected :
connector_status_disconnected;
}
static int ch7006_encoder_get_modes(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_mode *mode;
int n = 0;
for (mode = ch7006_modes; mode->mode.clock; mode++) {
if (~mode->valid_scales & 1<<priv->scale ||
~mode->valid_norms & 1<<priv->norm)
continue;
drm_mode_probed_add(connector,
drm_mode_duplicate(encoder->dev, &mode->mode));
n++;
}
return n;
}
static int ch7006_encoder_create_resources(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct drm_device *dev = encoder->dev;
struct drm_mode_config *conf = &dev->mode_config;
drm_mode_create_tv_properties(dev, NUM_TV_NORMS, ch7006_tv_norm_names);
priv->scale_property = drm_property_create_range(dev, 0, "scale", 0, 2);
drm_object_attach_property(&connector->base, conf->tv_select_subconnector_property,
priv->select_subconnector);
drm_object_attach_property(&connector->base, conf->tv_subconnector_property,
priv->subconnector);
drm_object_attach_property(&connector->base, conf->tv_left_margin_property,
priv->hmargin);
drm_object_attach_property(&connector->base, conf->tv_bottom_margin_property,
priv->vmargin);
drm_object_attach_property(&connector->base, conf->tv_mode_property,
priv->norm);
drm_object_attach_property(&connector->base, conf->tv_brightness_property,
priv->brightness);
drm_object_attach_property(&connector->base, conf->tv_contrast_property,
priv->contrast);
drm_object_attach_property(&connector->base, conf->tv_flicker_reduction_property,
priv->flicker);
drm_object_attach_property(&connector->base, priv->scale_property,
priv->scale);
return 0;
}
static int ch7006_encoder_set_property(struct drm_encoder *encoder,
struct drm_connector *connector,
struct drm_property *property,
uint64_t val)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_state *state = &priv->state;
struct drm_mode_config *conf = &encoder->dev->mode_config;
struct drm_crtc *crtc = encoder->crtc;
bool modes_changed = false;
ch7006_dbg(client, "\n");
if (property == conf->tv_select_subconnector_property) {
priv->select_subconnector = val;
ch7006_setup_power_state(encoder);
ch7006_load_reg(client, state, CH7006_POWER);
} else if (property == conf->tv_left_margin_property) {
priv->hmargin = val;
ch7006_setup_properties(encoder);
ch7006_load_reg(client, state, CH7006_POV);
ch7006_load_reg(client, state, CH7006_HPOS);
} else if (property == conf->tv_bottom_margin_property) {
priv->vmargin = val;
ch7006_setup_properties(encoder);
ch7006_load_reg(client, state, CH7006_POV);
ch7006_load_reg(client, state, CH7006_VPOS);
} else if (property == conf->tv_mode_property) {
if (connector->dpms != DRM_MODE_DPMS_OFF)
return -EINVAL;
priv->norm = val;
modes_changed = true;
} else if (property == conf->tv_brightness_property) {
priv->brightness = val;
ch7006_setup_levels(encoder);
ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);
} else if (property == conf->tv_contrast_property) {
priv->contrast = val;
ch7006_setup_properties(encoder);
ch7006_load_reg(client, state, CH7006_CONTRAST);
} else if (property == conf->tv_flicker_reduction_property) {
priv->flicker = val;
ch7006_setup_properties(encoder);
ch7006_load_reg(client, state, CH7006_FFILTER);
} else if (property == priv->scale_property) {
if (connector->dpms != DRM_MODE_DPMS_OFF)
return -EINVAL;
priv->scale = val;
modes_changed = true;
} else {
return -EINVAL;
}
if (modes_changed) {
drm_helper_probe_single_connector_modes(connector, 0, 0);
/* Disable the crtc to ensure a full modeset is
* performed whenever it's turned on again. */
if (crtc) {
struct drm_mode_set modeset = {
.crtc = crtc,
};
drm_mode_set_config_internal(&modeset);
}
}
return 0;
}
static struct drm_encoder_slave_funcs ch7006_encoder_funcs = {
.set_config = ch7006_encoder_set_config,
.destroy = ch7006_encoder_destroy,
.dpms = ch7006_encoder_dpms,
.save = ch7006_encoder_save,
.restore = ch7006_encoder_restore,
.mode_fixup = ch7006_encoder_mode_fixup,
.mode_valid = ch7006_encoder_mode_valid,
.mode_set = ch7006_encoder_mode_set,
.detect = ch7006_encoder_detect,
.get_modes = ch7006_encoder_get_modes,
.create_resources = ch7006_encoder_create_resources,
.set_property = ch7006_encoder_set_property,
};
/* I2C driver functions */
static int ch7006_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
uint8_t addr = CH7006_VERSION_ID;
uint8_t val;
int ret;
ch7006_dbg(client, "\n");
ret = i2c_master_send(client, &addr, sizeof(addr));
if (ret < 0)
goto fail;
ret = i2c_master_recv(client, &val, sizeof(val));
if (ret < 0)
goto fail;
ch7006_info(client, "Detected version ID: %x\n", val);
/* I don't know what this is for, but otherwise I get no
* signal.
*/
ch7006_write(client, 0x3d, 0x0);
return 0;
fail:
ch7006_err(client, "Error %d reading version ID\n", ret);
return -ENODEV;
}
static int ch7006_remove(struct i2c_client *client)
{
ch7006_dbg(client, "\n");
return 0;
}
static int ch7006_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
ch7006_dbg(client, "\n");
ch7006_write(client, 0x3d, 0x0);
return 0;
}
static int ch7006_encoder_init(struct i2c_client *client,
struct drm_device *dev,
struct drm_encoder_slave *encoder)
{
struct ch7006_priv *priv;
int i;
ch7006_dbg(client, "\n");
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
encoder->slave_priv = priv;
encoder->slave_funcs = &ch7006_encoder_funcs;
priv->norm = TV_NORM_PAL;
priv->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
priv->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
priv->scale = 1;
priv->contrast = 50;
priv->brightness = 50;
priv->flicker = 50;
priv->hmargin = 50;
priv->vmargin = 50;
priv->last_dpms = -1;
priv->chip_version = ch7006_read(client, CH7006_VERSION_ID);
if (ch7006_tv_norm) {
for (i = 0; i < NUM_TV_NORMS; i++) {
if (!strcmp(ch7006_tv_norm_names[i], ch7006_tv_norm)) {
priv->norm = i;
break;
}
}
if (i == NUM_TV_NORMS)
ch7006_err(client, "Invalid TV norm setting \"%s\".\n",
ch7006_tv_norm);
}
if (ch7006_scale >= 0 && ch7006_scale <= 2)
priv->scale = ch7006_scale;
else
ch7006_err(client, "Invalid scale setting \"%d\".\n",
ch7006_scale);
return 0;
}
static struct i2c_device_id ch7006_ids[] = {
{ "ch7006", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ch7006_ids);
static const struct dev_pm_ops ch7006_pm_ops = {
.resume = ch7006_resume,
};
static struct drm_i2c_encoder_driver ch7006_driver = {
.i2c_driver = {
.probe = ch7006_probe,
.remove = ch7006_remove,
.driver = {
.name = "ch7006",
.pm = &ch7006_pm_ops,
},
.id_table = ch7006_ids,
},
.encoder_init = ch7006_encoder_init,
};
/* Module initialization */
static int __init ch7006_init(void)
{
return drm_i2c_encoder_register(THIS_MODULE, &ch7006_driver);
}
static void __exit ch7006_exit(void)
{
drm_i2c_encoder_unregister(&ch7006_driver);
}
int ch7006_debug;
module_param_named(debug, ch7006_debug, int, 0600);
MODULE_PARM_DESC(debug, "Enable debug output.");
char *ch7006_tv_norm;
module_param_named(tv_norm, ch7006_tv_norm, charp, 0600);
MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, PAL-60, NTSC-M, NTSC-J.\n"
"\t\tDefault: PAL");
int ch7006_scale = 1;
module_param_named(scale, ch7006_scale, int, 0600);
MODULE_PARM_DESC(scale, "Default scale.\n"
"\t\tSupported: 0 -> Select video modes with a higher blanking ratio.\n"
"\t\t\t1 -> Select default video modes.\n"
"\t\t\t2 -> Select video modes with a lower blanking ratio.");
MODULE_AUTHOR("Francisco Jerez <currojerez@riseup.net>");
MODULE_DESCRIPTION("Chrontel ch7006 TV encoder driver");
MODULE_LICENSE("GPL and additional rights");
module_init(ch7006_init);
module_exit(ch7006_exit);

471
drivers/gpu/drm/i2c/ch7006_mode.c Normal file
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/*
* Copyright (C) 2009 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "ch7006_priv.h"
char *ch7006_tv_norm_names[] = {
[TV_NORM_PAL] = "PAL",
[TV_NORM_PAL_M] = "PAL-M",
[TV_NORM_PAL_N] = "PAL-N",
[TV_NORM_PAL_NC] = "PAL-Nc",
[TV_NORM_PAL_60] = "PAL-60",
[TV_NORM_NTSC_M] = "NTSC-M",
[TV_NORM_NTSC_J] = "NTSC-J",
};
#define NTSC_LIKE_TIMINGS .vrefresh = 60 * fixed1/1.001, \
.vdisplay = 480, \
.vtotal = 525, \
.hvirtual = 660
#define PAL_LIKE_TIMINGS .vrefresh = 50 * fixed1, \
.vdisplay = 576, \
.vtotal = 625, \
.hvirtual = 810
struct ch7006_tv_norm_info ch7006_tv_norms[] = {
[TV_NORM_NTSC_M] = {
NTSC_LIKE_TIMINGS,
.black_level = 0.339 * fixed1,
.subc_freq = 3579545 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC),
.voffset = 0,
},
[TV_NORM_NTSC_J] = {
NTSC_LIKE_TIMINGS,
.black_level = 0.286 * fixed1,
.subc_freq = 3579545 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC_J),
.voffset = 0,
},
[TV_NORM_PAL] = {
PAL_LIKE_TIMINGS,
.black_level = 0.3 * fixed1,
.subc_freq = 4433618.75 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
.voffset = 0,
},
[TV_NORM_PAL_M] = {
NTSC_LIKE_TIMINGS,
.black_level = 0.339 * fixed1,
.subc_freq = 3575611.433 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
.voffset = 16,
},
/* The following modes seem to work right but they're
* undocumented */
[TV_NORM_PAL_N] = {
PAL_LIKE_TIMINGS,
.black_level = 0.339 * fixed1,
.subc_freq = 4433618.75 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
.voffset = 0,
},
[TV_NORM_PAL_NC] = {
PAL_LIKE_TIMINGS,
.black_level = 0.3 * fixed1,
.subc_freq = 3582056.25 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
.voffset = 0,
},
[TV_NORM_PAL_60] = {
NTSC_LIKE_TIMINGS,
.black_level = 0.3 * fixed1,
.subc_freq = 4433618.75 * fixed1,
.dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
.voffset = 16,
},
};
#define __MODE(f, hd, vd, ht, vt, hsynp, vsynp, \
subc, scale, scale_mask, norm_mask, e_hd, e_vd) { \
.mode = { \
.name = #hd "x" #vd, \
.status = 0, \
.type = DRM_MODE_TYPE_DRIVER, \
.clock = f, \
.hdisplay = hd, \
.hsync_start = e_hd + 16, \
.hsync_end = e_hd + 80, \
.htotal = ht, \
.hskew = 0, \
.vdisplay = vd, \
.vsync_start = vd + 10, \
.vsync_end = vd + 26, \
.vtotal = vt, \
.vscan = 0, \
.flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
DRM_MODE_FLAG_##vsynp##VSYNC, \
.vrefresh = 0, \
}, \
.enc_hdisp = e_hd, \
.enc_vdisp = e_vd, \
.subc_coeff = subc * fixed1, \
.dispmode = bitfs(CH7006_DISPMODE_SCALING_RATIO, scale) | \
bitfs(CH7006_DISPMODE_INPUT_RES, e_hd##x##e_vd), \
.valid_scales = scale_mask, \
.valid_norms = norm_mask \
}
#define MODE(f, hd, vd, ht, vt, hsynp, vsynp, \
subc, scale, scale_mask, norm_mask) \
__MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale, \
scale_mask, norm_mask, hd, vd)
#define NTSC_LIKE (1 << TV_NORM_NTSC_M | 1 << TV_NORM_NTSC_J | \
1 << TV_NORM_PAL_M | 1 << TV_NORM_PAL_60)
#define PAL_LIKE (1 << TV_NORM_PAL | 1 << TV_NORM_PAL_N | 1 << TV_NORM_PAL_NC)
struct ch7006_mode ch7006_modes[] = {
MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),
MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),
MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),
MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),
MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),
MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),
MODE(31500, 640, 400, 1008, 625, N, N, 121.198371646, 1_1, 0x1, PAL_LIKE),
MODE(21147, 640, 400, 840, 420, N, N, 180.535097338, 5_4, 0x4, NTSC_LIKE),
MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),
MODE(30210, 640, 400, 840, 600, N, N, 126.374568276, 7_8, 0x1, NTSC_LIKE),
MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),
MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),
MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),
MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),
MODE(28196, 640, 480, 784, 600, N, N, 152.326488422, 7_8, 0x2, NTSC_LIKE),
MODE(30210, 640, 480, 800, 630, N, N, 142.171389101, 5_6, 0x1, NTSC_LIKE),
__MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),
MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),
MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),
MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),
MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),
{}
};
struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
const struct drm_display_mode *drm_mode)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_mode *mode;
for (mode = ch7006_modes; mode->mode.clock; mode++) {
if (~mode->valid_norms & 1<<priv->norm)
continue;
if (mode->mode.hdisplay != drm_mode->hdisplay ||
mode->mode.vdisplay != drm_mode->vdisplay ||
mode->mode.vtotal != drm_mode->vtotal ||
mode->mode.htotal != drm_mode->htotal ||
mode->mode.clock != drm_mode->clock)
continue;
return mode;
}
return NULL;
}
/* Some common HW state calculation code */
void ch7006_setup_levels(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
uint8_t *regs = priv->state.regs;
struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
int gain;
int black_level;
/* Set DAC_GAIN if the voltage drop between white and black is
* high enough. */
if (norm->black_level < 339*fixed1/1000) {
gain = 76;
regs[CH7006_INPUT_FORMAT] |= CH7006_INPUT_FORMAT_DAC_GAIN;
} else {
gain = 71;
regs[CH7006_INPUT_FORMAT] &= ~CH7006_INPUT_FORMAT_DAC_GAIN;
}
black_level = round_fixed(norm->black_level*26625)/gain;
/* Correct it with the specified brightness. */
black_level = interpolate(90, black_level, 208, priv->brightness);
regs[CH7006_BLACK_LEVEL] = bitf(CH7006_BLACK_LEVEL_0, black_level);
ch7006_dbg(client, "black level: %d\n", black_level);
}
void ch7006_setup_subcarrier(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_state *state = &priv->state;
struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
struct ch7006_mode *mode = priv->mode;
uint32_t subc_inc;
subc_inc = round_fixed((mode->subc_coeff >> 8)
* (norm->subc_freq >> 24));
setbitf(state, CH7006_SUBC_INC0, 28, subc_inc);
setbitf(state, CH7006_SUBC_INC1, 24, subc_inc);
setbitf(state, CH7006_SUBC_INC2, 20, subc_inc);
setbitf(state, CH7006_SUBC_INC3, 16, subc_inc);
setbitf(state, CH7006_SUBC_INC4, 12, subc_inc);
setbitf(state, CH7006_SUBC_INC5, 8, subc_inc);
setbitf(state, CH7006_SUBC_INC6, 4, subc_inc);
setbitf(state, CH7006_SUBC_INC7, 0, subc_inc);
ch7006_dbg(client, "subcarrier inc: %u\n", subc_inc);
}
void ch7006_setup_pll(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
uint8_t *regs = priv->state.regs;
struct ch7006_mode *mode = priv->mode;
int n, best_n = 0;
int m, best_m = 0;
int freq, best_freq = 0;
for (n = 0; n < CH7006_MAXN; n++) {
for (m = 0; m < CH7006_MAXM; m++) {
freq = CH7006_FREQ0*(n+2)/(m+2);
if (abs(freq - mode->mode.clock) <
abs(best_freq - mode->mode.clock)) {
best_freq = freq;
best_n = n;
best_m = m;
}
}
}
regs[CH7006_PLLOV] = bitf(CH7006_PLLOV_N_8, best_n) |
bitf(CH7006_PLLOV_M_8, best_m);
regs[CH7006_PLLM] = bitf(CH7006_PLLM_0, best_m);
regs[CH7006_PLLN] = bitf(CH7006_PLLN_0, best_n);
if (best_n < 108)
regs[CH7006_PLL_CONTROL] |= CH7006_PLL_CONTROL_CAPACITOR;
else
regs[CH7006_PLL_CONTROL] &= ~CH7006_PLL_CONTROL_CAPACITOR;
ch7006_dbg(client, "n=%d m=%d f=%d c=%d\n",
best_n, best_m, best_freq, best_n < 108);
}
void ch7006_setup_power_state(struct drm_encoder *encoder)
{
struct ch7006_priv *priv = to_ch7006_priv(encoder);
uint8_t *power = &priv->state.regs[CH7006_POWER];
int subconnector;
subconnector = priv->select_subconnector ? priv->select_subconnector :
priv->subconnector;
*power = CH7006_POWER_RESET;
if (priv->last_dpms == DRM_MODE_DPMS_ON) {
switch (subconnector) {
case DRM_MODE_SUBCONNECTOR_SVIDEO:
*power |= bitfs(CH7006_POWER_LEVEL, CVBS_OFF);
break;
case DRM_MODE_SUBCONNECTOR_Composite:
*power |= bitfs(CH7006_POWER_LEVEL, SVIDEO_OFF);
break;
case DRM_MODE_SUBCONNECTOR_SCART:
*power |= bitfs(CH7006_POWER_LEVEL, NORMAL) |
CH7006_POWER_SCART;
break;
}
} else {
if (priv->chip_version >= 0x20)
*power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF);
else
*power |= bitfs(CH7006_POWER_LEVEL, POWER_OFF);
}
}
void ch7006_setup_properties(struct drm_encoder *encoder)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
struct ch7006_priv *priv = to_ch7006_priv(encoder);
struct ch7006_state *state = &priv->state;
struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
struct ch7006_mode *ch_mode = priv->mode;
struct drm_display_mode *mode = &ch_mode->mode;
uint8_t *regs = state->regs;
int flicker, contrast, hpos, vpos;
uint64_t scale, aspect;
flicker = interpolate(0, 2, 3, priv->flicker);
regs[CH7006_FFILTER] = bitf(CH7006_FFILTER_TEXT, flicker) |
bitf(CH7006_FFILTER_LUMA, flicker) |
bitf(CH7006_FFILTER_CHROMA, 1);
contrast = interpolate(0, 5, 7, priv->contrast);
regs[CH7006_CONTRAST] = bitf(CH7006_CONTRAST_0, contrast);
scale = norm->vtotal*fixed1;
do_div(scale, mode->vtotal);
aspect = ch_mode->enc_hdisp*fixed1;
do_div(aspect, ch_mode->enc_vdisp);
hpos = round_fixed((norm->hvirtual * aspect - mode->hdisplay * scale)
* priv->hmargin * mode->vtotal) / norm->vtotal / 100 / 4;
setbitf(state, CH7006_POV, HPOS_8, hpos);
setbitf(state, CH7006_HPOS, 0, hpos);
vpos = max(0, norm->vdisplay - round_fixed(mode->vdisplay*scale)
+ norm->voffset) * priv->vmargin / 100 / 2;
setbitf(state, CH7006_POV, VPOS_8, vpos);
setbitf(state, CH7006_VPOS, 0, vpos);
ch7006_dbg(client, "hpos: %d, vpos: %d\n", hpos, vpos);
}
/* HW access functions */
void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)
{
uint8_t buf[] = {addr, val};
int ret;
ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
if (ret < 0)
ch7006_err(client, "Error %d writing to subaddress 0x%x\n",
ret, addr);
}
uint8_t ch7006_read(struct i2c_client *client, uint8_t addr)
{
uint8_t val;
int ret;
ret = i2c_master_send(client, &addr, sizeof(addr));
if (ret < 0)
goto fail;
ret = i2c_master_recv(client, &val, sizeof(val));
if (ret < 0)
goto fail;
return val;
fail:
ch7006_err(client, "Error %d reading from subaddress 0x%x\n",
ret, addr);
return 0;
}
void ch7006_state_load(struct i2c_client *client,
struct ch7006_state *state)
{
ch7006_load_reg(client, state, CH7006_POWER);
ch7006_load_reg(client, state, CH7006_DISPMODE);
ch7006_load_reg(client, state, CH7006_FFILTER);
ch7006_load_reg(client, state, CH7006_BWIDTH);
ch7006_load_reg(client, state, CH7006_INPUT_FORMAT);
ch7006_load_reg(client, state, CH7006_CLKMODE);
ch7006_load_reg(client, state, CH7006_START_ACTIVE);
ch7006_load_reg(client, state, CH7006_POV);
ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);
ch7006_load_reg(client, state, CH7006_HPOS);
ch7006_load_reg(client, state, CH7006_VPOS);
ch7006_load_reg(client, state, CH7006_INPUT_SYNC);
ch7006_load_reg(client, state, CH7006_DETECT);
ch7006_load_reg(client, state, CH7006_CONTRAST);
ch7006_load_reg(client, state, CH7006_PLLOV);
ch7006_load_reg(client, state, CH7006_PLLM);
ch7006_load_reg(client, state, CH7006_PLLN);
ch7006_load_reg(client, state, CH7006_BCLKOUT);
ch7006_load_reg(client, state, CH7006_SUBC_INC0);
ch7006_load_reg(client, state, CH7006_SUBC_INC1);
ch7006_load_reg(client, state, CH7006_SUBC_INC2);
ch7006_load_reg(client, state, CH7006_SUBC_INC3);
ch7006_load_reg(client, state, CH7006_SUBC_INC4);
ch7006_load_reg(client, state, CH7006_SUBC_INC5);
ch7006_load_reg(client, state, CH7006_SUBC_INC6);
ch7006_load_reg(client, state, CH7006_SUBC_INC7);
ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
}
void ch7006_state_save(struct i2c_client *client,
struct ch7006_state *state)
{
ch7006_save_reg(client, state, CH7006_POWER);
ch7006_save_reg(client, state, CH7006_DISPMODE);
ch7006_save_reg(client, state, CH7006_FFILTER);
ch7006_save_reg(client, state, CH7006_BWIDTH);
ch7006_save_reg(client, state, CH7006_INPUT_FORMAT);
ch7006_save_reg(client, state, CH7006_CLKMODE);
ch7006_save_reg(client, state, CH7006_START_ACTIVE);
ch7006_save_reg(client, state, CH7006_POV);
ch7006_save_reg(client, state, CH7006_BLACK_LEVEL);
ch7006_save_reg(client, state, CH7006_HPOS);
ch7006_save_reg(client, state, CH7006_VPOS);
ch7006_save_reg(client, state, CH7006_INPUT_SYNC);
ch7006_save_reg(client, state, CH7006_DETECT);
ch7006_save_reg(client, state, CH7006_CONTRAST);
ch7006_save_reg(client, state, CH7006_PLLOV);
ch7006_save_reg(client, state, CH7006_PLLM);
ch7006_save_reg(client, state, CH7006_PLLN);
ch7006_save_reg(client, state, CH7006_BCLKOUT);
ch7006_save_reg(client, state, CH7006_SUBC_INC0);
ch7006_save_reg(client, state, CH7006_SUBC_INC1);
ch7006_save_reg(client, state, CH7006_SUBC_INC2);
ch7006_save_reg(client, state, CH7006_SUBC_INC3);
ch7006_save_reg(client, state, CH7006_SUBC_INC4);
ch7006_save_reg(client, state, CH7006_SUBC_INC5);
ch7006_save_reg(client, state, CH7006_SUBC_INC6);
ch7006_save_reg(client, state, CH7006_SUBC_INC7);
ch7006_save_reg(client, state, CH7006_PLL_CONTROL);
ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0);
state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) |
(state->regs[CH7006_FFILTER] & 0x0c) >> 2 |
(state->regs[CH7006_FFILTER] & 0x03) << 2;
}

345
drivers/gpu/drm/i2c/ch7006_priv.h Normal file
View File

@@ -0,0 +1,345 @@
/*
* Copyright (C) 2009 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __DRM_I2C_CH7006_PRIV_H__
#define __DRM_I2C_CH7006_PRIV_H__
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder_slave.h>
#include <drm/i2c/ch7006.h>
typedef int64_t fixed;
#define fixed1 (1LL << 32)
enum ch7006_tv_norm {
TV_NORM_PAL,
TV_NORM_PAL_M,
TV_NORM_PAL_N,
TV_NORM_PAL_NC,
TV_NORM_PAL_60,
TV_NORM_NTSC_M,
TV_NORM_NTSC_J,
NUM_TV_NORMS
};
struct ch7006_tv_norm_info {
fixed vrefresh;
int vdisplay;
int vtotal;
int hvirtual;
fixed subc_freq;
fixed black_level;
uint32_t dispmode;
int voffset;
};
struct ch7006_mode {
struct drm_display_mode mode;
int enc_hdisp;
int enc_vdisp;
fixed subc_coeff;
uint32_t dispmode;
uint32_t valid_scales;
uint32_t valid_norms;
};
struct ch7006_state {
uint8_t regs[0x26];
};
struct ch7006_priv {
struct ch7006_encoder_params params;
struct ch7006_mode *mode;
struct ch7006_state state;
struct ch7006_state saved_state;
struct drm_property *scale_property;
int select_subconnector;
int subconnector;
int hmargin;
int vmargin;
enum ch7006_tv_norm norm;
int brightness;
int contrast;
int flicker;
int scale;
int chip_version;
int last_dpms;
};
#define to_ch7006_priv(x) \
((struct ch7006_priv *)to_encoder_slave(x)->slave_priv)
extern int ch7006_debug;
extern char *ch7006_tv_norm;
extern int ch7006_scale;
extern char *ch7006_tv_norm_names[];
extern struct ch7006_tv_norm_info ch7006_tv_norms[];
extern struct ch7006_mode ch7006_modes[];
struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
const struct drm_display_mode *drm_mode);
void ch7006_setup_levels(struct drm_encoder *encoder);
void ch7006_setup_subcarrier(struct drm_encoder *encoder);
void ch7006_setup_pll(struct drm_encoder *encoder);
void ch7006_setup_power_state(struct drm_encoder *encoder);
void ch7006_setup_properties(struct drm_encoder *encoder);
void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val);
uint8_t ch7006_read(struct i2c_client *client, uint8_t addr);
void ch7006_state_load(struct i2c_client *client,
struct ch7006_state *state);
void ch7006_state_save(struct i2c_client *client,
struct ch7006_state *state);
/* Some helper macros */
#define ch7006_dbg(client, format, ...) do { \
if (ch7006_debug) \
dev_printk(KERN_DEBUG, &client->dev, \
"%s: " format, __func__, ## __VA_ARGS__); \
} while (0)
#define ch7006_info(client, format, ...) \
dev_info(&client->dev, format, __VA_ARGS__)
#define ch7006_err(client, format, ...) \
dev_err(&client->dev, format, __VA_ARGS__)
#define __mask(src, bitfield) \
(((2 << (1 ? bitfield)) - 1) & ~((1 << (0 ? bitfield)) - 1))
#define mask(bitfield) __mask(bitfield)
#define __bitf(src, bitfield, x) \
(((x) >> (src) << (0 ? bitfield)) & __mask(src, bitfield))
#define bitf(bitfield, x) __bitf(bitfield, x)
#define bitfs(bitfield, s) __bitf(bitfield, bitfield##_##s)
#define setbitf(state, reg, bitfield, x) \
state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \
| bitf(reg##_##bitfield, x)
#define __unbitf(src, bitfield, x) \
((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src))
#define unbitf(bitfield, x) __unbitf(bitfield, x)
static inline int interpolate(int y0, int y1, int y2, int x)
{
return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
}
static inline int32_t round_fixed(fixed x)
{
return (x + fixed1/2) >> 32;
}
#define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg])
#define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg)
/* Fixed hardware specs */
#define CH7006_FREQ0 14318
#define CH7006_MAXN 650
#define CH7006_MAXM 315
/* Register definitions */
#define CH7006_DISPMODE 0x00
#define CH7006_DISPMODE_INPUT_RES 0, 7:5
#define CH7006_DISPMODE_INPUT_RES_512x384 0x0
#define CH7006_DISPMODE_INPUT_RES_720x400 0x1
#define CH7006_DISPMODE_INPUT_RES_640x400 0x2
#define CH7006_DISPMODE_INPUT_RES_640x480 0x3
#define CH7006_DISPMODE_INPUT_RES_800x600 0x4
#define CH7006_DISPMODE_INPUT_RES_NATIVE 0x5
#define CH7006_DISPMODE_OUTPUT_STD 0, 4:3
#define CH7006_DISPMODE_OUTPUT_STD_PAL 0x0
#define CH7006_DISPMODE_OUTPUT_STD_NTSC 0x1
#define CH7006_DISPMODE_OUTPUT_STD_PAL_M 0x2
#define CH7006_DISPMODE_OUTPUT_STD_NTSC_J 0x3
#define CH7006_DISPMODE_SCALING_RATIO 0, 2:0
#define CH7006_DISPMODE_SCALING_RATIO_5_4 0x0
#define CH7006_DISPMODE_SCALING_RATIO_1_1 0x1
#define CH7006_DISPMODE_SCALING_RATIO_7_8 0x2
#define CH7006_DISPMODE_SCALING_RATIO_5_6 0x3
#define CH7006_DISPMODE_SCALING_RATIO_3_4 0x4
#define CH7006_DISPMODE_SCALING_RATIO_7_10 0x5
#define CH7006_FFILTER 0x01
#define CH7006_FFILTER_TEXT 0, 5:4
#define CH7006_FFILTER_LUMA 0, 3:2
#define CH7006_FFILTER_CHROMA 0, 1:0
#define CH7006_FFILTER_CHROMA_NO_DCRAWL 0x3
#define CH7006_BWIDTH 0x03
#define CH7006_BWIDTH_5L_FFILER (1 << 7)
#define CH7006_BWIDTH_CVBS_NO_CHROMA (1 << 6)
#define CH7006_BWIDTH_CHROMA 0, 5:4
#define CH7006_BWIDTH_SVIDEO_YPEAK (1 << 3)
#define CH7006_BWIDTH_SVIDEO_LUMA 0, 2:1
#define CH7006_BWIDTH_CVBS_LUMA 0, 0:0
#define CH7006_INPUT_FORMAT 0x04
#define CH7006_INPUT_FORMAT_DAC_GAIN (1 << 6)
#define CH7006_INPUT_FORMAT_RGB_PASS_THROUGH (1 << 5)
#define CH7006_INPUT_FORMAT_FORMAT 0, 3:0
#define CH7006_INPUT_FORMAT_FORMAT_RGB16 0x0
#define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m16 0x1
#define CH7006_INPUT_FORMAT_FORMAT_RGB24m16 0x2
#define CH7006_INPUT_FORMAT_FORMAT_RGB15 0x3
#define CH7006_INPUT_FORMAT_FORMAT_RGB24m12C 0x4
#define CH7006_INPUT_FORMAT_FORMAT_RGB24m12I 0x5
#define CH7006_INPUT_FORMAT_FORMAT_RGB24m8 0x6
#define CH7006_INPUT_FORMAT_FORMAT_RGB16m8 0x7
#define CH7006_INPUT_FORMAT_FORMAT_RGB15m8 0x8
#define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m8 0x9
#define CH7006_CLKMODE 0x06
#define CH7006_CLKMODE_SUBC_LOCK (1 << 7)
#define CH7006_CLKMODE_MASTER (1 << 6)
#define CH7006_CLKMODE_POS_EDGE (1 << 4)
#define CH7006_CLKMODE_XCM 0, 3:2
#define CH7006_CLKMODE_PCM 0, 1:0
#define CH7006_START_ACTIVE 0x07
#define CH7006_START_ACTIVE_0 0, 7:0
#define CH7006_POV 0x08
#define CH7006_POV_START_ACTIVE_8 8, 2:2
#define CH7006_POV_HPOS_8 8, 1:1
#define CH7006_POV_VPOS_8 8, 0:0
#define CH7006_BLACK_LEVEL 0x09
#define CH7006_BLACK_LEVEL_0 0, 7:0
#define CH7006_HPOS 0x0a
#define CH7006_HPOS_0 0, 7:0
#define CH7006_VPOS 0x0b
#define CH7006_VPOS_0 0, 7:0
#define CH7006_INPUT_SYNC 0x0d
#define CH7006_INPUT_SYNC_EMBEDDED (1 << 3)
#define CH7006_INPUT_SYNC_OUTPUT (1 << 2)
#define CH7006_INPUT_SYNC_PVSYNC (1 << 1)
#define CH7006_INPUT_SYNC_PHSYNC (1 << 0)
#define CH7006_POWER 0x0e
#define CH7006_POWER_SCART (1 << 4)
#define CH7006_POWER_RESET (1 << 3)
#define CH7006_POWER_LEVEL 0, 2:0
#define CH7006_POWER_LEVEL_CVBS_OFF 0x0
#define CH7006_POWER_LEVEL_POWER_OFF 0x1
#define CH7006_POWER_LEVEL_SVIDEO_OFF 0x2
#define CH7006_POWER_LEVEL_NORMAL 0x3
#define CH7006_POWER_LEVEL_FULL_POWER_OFF 0x4
#define CH7006_DETECT 0x10
#define CH7006_DETECT_SVIDEO_Y_TEST (1 << 3)
#define CH7006_DETECT_SVIDEO_C_TEST (1 << 2)
#define CH7006_DETECT_CVBS_TEST (1 << 1)
#define CH7006_DETECT_SENSE (1 << 0)
#define CH7006_CONTRAST 0x11
#define CH7006_CONTRAST_0 0, 2:0
#define CH7006_PLLOV 0x13
#define CH7006_PLLOV_N_8 8, 2:1
#define CH7006_PLLOV_M_8 8, 0:0
#define CH7006_PLLM 0x14
#define CH7006_PLLM_0 0, 7:0
#define CH7006_PLLN 0x15
#define CH7006_PLLN_0 0, 7:0
#define CH7006_BCLKOUT 0x17
#define CH7006_SUBC_INC0 0x18
#define CH7006_SUBC_INC0_28 28, 3:0
#define CH7006_SUBC_INC1 0x19
#define CH7006_SUBC_INC1_24 24, 3:0
#define CH7006_SUBC_INC2 0x1a
#define CH7006_SUBC_INC2_20 20, 3:0
#define CH7006_SUBC_INC3 0x1b
#define CH7006_SUBC_INC3_GPIO1_VAL (1 << 7)
#define CH7006_SUBC_INC3_GPIO0_VAL (1 << 6)
#define CH7006_SUBC_INC3_POUT_3_3V (1 << 5)
#define CH7006_SUBC_INC3_POUT_INV (1 << 4)
#define CH7006_SUBC_INC3_16 16, 3:0
#define CH7006_SUBC_INC4 0x1c
#define CH7006_SUBC_INC4_GPIO1_IN (1 << 7)
#define CH7006_SUBC_INC4_GPIO0_IN (1 << 6)
#define CH7006_SUBC_INC4_DS_INPUT (1 << 4)
#define CH7006_SUBC_INC4_12 12, 3:0
#define CH7006_SUBC_INC5 0x1d
#define CH7006_SUBC_INC5_8 8, 3:0
#define CH7006_SUBC_INC6 0x1e
#define CH7006_SUBC_INC6_4 4, 3:0
#define CH7006_SUBC_INC7 0x1f
#define CH7006_SUBC_INC7_0 0, 3:0
#define CH7006_PLL_CONTROL 0x20
#define CH7006_PLL_CONTROL_CPI (1 << 5)
#define CH7006_PLL_CONTROL_CAPACITOR (1 << 4)
#define CH7006_PLL_CONTROL_7STAGES (1 << 3)
#define CH7006_PLL_CONTROL_DIGITAL_5V (1 << 2)
#define CH7006_PLL_CONTROL_ANALOG_5V (1 << 1)
#define CH7006_PLL_CONTROL_MEMORY_5V (1 << 0)
#define CH7006_CALC_SUBC_INC0 0x21
#define CH7006_CALC_SUBC_INC0_24 24, 4:3
#define CH7006_CALC_SUBC_INC0_HYST 0, 2:1
#define CH7006_CALC_SUBC_INC0_AUTO (1 << 0)
#define CH7006_CALC_SUBC_INC1 0x22
#define CH7006_CALC_SUBC_INC1_16 16, 7:0
#define CH7006_CALC_SUBC_INC2 0x23
#define CH7006_CALC_SUBC_INC2_8 8, 7:0
#define CH7006_CALC_SUBC_INC3 0x24
#define CH7006_CALC_SUBC_INC3_0 0, 7:0
#define CH7006_VERSION_ID 0x25
#endif

464
drivers/gpu/drm/i2c/sil164_drv.c Normal file
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/*
* Copyright (C) 2010 Francisco Jerez.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/module.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder_slave.h>
#include <drm/i2c/sil164.h>
struct sil164_priv {
struct sil164_encoder_params config;
struct i2c_client *duallink_slave;
uint8_t saved_state[0x10];
uint8_t saved_slave_state[0x10];
};
#define to_sil164_priv(x) \
((struct sil164_priv *)to_encoder_slave(x)->slave_priv)
#define sil164_dbg(client, format, ...) do { \
if (drm_debug & DRM_UT_KMS) \
dev_printk(KERN_DEBUG, &client->dev, \
"%s: " format, __func__, ## __VA_ARGS__); \
} while (0)
#define sil164_info(client, format, ...) \
dev_info(&client->dev, format, __VA_ARGS__)
#define sil164_err(client, format, ...) \
dev_err(&client->dev, format, __VA_ARGS__)
#define SIL164_I2C_ADDR_MASTER 0x38
#define SIL164_I2C_ADDR_SLAVE 0x39
/* HW register definitions */
#define SIL164_VENDOR_LO 0x0
#define SIL164_VENDOR_HI 0x1
#define SIL164_DEVICE_LO 0x2
#define SIL164_DEVICE_HI 0x3
#define SIL164_REVISION 0x4
#define SIL164_FREQ_MIN 0x6
#define SIL164_FREQ_MAX 0x7
#define SIL164_CONTROL0 0x8
# define SIL164_CONTROL0_POWER_ON 0x01
# define SIL164_CONTROL0_EDGE_RISING 0x02
# define SIL164_CONTROL0_INPUT_24BIT 0x04
# define SIL164_CONTROL0_DUAL_EDGE 0x08
# define SIL164_CONTROL0_HSYNC_ON 0x10
# define SIL164_CONTROL0_VSYNC_ON 0x20
#define SIL164_DETECT 0x9
# define SIL164_DETECT_INTR_STAT 0x01
# define SIL164_DETECT_HOTPLUG_STAT 0x02
# define SIL164_DETECT_RECEIVER_STAT 0x04
# define SIL164_DETECT_INTR_MODE_RECEIVER 0x00
# define SIL164_DETECT_INTR_MODE_HOTPLUG 0x08
# define SIL164_DETECT_OUT_MODE_HIGH 0x00
# define SIL164_DETECT_OUT_MODE_INTR 0x10
# define SIL164_DETECT_OUT_MODE_RECEIVER 0x20
# define SIL164_DETECT_OUT_MODE_HOTPLUG 0x30
# define SIL164_DETECT_VSWING_STAT 0x80
#define SIL164_CONTROL1 0xa
# define SIL164_CONTROL1_DESKEW_ENABLE 0x10
# define SIL164_CONTROL1_DESKEW_INCR_SHIFT 5
#define SIL164_GPIO 0xb
#define SIL164_CONTROL2 0xc
# define SIL164_CONTROL2_FILTER_ENABLE 0x01
# define SIL164_CONTROL2_FILTER_SETTING_SHIFT 1
# define SIL164_CONTROL2_DUALLINK_MASTER 0x40
# define SIL164_CONTROL2_SYNC_CONT 0x80
#define SIL164_DUALLINK 0xd
# define SIL164_DUALLINK_ENABLE 0x10
# define SIL164_DUALLINK_SKEW_SHIFT 5
#define SIL164_PLLZONE 0xe
# define SIL164_PLLZONE_STAT 0x08
# define SIL164_PLLZONE_FORCE_ON 0x10
# define SIL164_PLLZONE_FORCE_HIGH 0x20
/* HW access functions */
static void
sil164_write(struct i2c_client *client, uint8_t addr, uint8_t val)
{
uint8_t buf[] = {addr, val};
int ret;
ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
if (ret < 0)
sil164_err(client, "Error %d writing to subaddress 0x%x\n",
ret, addr);
}
static uint8_t
sil164_read(struct i2c_client *client, uint8_t addr)
{
uint8_t val;
int ret;
ret = i2c_master_send(client, &addr, sizeof(addr));
if (ret < 0)
goto fail;
ret = i2c_master_recv(client, &val, sizeof(val));
if (ret < 0)
goto fail;
return val;
fail:
sil164_err(client, "Error %d reading from subaddress 0x%x\n",
ret, addr);
return 0;
}
static void
sil164_save_state(struct i2c_client *client, uint8_t *state)
{
int i;
for (i = 0x8; i <= 0xe; i++)
state[i] = sil164_read(client, i);
}
static void
sil164_restore_state(struct i2c_client *client, uint8_t *state)
{
int i;
for (i = 0x8; i <= 0xe; i++)
sil164_write(client, i, state[i]);
}
static void
sil164_set_power_state(struct i2c_client *client, bool on)
{
uint8_t control0 = sil164_read(client, SIL164_CONTROL0);
if (on)
control0 |= SIL164_CONTROL0_POWER_ON;
else
control0 &= ~SIL164_CONTROL0_POWER_ON;
sil164_write(client, SIL164_CONTROL0, control0);
}
static void
sil164_init_state(struct i2c_client *client,
struct sil164_encoder_params *config,
bool duallink)
{
sil164_write(client, SIL164_CONTROL0,
SIL164_CONTROL0_HSYNC_ON |
SIL164_CONTROL0_VSYNC_ON |
(config->input_edge ? SIL164_CONTROL0_EDGE_RISING : 0) |
(config->input_width ? SIL164_CONTROL0_INPUT_24BIT : 0) |
(config->input_dual ? SIL164_CONTROL0_DUAL_EDGE : 0));
sil164_write(client, SIL164_DETECT,
SIL164_DETECT_INTR_STAT |
SIL164_DETECT_OUT_MODE_RECEIVER);
sil164_write(client, SIL164_CONTROL1,
(config->input_skew ? SIL164_CONTROL1_DESKEW_ENABLE : 0) |
(((config->input_skew + 4) & 0x7)
<< SIL164_CONTROL1_DESKEW_INCR_SHIFT));
sil164_write(client, SIL164_CONTROL2,
SIL164_CONTROL2_SYNC_CONT |
(config->pll_filter ? 0 : SIL164_CONTROL2_FILTER_ENABLE) |
(4 << SIL164_CONTROL2_FILTER_SETTING_SHIFT));
sil164_write(client, SIL164_PLLZONE, 0);
if (duallink)
sil164_write(client, SIL164_DUALLINK,
SIL164_DUALLINK_ENABLE |
(((config->duallink_skew + 4) & 0x7)
<< SIL164_DUALLINK_SKEW_SHIFT));
else
sil164_write(client, SIL164_DUALLINK, 0);
}
/* DRM encoder functions */
static void
sil164_encoder_set_config(struct drm_encoder *encoder, void *params)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
priv->config = *(struct sil164_encoder_params *)params;
}
static void
sil164_encoder_dpms(struct drm_encoder *encoder, int mode)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
bool on = (mode == DRM_MODE_DPMS_ON);
bool duallink = (on && encoder->crtc->mode.clock > 165000);
sil164_set_power_state(drm_i2c_encoder_get_client(encoder), on);
if (priv->duallink_slave)
sil164_set_power_state(priv->duallink_slave, duallink);
}
static void
sil164_encoder_save(struct drm_encoder *encoder)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
sil164_save_state(drm_i2c_encoder_get_client(encoder),
priv->saved_state);
if (priv->duallink_slave)
sil164_save_state(priv->duallink_slave,
priv->saved_slave_state);
}
static void
sil164_encoder_restore(struct drm_encoder *encoder)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
sil164_restore_state(drm_i2c_encoder_get_client(encoder),
priv->saved_state);
if (priv->duallink_slave)
sil164_restore_state(priv->duallink_slave,
priv->saved_slave_state);
}
static bool
sil164_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
return true;
}
static int
sil164_encoder_mode_valid(struct drm_encoder *encoder,
struct drm_display_mode *mode)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
if (mode->clock < 32000)
return MODE_CLOCK_LOW;
if (mode->clock > 330000 ||
(mode->clock > 165000 && !priv->duallink_slave))
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static void
sil164_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
bool duallink = adjusted_mode->clock > 165000;
sil164_init_state(drm_i2c_encoder_get_client(encoder),
&priv->config, duallink);
if (priv->duallink_slave)
sil164_init_state(priv->duallink_slave,
&priv->config, duallink);
sil164_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
}
static enum drm_connector_status
sil164_encoder_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
if (sil164_read(client, SIL164_DETECT) & SIL164_DETECT_HOTPLUG_STAT)
return connector_status_connected;
else
return connector_status_disconnected;
}
static int
sil164_encoder_get_modes(struct drm_encoder *encoder,
struct drm_connector *connector)
{
return 0;
}
static int
sil164_encoder_create_resources(struct drm_encoder *encoder,
struct drm_connector *connector)
{
return 0;
}
static int
sil164_encoder_set_property(struct drm_encoder *encoder,
struct drm_connector *connector,
struct drm_property *property,
uint64_t val)
{
return 0;
}
static void
sil164_encoder_destroy(struct drm_encoder *encoder)
{
struct sil164_priv *priv = to_sil164_priv(encoder);
if (priv->duallink_slave)
i2c_unregister_device(priv->duallink_slave);
kfree(priv);
drm_i2c_encoder_destroy(encoder);
}
static struct drm_encoder_slave_funcs sil164_encoder_funcs = {
.set_config = sil164_encoder_set_config,
.destroy = sil164_encoder_destroy,
.dpms = sil164_encoder_dpms,
.save = sil164_encoder_save,
.restore = sil164_encoder_restore,
.mode_fixup = sil164_encoder_mode_fixup,
.mode_valid = sil164_encoder_mode_valid,
.mode_set = sil164_encoder_mode_set,
.detect = sil164_encoder_detect,
.get_modes = sil164_encoder_get_modes,
.create_resources = sil164_encoder_create_resources,
.set_property = sil164_encoder_set_property,
};
/* I2C driver functions */
static int
sil164_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
int vendor = sil164_read(client, SIL164_VENDOR_HI) << 8 |
sil164_read(client, SIL164_VENDOR_LO);
int device = sil164_read(client, SIL164_DEVICE_HI) << 8 |
sil164_read(client, SIL164_DEVICE_LO);
int rev = sil164_read(client, SIL164_REVISION);
if (vendor != 0x1 || device != 0x6) {
sil164_dbg(client, "Unknown device %x:%x.%x\n",
vendor, device, rev);
return -ENODEV;
}
sil164_info(client, "Detected device %x:%x.%x\n",
vendor, device, rev);
return 0;
}
static int
sil164_remove(struct i2c_client *client)
{
return 0;
}
static struct i2c_client *
sil164_detect_slave(struct i2c_client *client)
{
struct i2c_adapter *adap = client->adapter;
struct i2c_msg msg = {
.addr = SIL164_I2C_ADDR_SLAVE,
.len = 0,
};
const struct i2c_board_info info = {
I2C_BOARD_INFO("sil164", SIL164_I2C_ADDR_SLAVE)
};
if (i2c_transfer(adap, &msg, 1) != 1) {
sil164_dbg(adap, "No dual-link slave found.");
return NULL;
}
return i2c_new_device(adap, &info);
}
static int
sil164_encoder_init(struct i2c_client *client,
struct drm_device *dev,
struct drm_encoder_slave *encoder)
{
struct sil164_priv *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
encoder->slave_priv = priv;
encoder->slave_funcs = &sil164_encoder_funcs;
priv->duallink_slave = sil164_detect_slave(client);
return 0;
}
static struct i2c_device_id sil164_ids[] = {
{ "sil164", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, sil164_ids);
static struct drm_i2c_encoder_driver sil164_driver = {
.i2c_driver = {
.probe = sil164_probe,
.remove = sil164_remove,
.driver = {
.name = "sil164",
},
.id_table = sil164_ids,
},
.encoder_init = sil164_encoder_init,
};
/* Module initialization */
static int __init
sil164_init(void)
{
return drm_i2c_encoder_register(THIS_MODULE, &sil164_driver);
}
static void __exit
sil164_exit(void)
{
drm_i2c_encoder_unregister(&sil164_driver);
}
MODULE_AUTHOR("Francisco Jerez <currojerez@riseup.net>");
MODULE_DESCRIPTION("Silicon Image sil164 TMDS transmitter driver");
MODULE_LICENSE("GPL and additional rights");
module_init(sil164_init);
module_exit(sil164_exit);

906
drivers/gpu/drm/i2c/tda998x_drv.c Normal file
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@@ -0,0 +1,906 @@
/*
* Copyright (C) 2012 Texas Instruments
* Author: Rob Clark <robdclark@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/module.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder_slave.h>
#include <drm/drm_edid.h>
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
struct tda998x_priv {
struct i2c_client *cec;
uint16_t rev;
uint8_t current_page;
int dpms;
};
#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
/* The TDA9988 series of devices use a paged register scheme.. to simplify
* things we encode the page # in upper bits of the register #. To read/
* write a given register, we need to make sure CURPAGE register is set
* appropriately. Which implies reads/writes are not atomic. Fun!
*/
#define REG(page, addr) (((page) << 8) | (addr))
#define REG2ADDR(reg) ((reg) & 0xff)
#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
#define REG_CURPAGE 0xff /* write */
/* Page 00h: General Control */
#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
# define MAIN_CNTRL0_SR (1 << 0)
# define MAIN_CNTRL0_DECS (1 << 1)
# define MAIN_CNTRL0_DEHS (1 << 2)
# define MAIN_CNTRL0_CECS (1 << 3)
# define MAIN_CNTRL0_CEHS (1 << 4)
# define MAIN_CNTRL0_SCALER (1 << 7)
#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
# define SOFTRESET_AUDIO (1 << 0)
# define SOFTRESET_I2C_MASTER (1 << 1)
#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
# define I2C_MASTER_DIS_MM (1 << 0)
# define I2C_MASTER_DIS_FILT (1 << 1)
# define I2C_MASTER_APP_STRT_LAT (1 << 2)
#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
# define VIP_CNTRL_0_MIRR_A (1 << 7)
# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
# define VIP_CNTRL_0_MIRR_B (1 << 3)
# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
# define VIP_CNTRL_1_MIRR_C (1 << 7)
# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
# define VIP_CNTRL_1_MIRR_D (1 << 3)
# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
# define VIP_CNTRL_2_MIRR_E (1 << 7)
# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
# define VIP_CNTRL_2_MIRR_F (1 << 3)
# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
# define VIP_CNTRL_3_X_TGL (1 << 0)
# define VIP_CNTRL_3_H_TGL (1 << 1)
# define VIP_CNTRL_3_V_TGL (1 << 2)
# define VIP_CNTRL_3_EMB (1 << 3)
# define VIP_CNTRL_3_SYNC_DE (1 << 4)
# define VIP_CNTRL_3_SYNC_HS (1 << 5)
# define VIP_CNTRL_3_DE_INT (1 << 6)
# define VIP_CNTRL_3_EDGE (1 << 7)
#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
# define VIP_CNTRL_4_CCIR656 (1 << 4)
# define VIP_CNTRL_4_656_ALT (1 << 5)
# define VIP_CNTRL_4_TST_656 (1 << 6)
# define VIP_CNTRL_4_TST_PAT (1 << 7)
#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
# define VIP_CNTRL_5_CKCASE (1 << 0)
# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
# define MAT_CONTRL_MAT_BP (1 << 2)
#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
# define TBG_CNTRL_1_VH_TGL_0 (1 << 0)
# define TBG_CNTRL_1_VH_TGL_1 (1 << 1)
# define TBG_CNTRL_1_VH_TGL_2 (1 << 2)
# define TBG_CNTRL_1_VHX_EXT_DE (1 << 3)
# define TBG_CNTRL_1_VHX_EXT_HS (1 << 4)
# define TBG_CNTRL_1_VHX_EXT_VS (1 << 5)
# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
# define HVF_CNTRL_0_SM (1 << 7)
# define HVF_CNTRL_0_RWB (1 << 6)
# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
# define HVF_CNTRL_1_FOR (1 << 0)
# define HVF_CNTRL_1_YUVBLK (1 << 1)
# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
/* Page 02h: PLL settings */
#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
# define PLL_SERIAL_1_SRL_FDN (1 << 0)
# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0)
# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
# define PLL_SERIAL_3_SRL_DE (1 << 2)
# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
# define SEL_CLK_SEL_CLK1 (1 << 0)
# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
# define SEL_CLK_ENA_SC_CLK (1 << 3)
#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
/* Page 09h: EDID Control */
#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
/* next 127 successive registers are the EDID block */
#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
/* Page 10h: information frames and packets */
/* Page 11h: audio settings and content info packets */
#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
# define AIP_CNTRL_0_RST_FIFO (1 << 0)
# define AIP_CNTRL_0_SWAP (1 << 1)
# define AIP_CNTRL_0_LAYOUT (1 << 2)
# define AIP_CNTRL_0_ACR_MAN (1 << 5)
# define AIP_CNTRL_0_RST_CTS (1 << 6)
#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
# define ENC_CNTRL_RST_ENC (1 << 0)
# define ENC_CNTRL_RST_SEL (1 << 1)
# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
/* Page 12h: HDCP and OTP */
#define REG_TX3 REG(0x12, 0x9a) /* read/write */
#define REG_TX33 REG(0x12, 0xb8) /* read/write */
# define TX33_HDMI (1 << 1)
/* Page 13h: Gamut related metadata packets */
/* CEC registers: (not paged)
*/
#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
#define REG_CEC_RXSHPDLEV 0xfe /* read */
# define CEC_RXSHPDLEV_RXSENS (1 << 0)
# define CEC_RXSHPDLEV_HPD (1 << 1)
#define REG_CEC_ENAMODS 0xff /* read/write */
# define CEC_ENAMODS_DIS_FRO (1 << 6)
# define CEC_ENAMODS_DIS_CCLK (1 << 5)
# define CEC_ENAMODS_EN_RXSENS (1 << 2)
# define CEC_ENAMODS_EN_HDMI (1 << 1)
# define CEC_ENAMODS_EN_CEC (1 << 0)
/* Device versions: */
#define TDA9989N2 0x0101
#define TDA19989 0x0201
#define TDA19989N2 0x0202
#define TDA19988 0x0301
static void
cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val)
{
struct i2c_client *client = to_tda998x_priv(encoder)->cec;
uint8_t buf[] = {addr, val};
int ret;
ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
if (ret < 0)
dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
}
static uint8_t
cec_read(struct drm_encoder *encoder, uint8_t addr)
{
struct i2c_client *client = to_tda998x_priv(encoder)->cec;
uint8_t val;
int ret;
ret = i2c_master_send(client, &addr, sizeof(addr));
if (ret < 0)
goto fail;
ret = i2c_master_recv(client, &val, sizeof(val));
if (ret < 0)
goto fail;
return val;
fail:
dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
return 0;
}
static void
set_page(struct drm_encoder *encoder, uint16_t reg)
{
struct tda998x_priv *priv = to_tda998x_priv(encoder);
if (REG2PAGE(reg) != priv->current_page) {
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
uint8_t buf[] = {
REG_CURPAGE, REG2PAGE(reg)
};
int ret = i2c_master_send(client, buf, sizeof(buf));
if (ret < 0)
dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret);
priv->current_page = REG2PAGE(reg);
}
}
static int
reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
uint8_t addr = REG2ADDR(reg);
int ret;
set_page(encoder, reg);
ret = i2c_master_send(client, &addr, sizeof(addr));
if (ret < 0)
goto fail;
ret = i2c_master_recv(client, buf, cnt);
if (ret < 0)
goto fail;
return ret;
fail:
dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
return ret;
}
static uint8_t
reg_read(struct drm_encoder *encoder, uint16_t reg)
{
uint8_t val = 0;
reg_read_range(encoder, reg, &val, sizeof(val));
return val;
}
static void
reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
uint8_t buf[] = {REG2ADDR(reg), val};
int ret;
set_page(encoder, reg);
ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
if (ret < 0)
dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
}
static void
reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val)
{
struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
int ret;
set_page(encoder, reg);
ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
if (ret < 0)
dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
}
static void
reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
{
reg_write(encoder, reg, reg_read(encoder, reg) | val);
}
static void
reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
{
reg_write(encoder, reg, reg_read(encoder, reg) & ~val);
}
static void
tda998x_reset(struct drm_encoder *encoder)
{
/* reset audio and i2c master: */
reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
msleep(50);
reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
msleep(50);
/* reset transmitter: */
reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
/* PLL registers common configuration */
reg_write(encoder, REG_PLL_SERIAL_1, 0x00);
reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
reg_write(encoder, REG_PLL_SERIAL_3, 0x00);
reg_write(encoder, REG_SERIALIZER, 0x00);
reg_write(encoder, REG_BUFFER_OUT, 0x00);
reg_write(encoder, REG_PLL_SCG1, 0x00);
reg_write(encoder, REG_AUDIO_DIV, 0x03);
reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
reg_write(encoder, REG_PLL_SCGN1, 0xfa);
reg_write(encoder, REG_PLL_SCGN2, 0x00);
reg_write(encoder, REG_PLL_SCGR1, 0x5b);
reg_write(encoder, REG_PLL_SCGR2, 0x00);
reg_write(encoder, REG_PLL_SCG2, 0x10);
}
/* DRM encoder functions */
static void
tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
{
}
static void
tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
{
struct tda998x_priv *priv = to_tda998x_priv(encoder);
/* we only care about on or off: */
if (mode != DRM_MODE_DPMS_ON)
mode = DRM_MODE_DPMS_OFF;
if (mode == priv->dpms)
return;
switch (mode) {
case DRM_MODE_DPMS_ON:
/* enable audio and video ports */
reg_write(encoder, REG_ENA_AP, 0xff);
reg_write(encoder, REG_ENA_VP_0, 0xff);
reg_write(encoder, REG_ENA_VP_1, 0xff);
reg_write(encoder, REG_ENA_VP_2, 0xff);
/* set muxing after enabling ports: */
reg_write(encoder, REG_VIP_CNTRL_0,
VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
reg_write(encoder, REG_VIP_CNTRL_1,
VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1));
reg_write(encoder, REG_VIP_CNTRL_2,
VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5));
break;
case DRM_MODE_DPMS_OFF:
/* disable audio and video ports */
reg_write(encoder, REG_ENA_AP, 0x00);
reg_write(encoder, REG_ENA_VP_0, 0x00);
reg_write(encoder, REG_ENA_VP_1, 0x00);
reg_write(encoder, REG_ENA_VP_2, 0x00);
break;
}
priv->dpms = mode;
}
static void
tda998x_encoder_save(struct drm_encoder *encoder)
{
DBG("");
}
static void
tda998x_encoder_restore(struct drm_encoder *encoder)
{
DBG("");
}
static bool
tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
return true;
}
static int
tda998x_encoder_mode_valid(struct drm_encoder *encoder,
struct drm_display_mode *mode)
{
return MODE_OK;
}
static void
tda998x_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct tda998x_priv *priv = to_tda998x_priv(encoder);
uint16_t hs_start, hs_end, line_start, line_end;
uint16_t vwin_start, vwin_end, de_start, de_end;
uint16_t ref_pix, ref_line, pix_start2;
uint8_t reg, div, rep;
hs_start = mode->hsync_start - mode->hdisplay;
hs_end = mode->hsync_end - mode->hdisplay;
line_start = 1;
line_end = 1 + mode->vsync_end - mode->vsync_start;
vwin_start = mode->vtotal - mode->vsync_start;
vwin_end = vwin_start + mode->vdisplay;
de_start = mode->htotal - mode->hdisplay;
de_end = mode->htotal;
pix_start2 = 0;
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
pix_start2 = (mode->htotal / 2) + hs_start;
/* TODO how is this value calculated? It is 2 for all common
* formats in the tables in out of tree nxp driver (assuming
* I've properly deciphered their byzantine table system)
*/
ref_line = 2;
/* this might changes for other color formats from the CRTC: */
ref_pix = 3 + hs_start;
div = 148500 / mode->clock;
DBG("clock=%d, div=%u", mode->clock, div);
DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u",
hs_start, hs_end, line_start, line_end);
DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u",
vwin_start, vwin_end, de_start, de_end);
DBG("ref_line=%u, ref_pix=%u, pix_start2=%u",
ref_line, ref_pix, pix_start2);
/* mute the audio FIFO: */
reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
/* set HDMI HDCP mode off: */
reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
reg_clear(encoder, REG_TX33, TX33_HDMI);
reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
/* no pre-filter or interpolator: */
reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
HVF_CNTRL_0_INTPOL(0));
reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
VIP_CNTRL_4_BLC(0));
reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
reg_write(encoder, REG_SERIALIZER, 0);
reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
/* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
rep = 0;
reg_write(encoder, REG_RPT_CNTRL, 0);
reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
PLL_SERIAL_2_SRL_PR(rep));
reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2);
reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2);
/* set color matrix bypass flag: */
reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
/* set BIAS tmds value: */
reg_write(encoder, REG_ANA_GENERAL, 0x09);
reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
reg_write(encoder, REG_VIP_CNTRL_3, 0);
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
reg_write(encoder, REG_VIDFORMAT, 0x00);
reg_write16(encoder, REG_NPIX_MSB, mode->hdisplay - 1);
reg_write16(encoder, REG_NLINE_MSB, mode->vdisplay - 1);
reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start);
reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end);
reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start);
reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start);
reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start);
reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end);
reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start);
reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end);
reg_write16(encoder, REG_DE_START_MSB, de_start);
reg_write16(encoder, REG_DE_STOP_MSB, de_end);
if (priv->rev == TDA19988) {
/* let incoming pixels fill the active space (if any) */
reg_write(encoder, REG_ENABLE_SPACE, 0x01);
}
reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
reg_write16(encoder, REG_REFLINE_MSB, ref_line);
reg = TBG_CNTRL_1_VHX_EXT_DE |
TBG_CNTRL_1_VHX_EXT_HS |
TBG_CNTRL_1_VHX_EXT_VS |
TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
TBG_CNTRL_1_VH_TGL_2;
if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC))
reg |= TBG_CNTRL_1_VH_TGL_0;
reg_set(encoder, REG_TBG_CNTRL_1, reg);
/* must be last register set: */
reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
}
static enum drm_connector_status
tda998x_encoder_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV);
return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
connector_status_disconnected;
}
static int
read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
{
uint8_t offset, segptr;
int ret, i;
/* enable EDID read irq: */
reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
offset = (blk & 1) ? 128 : 0;
segptr = blk / 2;
reg_write(encoder, REG_DDC_ADDR, 0xa0);
reg_write(encoder, REG_DDC_OFFS, offset);
reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60);
reg_write(encoder, REG_DDC_SEGM, segptr);
/* enable reading EDID: */
reg_write(encoder, REG_EDID_CTRL, 0x1);
/* flag must be cleared by sw: */
reg_write(encoder, REG_EDID_CTRL, 0x0);
/* wait for block read to complete: */
for (i = 100; i > 0; i--) {
uint8_t val = reg_read(encoder, REG_INT_FLAGS_2);
if (val & INT_FLAGS_2_EDID_BLK_RD)
break;
msleep(1);
}
if (i == 0)
return -ETIMEDOUT;
ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH);
if (ret != EDID_LENGTH) {
dev_err(encoder->dev->dev, "failed to read edid block %d: %d",
blk, ret);
return ret;
}
reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
return 0;
}
static uint8_t *
do_get_edid(struct drm_encoder *encoder)
{
int j = 0, valid_extensions = 0;
uint8_t *block, *new;
bool print_bad_edid = drm_debug & DRM_UT_KMS;
if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
return NULL;
/* base block fetch */
if (read_edid_block(encoder, block, 0))
goto fail;
if (!drm_edid_block_valid(block, 0, print_bad_edid))
goto fail;
/* if there's no extensions, we're done */
if (block[0x7e] == 0)
return block;
new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
if (!new)
goto fail;
block = new;
for (j = 1; j <= block[0x7e]; j++) {
uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
if (read_edid_block(encoder, ext_block, j))
goto fail;
if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
goto fail;
valid_extensions++;
}
if (valid_extensions != block[0x7e]) {
block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
block[0x7e] = valid_extensions;
new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
if (!new)
goto fail;
block = new;
}
return block;
fail:
dev_warn(encoder->dev->dev, "failed to read EDID\n");
kfree(block);
return NULL;
}
static int
tda998x_encoder_get_modes(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct edid *edid = (struct edid *)do_get_edid(encoder);
int n = 0;
if (edid) {
drm_mode_connector_update_edid_property(connector, edid);
n = drm_add_edid_modes(connector, edid);
kfree(edid);
}
return n;
}
static int
tda998x_encoder_create_resources(struct drm_encoder *encoder,
struct drm_connector *connector)
{
DBG("");
return 0;
}
static int
tda998x_encoder_set_property(struct drm_encoder *encoder,
struct drm_connector *connector,
struct drm_property *property,
uint64_t val)
{
DBG("");
return 0;
}
static void
tda998x_encoder_destroy(struct drm_encoder *encoder)
{
struct tda998x_priv *priv = to_tda998x_priv(encoder);
drm_i2c_encoder_destroy(encoder);
kfree(priv);
}
static struct drm_encoder_slave_funcs tda998x_encoder_funcs = {
.set_config = tda998x_encoder_set_config,
.destroy = tda998x_encoder_destroy,
.dpms = tda998x_encoder_dpms,
.save = tda998x_encoder_save,
.restore = tda998x_encoder_restore,
.mode_fixup = tda998x_encoder_mode_fixup,
.mode_valid = tda998x_encoder_mode_valid,
.mode_set = tda998x_encoder_mode_set,
.detect = tda998x_encoder_detect,
.get_modes = tda998x_encoder_get_modes,
.create_resources = tda998x_encoder_create_resources,
.set_property = tda998x_encoder_set_property,
};
/* I2C driver functions */
static int
tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
return 0;
}
static int
tda998x_remove(struct i2c_client *client)
{
return 0;
}
static int
tda998x_encoder_init(struct i2c_client *client,
struct drm_device *dev,
struct drm_encoder_slave *encoder_slave)
{
struct drm_encoder *encoder = &encoder_slave->base;
struct tda998x_priv *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->current_page = 0;
priv->cec = i2c_new_dummy(client->adapter, 0x34);
priv->dpms = DRM_MODE_DPMS_OFF;
encoder_slave->slave_priv = priv;
encoder_slave->slave_funcs = &tda998x_encoder_funcs;
/* wake up the device: */
cec_write(encoder, REG_CEC_ENAMODS,
CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
tda998x_reset(encoder);
/* read version: */
priv->rev = reg_read(encoder, REG_VERSION_LSB) |
reg_read(encoder, REG_VERSION_MSB) << 8;
/* mask off feature bits: */
priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
switch (priv->rev) {
case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break;
case TDA19989: dev_info(dev->dev, "found TDA19989"); break;
case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break;
case TDA19988: dev_info(dev->dev, "found TDA19988"); break;
default:
DBG("found unsupported device: %04x", priv->rev);
goto fail;
}
/* after reset, enable DDC: */
reg_write(encoder, REG_DDC_DISABLE, 0x00);
/* set clock on DDC channel: */
reg_write(encoder, REG_TX3, 39);
/* if necessary, disable multi-master: */
if (priv->rev == TDA19989)
reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL,
CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
return 0;
fail:
/* if encoder_init fails, the encoder slave is never registered,
* so cleanup here:
*/
if (priv->cec)
i2c_unregister_device(priv->cec);
kfree(priv);
encoder_slave->slave_priv = NULL;
encoder_slave->slave_funcs = NULL;
return -ENXIO;
}
static struct i2c_device_id tda998x_ids[] = {
{ "tda998x", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tda998x_ids);
static struct drm_i2c_encoder_driver tda998x_driver = {
.i2c_driver = {
.probe = tda998x_probe,
.remove = tda998x_remove,
.driver = {
.name = "tda998x",
},
.id_table = tda998x_ids,
},
.encoder_init = tda998x_encoder_init,
};
/* Module initialization */
static int __init
tda998x_init(void)
{
DBG("");
return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
}
static void __exit
tda998x_exit(void)
{
DBG("");
drm_i2c_encoder_unregister(&tda998x_driver);
}
MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
MODULE_LICENSE("GPL");
module_init(tda998x_init);
module_exit(tda998x_exit);