nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit; kernel source import

Browse Source
This commit is contained in:
Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
45093 changed files with 18199410 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

96
arch/arm/mach-ux500/Kconfig Normal file
View File

@@ -0,0 +1,96 @@
config ARCH_U8500
bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7
depends on MMU
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Support for ST-Ericsson's Ux500 architecture
if ARCH_U8500
config UX500_SOC_COMMON
bool
default y
select ABX500_CORE
select AB8500_CORE
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select CACHE_L2X0
select CLKSRC_NOMADIK_MTU
select COMMON_CLK
select PINCTRL
select PINCTRL_NOMADIK
select PINCTRL_ABX500
select PL310_ERRATA_753970 if CACHE_PL310
config UX500_SOC_DB8500
bool
select CPU_FREQ_TABLE if CPU_FREQ
select MFD_DB8500_PRCMU
select PINCTRL_DB8500
select PINCTRL_DB8540
select PINCTRL_AB8500
select PINCTRL_AB8505
select PINCTRL_AB9540
select PINCTRL_AB8540
select REGULATOR
select REGULATOR_DB8500_PRCMU
menu "Ux500 target platform (boards)"
config MACH_MOP500
bool "U8500 Development platform, MOP500 versions"
select I2C
select I2C_NOMADIK
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
select SOC_BUS
select UX500_SOC_DB8500
help
Include support for the MOP500 development platform.
config MACH_HREFV60
bool "U8500 Development platform, HREFv60 version"
select MACH_MOP500
help
Include support for the HREFv60 new development platform.
Includes HREFv70, v71 etc.
config MACH_SNOWBALL
bool "U8500 Snowball platform"
select MACH_MOP500
help
Include support for the snowball development platform.
config UX500_AUTO_PLATFORM
def_bool y
select MACH_MOP500
help
At least one platform needs to be selected in order to build
a working kernel. If everything else is disabled, this
automatically enables MACH_MOP500.
config MACH_UX500_DT
bool "Generic U8500 support using device tree"
depends on MACH_MOP500
select USE_OF
endmenu
config UX500_DEBUG_UART
int "Ux500 UART to use for low-level debug"
default 2
help
Choose the UART on which kernel low-level debug messages should be
output.
endif

19
arch/arm/mach-ux500/Makefile Normal file
View File

@@ -0,0 +1,19 @@
#
# Makefile for the linux kernel, U8500 machine.
#
obj-y := cpu.o devices.o devices-common.o \
id.o usb.o timer.o pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
board-mop500-regulators.o \
board-mop500-uib.o board-mop500-stuib.o \
board-mop500-u8500uib.o \
board-mop500-pins.o \
board-mop500-audio.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
CFLAGS_hotplug.o += -march=armv7-a

3
arch/arm/mach-ux500/Makefile.boot Normal file
View File

@@ -0,0 +1,3 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

176
arch/arm/mach-ux500/board-mop500-audio.c Normal file
View File

@@ -0,0 +1,176 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL), version 2
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/platform_data/dma-ste-dma40.h>
#include "devices.h"
#include "irqs.h"
#include <linux/platform_data/asoc-ux500-msp.h>
#include "ste-dma40-db8500.h"
#include "board-mop500.h"
#include "devices-db8500.h"
#include "pins-db8500.h"
static struct stedma40_chan_cfg msp0_dma_rx = {
.high_priority = true,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
/* data_width is set during configuration */
};
static struct stedma40_chan_cfg msp0_dma_tx = {
.high_priority = true,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
/* data_width is set during configuration */
};
struct msp_i2s_platform_data msp0_platform_data = {
.id = MSP_I2S_0,
.msp_i2s_dma_rx = &msp0_dma_rx,
.msp_i2s_dma_tx = &msp0_dma_tx,
};
static struct stedma40_chan_cfg msp1_dma_rx = {
.high_priority = true,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
/* data_width is set during configuration */
};
static struct stedma40_chan_cfg msp1_dma_tx = {
.high_priority = true,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
/* data_width is set during configuration */
};
struct msp_i2s_platform_data msp1_platform_data = {
.id = MSP_I2S_1,
.msp_i2s_dma_rx = NULL,
.msp_i2s_dma_tx = &msp1_dma_tx,
};
static struct stedma40_chan_cfg msp2_dma_rx = {
.high_priority = true,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
.src_info.psize = STEDMA40_PSIZE_LOG_1,
.dst_info.psize = STEDMA40_PSIZE_LOG_1,
/* data_width is set during configuration */
};
static struct stedma40_chan_cfg msp2_dma_tx = {
.high_priority = true,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_DST_MEMORY,
.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
.use_fixed_channel = true,
.phy_channel = 1,
/* data_width is set during configuration */
};
static struct platform_device *db8500_add_msp_i2s(struct device *parent,
int id,
resource_size_t base, int irq,
struct msp_i2s_platform_data *pdata)
{
struct platform_device *pdev;
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
DEFINE_RES_IRQ(irq),
};
pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
id, irq);
pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata));
if (!pdev) {
pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
id);
return NULL;
}
return pdev;
}
/* Platform device for ASoC MOP500 machine */
static struct platform_device snd_soc_mop500 = {
.name = "snd-soc-mop500",
.id = 0,
.dev = {
.platform_data = NULL,
},
};
struct msp_i2s_platform_data msp2_platform_data = {
.id = MSP_I2S_2,
.msp_i2s_dma_rx = &msp2_dma_rx,
.msp_i2s_dma_tx = &msp2_dma_tx,
};
struct msp_i2s_platform_data msp3_platform_data = {
.id = MSP_I2S_3,
.msp_i2s_dma_rx = &msp1_dma_rx,
.msp_i2s_dma_tx = NULL,
};
void mop500_audio_init(struct device *parent)
{
pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
platform_device_register(&snd_soc_mop500);
pr_info("Initialize MSP I2S-devices.\n");
db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
&msp0_platform_data);
db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
&msp1_platform_data);
db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
&msp2_platform_data);
db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
&msp3_platform_data);
}

843
arch/arm/mach-ux500/board-mop500-pins.c Normal file
View File

@@ -0,0 +1,843 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <linux/string.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <asm/mach-types.h>
#include "pins-db8500.h"
#include "board-mop500.h"
enum custom_pin_cfg_t {
PINS_FOR_DEFAULT,
PINS_FOR_U9500,
};
static enum custom_pin_cfg_t pinsfor;
/* These simply sets bias for pins */
#define BIAS(a,b) static unsigned long a[] = { b }
BIAS(pd, PIN_PULL_DOWN);
BIAS(in_nopull, PIN_INPUT_NOPULL);
BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
BIAS(in_pu, PIN_INPUT_PULLUP);
BIAS(in_pd, PIN_INPUT_PULLDOWN);
BIAS(out_hi, PIN_OUTPUT_HIGH);
BIAS(out_lo, PIN_OUTPUT_LOW);
BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
/* These also force them into GPIO mode */
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
/* Sleep modes */
BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
PIN_SLPM_PDIS_ENABLED);
BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
PIN_SLPM_PDIS_DISABLED);
BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
PIN_SLPM_PDIS_DISABLED);
/* We use these to define hog settings that are always done on boot */
#define DB8500_MUX_HOG(group,func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
#define DB8500_PIN_HOG(pin,conf) \
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
/* These are default states associated with device and changed runtime */
#define DB8500_MUX(group,func,dev) \
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
#define DB8500_PIN(pin,conf,dev) \
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
#define DB8500_PIN_IDLE(pin, conf, dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
pin, conf)
#define DB8500_PIN_SLEEP(pin, conf, dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
pin, conf)
#define DB8500_MUX_STATE(group, func, dev, state) \
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
#define DB8500_PIN_STATE(pin, conf, dev, state) \
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
/* Pin control settings */
static struct pinctrl_map __initdata mop500_family_pinmap[] = {
/*
* uMSP0, mux in 4 pins, regular placement of RX/TX
* explicitly set the pins to no pull
*/
DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
/* MSP2 for HDMI, pull down TXD, TCK, TFS */
DB8500_MUX_HOG("msp2_a_1", "msp2"),
DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
/*
* LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
* pull-up
* TODO: is this really correct? Snowball doesn't have a LCD.
*/
DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
DB8500_PIN_HOG("GPIO68_E1", in_pu),
DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
/*
* STMPE1601/tc35893 keypad IRQ GPIO 218
* TODO: set for snowball and HREF really??
*/
DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
/*
* UART0, we do not mux in u0 here.
* uart-0 pins gpio configuration should be kept intact to prevent
* a glitch in tx line when the tty dev is opened. Later these pins
* are configured by uart driver
*/
DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
/*
* Mux in UART2 on altfunction C and set pull-ups.
* TODO: is this used on U8500 variants and Snowball really?
* The setting on GPIO31 conflicts with magnetometer use on hrefv60
*/
/* default state for UART2 */
DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
/* Sleep state for UART2 */
DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
/*
* The following pin sets were known as "runtime pins" before being
* converted to the pinctrl model. Here we model them as "default"
* states.
*/
/* Mux in UART0 after initialization */
DB8500_MUX("u0_a_1", "u0", "uart0"),
DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
/* Sleep state for UART0 */
DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
/* Mux in UART1 after initialization */
DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
/* Sleep state for UART1 */
DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
/* MSP1 for ALSA codec */
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
/* MSP1 sleep state */
DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
/* LCD VSI1 sleep state */
DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
/* Mux in i2c0 block, default state */
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
/* i2c0 sleep state */
DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
/* Mux in i2c1 block, default state */
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
/* i2c1 sleep state */
DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
/* Mux in i2c2 block, default state */
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
/* i2c2 sleep state */
DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
/* Mux in i2c3 block, default state */
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
/* i2c3 sleep state */
DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
/* SDI0 sleep state */
DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
/* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
/* SDI1 sleep state */
DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
/* Mux in SDI2 (here called MC2) used for for PoP eMMC */
DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
/* SDI2 sleep state */
DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
/* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
/*SDI4 sleep state */
DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
/* Mux in USB pins, drive STP high */
/* USB default state */
DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
/* USB sleep state */
DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
/* Mux in SPI2 pins on the "other C1" altfunction */
DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
/* SPI2 idle state */
DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
/* SPI2 sleep state */
DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
/* ske default state */
DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
/* ske sleep state */
DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
/* STM APE pins states */
DB8500_MUX_STATE("stmape_c_1", "stmape",
"stm", "ape_mipi34"),
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
"stm", "ape_mipi34"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
"stm", "ape_mipi34"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
"stm", "ape_mipi34"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
"stm", "ape_mipi34"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
"stm", "ape_mipi34"), /* dat0 */
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
"stm", "ape_mipi34_sleep"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
"stm", "ape_mipi34_sleep"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
"stm", "ape_mipi34_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
"stm", "ape_mipi34_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
"stm", "ape_mipi34_sleep"), /* dat0 */
DB8500_MUX_STATE("stmape_oc1_1", "stmape",
"stm", "ape_microsd"),
DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
"stm", "ape_microsd"), /* clk */
DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
"stm", "ape_microsd"), /* dat0 */
DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
"stm", "ape_microsd"), /* dat1 */
DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
"stm", "ape_microsd"), /* dat2 */
DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
"stm", "ape_microsd"), /* dat3 */
DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
"stm", "ape_microsd_sleep"), /* clk */
DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
"stm", "ape_microsd_sleep"), /* dat0 */
DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
"stm", "ape_microsd_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
"stm", "ape_microsd_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
"stm", "ape_microsd_sleep"), /* dat3 */
/* STM Modem pins states */
DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
"stm", "mod_mipi34"),
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
"stm", "mod_mipi34"),
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
"stm", "mod_mipi34"),
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
"stm", "mod_mipi34"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
"stm", "mod_mipi34"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
"stm", "mod_mipi34"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
"stm", "mod_mipi34"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
"stm", "mod_mipi34"), /* dat0 */
DB8500_PIN_STATE("GPIO75_H2", in_pu,
"stm", "mod_mipi34"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", out_lo,
"stm", "mod_mipi34"), /* uartmod tx */
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
"stm", "mod_mipi34_sleep"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
"stm", "mod_mipi34_sleep"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
"stm", "mod_mipi34_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
"stm", "mod_mipi34_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
"stm", "mod_mipi34_sleep"), /* dat0 */
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
"stm", "mod_mipi34_sleep"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
"stm", "mod_mipi34_sleep"), /* uartmod tx */
DB8500_MUX_STATE("stmmod_b_1", "stmmod",
"stm", "mod_microsd"),
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
"stm", "mod_microsd"),
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
"stm", "mod_microsd"),
DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
"stm", "mod_microsd"), /* clk */
DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
"stm", "mod_microsd"), /* dat0 */
DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
"stm", "mod_microsd"), /* dat1 */
DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
"stm", "mod_microsd"), /* dat2 */
DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
"stm", "mod_microsd"), /* dat3 */
DB8500_PIN_STATE("GPIO75_H2", in_pu,
"stm", "mod_microsd"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", out_lo,
"stm", "mod_microsd"), /* uartmod tx */
DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
"stm", "mod_microsd_sleep"), /* clk */
DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
"stm", "mod_microsd_sleep"), /* dat0 */
DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
"stm", "mod_microsd_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
"stm", "mod_microsd_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
"stm", "mod_microsd_sleep"), /* dat3 */
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
"stm", "mod_microsd_sleep"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
"stm", "mod_microsd_sleep"), /* uartmod tx */
/* STM dual Modem/APE pins state */
DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
"stm", "mod_mipi34_ape_mipi60"),
DB8500_MUX_STATE("stmape_c_2", "stmape",
"stm", "mod_mipi34_ape_mipi60"),
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
"stm", "mod_mipi34_ape_mipi60"),
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
"stm", "mod_mipi34_ape_mipi60"),
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat0 */
DB8500_PIN_STATE("GPIO75_H2", in_pu,
"stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", out_lo,
"stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
DB8500_PIN_STATE("GPIO155_C19", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* clk */
DB8500_PIN_STATE("GPIO156_C17", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat3 */
DB8500_PIN_STATE("GPIO157_A18", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat2 */
DB8500_PIN_STATE("GPIO158_C18", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat1 */
DB8500_PIN_STATE("GPIO159_B19", in_nopull,
"stm", "mod_mipi34_ape_mipi60"), /* dat0 */
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
};
/*
* These are specifically for the MOP500 and HREFP (pre-v60) version of the
* board, which utilized a TC35892 GPIO expander instead of using a lot of
* on-chip pins as the HREFv60 and later does.
*/
static struct pinctrl_map __initdata mop500_pinmap[] = {
/* Mux in SSP0, pull down RXD pin */
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
DB8500_PIN_HOG("GPIO145_C13", pd),
/*
* XENON Flashgun on image processor GPIO (controlled from image
* processor firmware), mux in these image processor GPIO lines 0
* (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
* the pins.
*/
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
DB8500_PIN_HOG("GPIO6_AF6", in_pu),
DB8500_PIN_HOG("GPIO7_AG5", in_pu),
/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
/* Mux in UART1 and set the pull-ups */
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
/*
* Runtime stuff: make it possible to mux in the SKE keypad
* and bias the pins
*/
/* ske default state */
DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
/* ske sleep state */
DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
/* Mux in and drive the SDI0 DAT31DIR line high at runtime */
DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
};
/*
* The HREFv60 series of platforms is using available pins on the DB8500
* insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
* and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
*/
static struct pinctrl_map __initdata hrefv60_pinmap[] = {
/* Drive WLAN_ENA low */
DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
/*
* XENON Flashgun on image processor GPIO (controlled from image
* processor firmware), mux in these image processor GPIO lines 0
* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
*/
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
/*
* Display Interface 1 uses GPIO 65 for RST (reset).
* Display Interface 2 uses GPIO 66 for RST (reset).
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
*/
DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
/*
* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
* reset signals low.
*/
DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
/*
* Drive D19-D23 for the ETM PTM trace interface low,
* (presumably pins are unconnected therefore grounded here,
* the "other alt C1" setting enables these pins)
*/
DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
/* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
/* NFC ENA and RESET to low, pulldown IRQ line */
DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
/*
* SKE keyboard partly on alt A and partly on "Other alt C1"
* Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
* rows of 6 keys, then pull up force sensing interrup and
* drive reset and force sensing WU low.
*/
DB8500_MUX_HOG("kp_a_1", "kp"),
DB8500_MUX_HOG("kp_oc1_1", "kp"),
DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
/* DiPro Sensor interrupt */
DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
/* Audio Amplifier HF enable */
DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
/* GBF interface, pull low to reset state */
DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
/* MSP : HDTV INTERFACE GPIO line */
DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
/* Accelerometer interrupt lines */
DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
/* SD card detect GPIO pin */
DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
/*
* Runtime stuff
* Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
* etc.
*/
DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
};
static struct pinctrl_map __initdata u9500_pinmap[] = {
/* Mux in UART1 (just RX/TX) and set the pull-ups */
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
DB8500_PIN_HOG("GPIO4_AH6", in_pu),
DB8500_PIN_HOG("GPIO5_AG6", out_hi),
/* WLAN_IRQ line */
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
/* HSI */
DB8500_MUX_HOG("hsir_a_1", "hsi"),
DB8500_MUX_HOG("hsit_a_2", "hsi"),
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
};
static struct pinctrl_map __initdata u8500_pinmap[] = {
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
};
static struct pinctrl_map __initdata snowball_pinmap[] = {
/* Mux in SSP0 connected to AB8500, pull down RXD pin */
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
DB8500_PIN_HOG("GPIO145_C13", pd),
/* Always drive the MC0 DAT31DIR line high on these boards */
DB8500_PIN_HOG("GPIO21_AB3", out_hi),
/* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
DB8500_MUX_HOG("sm_b_1", "sm"),
/* User LED */
DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
/* Drive RSTn_LAN high */
DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
/* Accelerometer/Magnetometer */
DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
/* WLAN/GBF */
DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
};
/*
* passing "pinsfor=" in kernel cmdline allows for custom
* configuration of GPIOs on u8500 derived boards.
*/
static int __init early_pinsfor(char *p)
{
pinsfor = PINS_FOR_DEFAULT;
if (strcmp(p, "u9500-21") == 0)
pinsfor = PINS_FOR_U9500;
return 0;
}
early_param("pinsfor", early_pinsfor);
int pins_for_u9500(void)
{
if (pinsfor == PINS_FOR_U9500)
return 1;
return 0;
}
static void __init mop500_href_family_pinmaps_init(void)
{
switch (pinsfor) {
case PINS_FOR_U9500:
pinctrl_register_mappings(u9500_pinmap,
ARRAY_SIZE(u9500_pinmap));
break;
case PINS_FOR_DEFAULT:
pinctrl_register_mappings(u8500_pinmap,
ARRAY_SIZE(u8500_pinmap));
default:
break;
}
}
void __init mop500_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(mop500_pinmap,
ARRAY_SIZE(mop500_pinmap));
mop500_href_family_pinmaps_init();
}
void __init snowball_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(snowball_pinmap,
ARRAY_SIZE(snowball_pinmap));
pinctrl_register_mappings(u8500_pinmap,
ARRAY_SIZE(u8500_pinmap));
}
void __init hrefv60_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(hrefv60_pinmap,
ARRAY_SIZE(hrefv60_pinmap));
mop500_href_family_pinmaps_init();
}

1080
arch/arm/mach-ux500/board-mop500-regulators.c Normal file
View File

File diff suppressed because it is too large Load Diff

25
arch/arm/mach-ux500/board-mop500-regulators.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
*
* Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
*
* MOP500 board specific initialization for regulators
*/
#ifndef __BOARD_MOP500_REGULATORS_H
#define __BOARD_MOP500_REGULATORS_H
#include <linux/regulator/machine.h>
#include <linux/regulator/ab8500.h>
extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
extern struct regulator_init_data tps61052_regulator;
extern struct regulator_init_data gpio_en_3v3_regulator;
extern struct regulator_init_data sdi0_reg_init_data;
void mop500_regulator_init(void);
#endif

233
arch/arm/mach-ux500/board-mop500-sdi.c Normal file
View File

@@ -0,0 +1,233 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dma-ste-dma40.h>
#include <asm/mach-types.h>
#include "devices.h"
#include "db8500-regs.h"
#include "devices-db8500.h"
#include "board-mop500.h"
#include "ste-dma40-db8500.h"
/*
* v2 has a new version of this block that need to be forced, the number found
* in hardware is incorrect
*/
#define U8500_SDI_V2_PERIPHID 0x10480180
/*
* SDI 0 (MicroSD slot)
*/
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
struct mmci_platform_data mop500_sdi0_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA |
MMC_CAP_SD_HIGHSPEED |
MMC_CAP_MMC_HIGHSPEED,
.gpio_wp = -1,
.sigdir = MCI_ST_FBCLKEN |
MCI_ST_CMDDIREN |
MCI_ST_DATA0DIREN |
MCI_ST_DATA2DIREN,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi0_dma_cfg_rx,
.dma_tx_param = &mop500_sdi0_dma_cfg_tx,
#endif
};
static void sdi0_configure(struct device *parent)
{
/* Add the device, force v2 to subrevision 1 */
db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
}
void mop500_sdi_tc35892_init(struct device *parent)
{
mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
sdi0_configure(parent);
}
/*
* SDI1 (SDIO WLAN)
*/
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
struct mmci_platform_data mop500_sdi1_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &sdi1_dma_cfg_rx,
.dma_tx_param = &sdi1_dma_cfg_tx,
#endif
};
/*
* SDI 2 (POP eMMC, not on DB8500ed)
*/
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
struct mmci_platform_data mop500_sdi2_data = {
.ocr_mask = MMC_VDD_165_195,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi2_dma_cfg_rx,
.dma_tx_param = &mop500_sdi2_dma_cfg_tx,
#endif
};
/*
* SDI 4 (on-board eMMC)
*/
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
struct mmci_platform_data mop500_sdi4_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi4_dma_cfg_rx,
.dma_tx_param = &mop500_sdi4_dma_cfg_tx,
#endif
};
void __init mop500_sdi_init(struct device *parent)
{
/* PoP:ed eMMC */
db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
/* On-board eMMC */
db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/*
* On boards with the TC35892 GPIO expander, sdi0 will finally
* be added when the TC35892 initializes and calls
* mop500_sdi_tc35892_init() above.
*/
}
void __init snowball_sdi_init(struct device *parent)
{
/* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
/* On-board eMMC */
db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true;
sdi0_configure(parent);
}
void __init hrefv60_sdi_init(struct device *parent)
{
/* PoP:ed eMMC */
db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
/* On-board eMMC */
db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
sdi0_configure(parent);
/* WLAN SDIO channel */
db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
}

120
arch/arm/mach-ux500/board-mop500-stuib.c Normal file
View File

@@ -0,0 +1,120 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL), version 2
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mfd/stmpe.h>
#include <linux/input/bu21013.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach-types.h>
#include "board-mop500.h"
/* STMPE/SKE keypad use this key layout */
static const unsigned int mop500_keymap[] = {
KEY(2, 5, KEY_END),
KEY(4, 1, KEY_POWER),
KEY(3, 5, KEY_VOLUMEDOWN),
KEY(1, 3, KEY_3),
KEY(5, 2, KEY_RIGHT),
KEY(5, 0, KEY_9),
KEY(0, 5, KEY_MENU),
KEY(7, 6, KEY_ENTER),
KEY(4, 5, KEY_0),
KEY(6, 7, KEY_2),
KEY(3, 4, KEY_UP),
KEY(3, 3, KEY_DOWN),
KEY(6, 4, KEY_SEND),
KEY(6, 2, KEY_BACK),
KEY(4, 2, KEY_VOLUMEUP),
KEY(5, 5, KEY_1),
KEY(4, 3, KEY_LEFT),
KEY(3, 2, KEY_7),
};
static const struct matrix_keymap_data mop500_keymap_data = {
.keymap = mop500_keymap,
.keymap_size = ARRAY_SIZE(mop500_keymap),
};
/*
* STMPE1601
*/
static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
.debounce_ms = 64,
.scan_count = 8,
.no_autorepeat = true,
.keymap_data = &mop500_keymap_data,
};
static struct stmpe_platform_data stmpe1601_data = {
.id = 1,
.blocks = STMPE_BLOCK_KEYPAD,
.irq_trigger = IRQF_TRIGGER_FALLING,
.irq_base = MOP500_STMPE1601_IRQ(0),
.keypad = &stmpe1601_keypad_data,
.autosleep = true,
.autosleep_timeout = 1024,
};
static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = {
{
I2C_BOARD_INFO("stmpe1601", 0x40),
.irq = NOMADIK_GPIO_TO_IRQ(218),
.platform_data = &stmpe1601_data,
.flags = I2C_CLIENT_WAKE,
},
};
/*
* BU21013 ROHM touchscreen interface on the STUIBs
*/
#define TOUCH_GPIO_PIN 84
#define TOUCH_XMAX 384
#define TOUCH_YMAX 704
#define PRCMU_CLOCK_OCR 0x1CC
#define TSC_EXT_CLOCK_9_6MHZ 0x840000
static struct bu21013_platform_device tsc_plat_device = {
.touch_pin = TOUCH_GPIO_PIN,
.touch_x_max = TOUCH_XMAX,
.touch_y_max = TOUCH_YMAX,
.ext_clk = false,
.x_flip = false,
.y_flip = true,
};
static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
{
I2C_BOARD_INFO("bu21013_tp", 0x5C),
.platform_data = &tsc_plat_device,
},
{
I2C_BOARD_INFO("bu21013_tp", 0x5D),
.platform_data = &tsc_plat_device,
},
};
void __init mop500_stuib_init(void)
{
if (machine_is_hrefv60())
tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
else
tsc_plat_device.cs_pin = GPIO_BU21013_CS;
mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
ARRAY_SIZE(mop500_i2c0_devices_stuib));
mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
ARRAY_SIZE(u8500_i2c3_devices_stuib));
}

92
arch/arm/mach-ux500/board-mop500-u8500uib.c Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Board data for the U8500 UIB, also known as the New UIB
* License terms: GNU General Public License (GPL), version 2
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/input/matrix_keypad.h>
#include "irqs.h"
#include "board-mop500.h"
static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
{
I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
.irq = NOMADIK_GPIO_TO_IRQ(84),
},
};
/*
* TC35893
*/
static const unsigned int u8500_keymap[] = {
KEY(3, 1, KEY_END),
KEY(4, 1, KEY_POWER),
KEY(6, 4, KEY_VOLUMEDOWN),
KEY(4, 2, KEY_EMAIL),
KEY(3, 3, KEY_RIGHT),
KEY(2, 5, KEY_BACKSPACE),
KEY(6, 7, KEY_MENU),
KEY(5, 0, KEY_ENTER),
KEY(4, 3, KEY_0),
KEY(3, 4, KEY_DOT),
KEY(5, 2, KEY_UP),
KEY(3, 5, KEY_DOWN),
KEY(4, 5, KEY_SEND),
KEY(0, 5, KEY_BACK),
KEY(6, 2, KEY_VOLUMEUP),
KEY(1, 3, KEY_SPACE),
KEY(7, 6, KEY_LEFT),
KEY(5, 5, KEY_SEARCH),
};
static struct matrix_keymap_data u8500_keymap_data = {
.keymap = u8500_keymap,
.keymap_size = ARRAY_SIZE(u8500_keymap),
};
static struct tc3589x_keypad_platform_data tc35893_data = {
.krow = TC_KPD_ROWS,
.kcol = TC_KPD_COLUMNS,
.debounce_period = TC_KPD_DEBOUNCE_PERIOD,
.settle_time = TC_KPD_SETTLE_TIME,
.irqtype = IRQF_TRIGGER_FALLING,
.enable_wakeup = true,
.keymap_data = &u8500_keymap_data,
.no_autorepeat = true,
};
static struct tc3589x_platform_data tc3589x_keypad_data = {
.block = TC3589x_BLOCK_KEYPAD,
.keypad = &tc35893_data,
.irq_base = MOP500_EGPIO_IRQ_BASE,
};
static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = {
{
I2C_BOARD_INFO("tc3589x", 0x44),
.platform_data = &tc3589x_keypad_data,
.irq = NOMADIK_GPIO_TO_IRQ(218),
.flags = I2C_CLIENT_WAKE,
},
};
void __init mop500_u8500uib_init(void)
{
mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
ARRAY_SIZE(mop500_i2c3_devices_u8500));
mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
ARRAY_SIZE(mop500_i2c0_devices_u8500));
}

133
arch/arm/mach-ux500/board-mop500-uib.c Normal file
View File

@@ -0,0 +1,133 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2
*/
#define pr_fmt(fmt) "mop500-uib: " fmt
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include "board-mop500.h"
#include "id.h"
enum mop500_uib {
STUIB,
U8500UIB,
};
struct uib {
const char *name;
const char *option;
void (*init)(void);
};
static struct uib __initdata mop500_uibs[] = {
[STUIB] = {
.name = "ST-UIB",
.option = "stuib",
.init = mop500_stuib_init,
},
[U8500UIB] = {
.name = "U8500-UIB",
.option = "u8500uib",
.init = mop500_u8500uib_init,
},
};
static struct uib *mop500_uib;
static int __init mop500_uib_setup(char *str)
{
int i;
for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) {
struct uib *uib = &mop500_uibs[i];
if (!strcmp(str, uib->option)) {
mop500_uib = uib;
break;
}
}
if (i == ARRAY_SIZE(mop500_uibs))
pr_err("invalid uib= option (%s)\n", str);
return 1;
}
__setup("uib=", mop500_uib_setup);
/*
* The UIBs are detected after the I2C host controllers are registered, so
* i2c_register_board_info() can't be used.
*/
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
unsigned n)
{
struct i2c_adapter *adap;
struct i2c_client *client;
int i;
adap = i2c_get_adapter(busnum);
if (!adap) {
pr_err("failed to get adapter i2c%d\n", busnum);
return;
}
for (i = 0; i < n; i++) {
client = i2c_new_device(adap, &info[i]);
if (!client)
pr_err("failed to register %s to i2c%d\n",
info[i].type, busnum);
}
i2c_put_adapter(adap);
}
static void __init __mop500_uib_init(struct uib *uib, const char *why)
{
pr_info("%s (%s)\n", uib->name, why);
uib->init();
}
/*
* Detect the UIB attached based on the presence or absence of i2c devices.
*/
int __init mop500_uib_init(void)
{
struct uib *uib = mop500_uib;
struct i2c_adapter *i2c0;
int ret;
if (!cpu_is_u8500_family())
return -ENODEV;
if (uib) {
__mop500_uib_init(uib, "from uib= boot argument");
return 0;
}
i2c0 = i2c_get_adapter(0);
if (!i2c0) {
__mop500_uib_init(&mop500_uibs[STUIB],
"fallback, could not get i2c0");
return -ENODEV;
}
/* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */
ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0,
I2C_SMBUS_QUICK, NULL);
i2c_put_adapter(i2c0);
if (ret == 0)
uib = &mop500_uibs[U8500UIB];
else
uib = &mop500_uibs[STUIB];
__mop500_uib_init(uib, "detected");
return 0;
}

767
arch/arm/mach-ux500/board-mop500.c Normal file
View File

@@ -0,0 +1,767 @@
/*
* Copyright (C) 2008-2012 ST-Ericsson
*
* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/platform_data/i2c-nomadik.h>
#include <linux/platform_data/db8500_thermal.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl022.h>
#include <linux/amba/serial.h>
#include <linux/spi/spi.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/ab8500.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/mfd/tc3589x.h>
#include <linux/mfd/tps6105x.h>
#include <linux/mfd/abx500/ab8500-gpio.h>
#include <linux/mfd/abx500/ab8500-codec.h>
#include <linux/platform_data/leds-lp55xx.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <linux/gpio_keys.h>
#include <linux/delay.h>
#include <linux/leds.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/platform_data/dma-ste-dma40.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "setup.h"
#include "devices.h"
#include "irqs.h"
#include <linux/platform_data/crypto-ux500.h>
#include "ste-dma40-db8500.h"
#include "db8500-regs.h"
#include "devices-db8500.h"
#include "board-mop500.h"
#include "board-mop500-regulators.h"
static struct gpio_led snowball_led_array[] = {
{
.name = "user_led",
.default_trigger = "heartbeat",
.gpio = 142,
},
};
static struct gpio_led_platform_data snowball_led_data = {
.leds = snowball_led_array,
.num_leds = ARRAY_SIZE(snowball_led_array),
};
static struct platform_device snowball_led_dev = {
.name = "leds-gpio",
.dev = {
.platform_data = &snowball_led_data,
},
};
static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
.supply_name = "EN-3V3",
.gpio = SNOWBALL_EN_3V3_ETH_GPIO,
.microvolts = 3300000,
.enable_high = 1,
.init_data = &gpio_en_3v3_regulator,
.startup_delay = 5000, /* 1200us */
};
static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &snowball_gpio_en_3v3_data,
},
};
/* Dynamically populated. */
static struct gpio sdi0_reg_gpios[] = {
{ 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
};
static struct gpio_regulator_state sdi0_reg_states[] = {
{ .value = 2900000, .gpios = (0 << 0) },
{ .value = 1800000, .gpios = (1 << 0) },
};
static struct gpio_regulator_config sdi0_reg_info = {
.supply_name = "ext-mmc-level-shifter",
.gpios = sdi0_reg_gpios,
.nr_gpios = ARRAY_SIZE(sdi0_reg_gpios),
.states = sdi0_reg_states,
.nr_states = ARRAY_SIZE(sdi0_reg_states),
.type = REGULATOR_VOLTAGE,
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &sdi0_reg_init_data,
.startup_delay = 100,
};
static struct platform_device sdi0_regulator = {
.name = "gpio-regulator",
.id = -1,
.dev = {
.platform_data = &sdi0_reg_info,
},
};
static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_PIN_GPIO(1),
};
/* ab8500-codec */
static struct ab8500_codec_platform_data ab8500_codec_pdata = {
.amics = {
.mic1_type = AMIC_TYPE_DIFFERENTIAL,
.mic2_type = AMIC_TYPE_DIFFERENTIAL,
.mic1a_micbias = AMIC_MICBIAS_VAMIC1,
.mic1b_micbias = AMIC_MICBIAS_VAMIC1,
.mic2_micbias = AMIC_MICBIAS_VAMIC2
},
.ear_cmv = EAR_CMV_0_95V
};
static struct gpio_keys_button snowball_key_array[] = {
{
.gpio = 32,
.type = EV_KEY,
.code = KEY_1,
.desc = "userpb",
.active_low = 1,
.debounce_interval = 50,
.wakeup = 1,
},
{
.gpio = 151,
.type = EV_KEY,
.code = KEY_2,
.desc = "extkb1",
.active_low = 1,
.debounce_interval = 50,
.wakeup = 1,
},
{
.gpio = 152,
.type = EV_KEY,
.code = KEY_3,
.desc = "extkb2",
.active_low = 1,
.debounce_interval = 50,
.wakeup = 1,
},
{
.gpio = 161,
.type = EV_KEY,
.code = KEY_4,
.desc = "extkb3",
.active_low = 1,
.debounce_interval = 50,
.wakeup = 1,
},
{
.gpio = 162,
.type = EV_KEY,
.code = KEY_5,
.desc = "extkb4",
.active_low = 1,
.debounce_interval = 50,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data snowball_key_data = {
.buttons = snowball_key_array,
.nbuttons = ARRAY_SIZE(snowball_key_array),
};
static struct platform_device snowball_key_dev = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &snowball_key_data,
}
};
static struct smsc911x_platform_config snowball_sbnet_cfg = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
.shift = 1,
};
static struct resource sbnet_res[] = {
{
.name = "smsc911x-memory",
.start = (0x5000 << 16),
.end = (0x5000 << 16) + 0xffff,
.flags = IORESOURCE_MEM,
},
{
.start = NOMADIK_GPIO_TO_IRQ(140),
.end = NOMADIK_GPIO_TO_IRQ(140),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
static struct platform_device snowball_sbnet_dev = {
.name = "smsc911x",
.num_resources = ARRAY_SIZE(sbnet_res),
.resource = sbnet_res,
.dev = {
.platform_data = &snowball_sbnet_cfg,
},
};
struct ab8500_platform_data ab8500_platdata = {
.irq_base = MOP500_AB8500_IRQ_BASE,
.regulator = &ab8500_regulator_plat_data,
.gpio = &ab8500_gpio_pdata,
.codec = &ab8500_codec_pdata,
};
static struct platform_device u8500_cpufreq_cooling_device = {
.name = "db8500-cpufreq-cooling",
};
/*
* TPS61052
*/
static struct tps6105x_platform_data mop500_tps61052_data = {
.mode = TPS6105X_MODE_VOLTAGE,
.regulator_data = &tps61052_regulator,
};
/*
* TC35892
*/
static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
{
struct device *parent = NULL;
#if 0
/* FIXME: Is the sdi actually part of tc3589x? */
parent = tc3589x->dev;
#endif
mop500_sdi_tc35892_init(parent);
}
static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
.gpio_base = MOP500_EGPIO(0),
.setup = mop500_tc35892_init,
};
static struct tc3589x_platform_data mop500_tc35892_data = {
.block = TC3589x_BLOCK_GPIO,
.gpio = &mop500_tc35892_gpio_data,
.irq_base = MOP500_EGPIO_IRQ_BASE,
};
static struct lp55xx_led_config lp5521_pri_led[] = {
[0] = {
.chan_nr = 0,
.led_current = 0x2f,
.max_current = 0x5f,
},
[1] = {
.chan_nr = 1,
.led_current = 0x2f,
.max_current = 0x5f,
},
[2] = {
.chan_nr = 2,
.led_current = 0x2f,
.max_current = 0x5f,
},
};
static struct lp55xx_platform_data __initdata lp5521_pri_data = {
.label = "lp5521_pri",
.led_config = &lp5521_pri_led[0],
.num_channels = 3,
.clock_mode = LP55XX_CLOCK_EXT,
};
static struct lp55xx_led_config lp5521_sec_led[] = {
[0] = {
.chan_nr = 0,
.led_current = 0x2f,
.max_current = 0x5f,
},
[1] = {
.chan_nr = 1,
.led_current = 0x2f,
.max_current = 0x5f,
},
[2] = {
.chan_nr = 2,
.led_current = 0x2f,
.max_current = 0x5f,
},
};
static struct lp55xx_platform_data __initdata lp5521_sec_data = {
.label = "lp5521_sec",
.led_config = &lp5521_sec_led[0],
.num_channels = 3,
.clock_mode = LP55XX_CLOCK_EXT,
};
static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
{
I2C_BOARD_INFO("tc3589x", 0x42),
.irq = NOMADIK_GPIO_TO_IRQ(217),
.platform_data = &mop500_tc35892_data,
},
/* I2C0 devices only available prior to HREFv60 */
{
I2C_BOARD_INFO("tps61052", 0x33),
.platform_data = &mop500_tps61052_data,
},
};
#define NUM_PRE_V60_I2C0_DEVICES 1
static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
{
/* lp5521 LED driver, 1st device */
I2C_BOARD_INFO("lp5521", 0x33),
.platform_data = &lp5521_pri_data,
},
{
/* lp5521 LED driver, 2st device */
I2C_BOARD_INFO("lp5521", 0x34),
.platform_data = &lp5521_sec_data,
},
{
/* Light sensor Rohm BH1780GLI */
I2C_BOARD_INFO("bh1780", 0x29),
},
};
static void __init mop500_i2c_init(struct device *parent)
{
db8500_add_i2c0(parent, NULL);
db8500_add_i2c1(parent, NULL);
db8500_add_i2c2(parent, NULL);
db8500_add_i2c3(parent, NULL);
}
static struct gpio_keys_button mop500_gpio_keys[] = {
{
.desc = "SFH7741 Proximity Sensor",
.type = EV_SW,
.code = SW_FRONT_PROXIMITY,
.active_low = 0,
.can_disable = 1,
}
};
static struct regulator *prox_regulator;
static int mop500_prox_activate(struct device *dev);
static void mop500_prox_deactivate(struct device *dev);
static struct gpio_keys_platform_data mop500_gpio_keys_data = {
.buttons = mop500_gpio_keys,
.nbuttons = ARRAY_SIZE(mop500_gpio_keys),
.enable = mop500_prox_activate,
.disable = mop500_prox_deactivate,
};
static struct platform_device mop500_gpio_keys_device = {
.name = "gpio-keys",
.id = 0,
.dev = {
.platform_data = &mop500_gpio_keys_data,
},
};
static int mop500_prox_activate(struct device *dev)
{
prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
"vcc");
if (IS_ERR(prox_regulator)) {
dev_err(&mop500_gpio_keys_device.dev,
"no regulator\n");
return PTR_ERR(prox_regulator);
}
return regulator_enable(prox_regulator);
}
static void mop500_prox_deactivate(struct device *dev)
{
regulator_disable(prox_regulator);
regulator_put(prox_regulator);
}
void mop500_snowball_ethernet_clock_enable(void)
{
struct clk *clk;
clk = clk_get_sys("fsmc", NULL);
if (!IS_ERR(clk))
clk_prepare_enable(clk);
}
static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
},
.engine_to_mem = {
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
}
};
static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_16,
.dst_info.psize = STEDMA40_PSIZE_LOG_16,
};
static struct hash_platform_data u8500_hash1_platform_data = {
.mem_to_engine = &u8500_hash_dma_cfg_tx,
.dma_filter = stedma40_filter,
};
/* add any platform devices here - TODO */
static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
&sdi0_regulator,
};
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV8_SSP0_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
#endif
struct pl022_ssp_controller ssp0_plat = {
.bus_id = 0,
#ifdef CONFIG_STE_DMA40
.enable_dma = 1,
.dma_filter = stedma40_filter,
.dma_rx_param = &ssp0_dma_cfg_rx,
.dma_tx_param = &ssp0_dma_cfg_tx,
#else
.enable_dma = 0,
#endif
/* on this platform, gpio 31,142,144,214 &
* 224 are connected as chip selects
*/
.num_chipselect = 5,
};
static void __init mop500_spi_init(struct device *parent)
{
db8500_add_ssp0(parent, &ssp0_plat);
}
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV13_UART0_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV12_UART1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV11_UART2_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
};
#endif
struct amba_pl011_data uart0_plat = {
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &uart0_dma_cfg_rx,
.dma_tx_param = &uart0_dma_cfg_tx,
#endif
};
struct amba_pl011_data uart1_plat = {
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &uart1_dma_cfg_rx,
.dma_tx_param = &uart1_dma_cfg_tx,
#endif
};
struct amba_pl011_data uart2_plat = {
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &uart2_dma_cfg_rx,
.dma_tx_param = &uart2_dma_cfg_tx,
#endif
};
static void __init mop500_uart_init(struct device *parent)
{
db8500_add_uart0(parent, &uart0_plat);
db8500_add_uart1(parent, &uart1_plat);
db8500_add_uart2(parent, &uart2_plat);
}
static void __init u8500_cryp1_hash1_init(struct device *parent)
{
db8500_add_cryp1(parent, &u8500_cryp1_platform_data);
db8500_add_hash1(parent, &u8500_hash1_platform_data);
}
static struct platform_device *snowball_platform_devs[] __initdata = {
&snowball_led_dev,
&snowball_key_dev,
&snowball_sbnet_dev,
&snowball_gpio_en_3v3_regulator_dev,
&u8500_cpufreq_cooling_device,
&sdi0_regulator,
};
static void __init mop500_init_machine(void)
{
struct device *parent = NULL;
int i2c0_devs;
int i;
platform_device_register(&db8500_prcmu_device);
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
mop500_pinmaps_init();
parent = u8500_init_devices();
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs));
mop500_i2c_init(parent);
mop500_sdi_init(parent);
mop500_spi_init(parent);
mop500_audio_init(parent);
mop500_uart_init(parent);
u8500_cryp1_hash1_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
i2c_register_board_info(2, mop500_i2c2_devices,
ARRAY_SIZE(mop500_i2c2_devices));
/* This board has full regulator constraints */
regulator_has_full_constraints();
}
static void __init snowball_init_machine(void)
{
struct device *parent = NULL;
int i;
platform_device_register(&db8500_prcmu_device);
sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
snowball_pinmaps_init();
parent = u8500_init_devices();
for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
snowball_platform_devs[i]->dev.parent = parent;
platform_add_devices(snowball_platform_devs,
ARRAY_SIZE(snowball_platform_devs));
mop500_i2c_init(parent);
snowball_sdi_init(parent);
mop500_spi_init(parent);
mop500_audio_init(parent);
mop500_uart_init(parent);
mop500_snowball_ethernet_clock_enable();
/* This board has full regulator constraints */
regulator_has_full_constraints();
}
static void __init hrefv60_init_machine(void)
{
struct device *parent = NULL;
int i2c0_devs;
int i;
platform_device_register(&db8500_prcmu_device);
/*
* The HREFv60 board removed a GPIO expander and routed
* all these GPIO pins to the internal GPIO controller
* instead.
*/
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
hrefv60_pinmaps_init();
parent = u8500_init_devices();
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs));
mop500_i2c_init(parent);
hrefv60_sdi_init(parent);
mop500_spi_init(parent);
mop500_audio_init(parent);
mop500_uart_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
i2c_register_board_info(2, mop500_i2c2_devices,
ARRAY_SIZE(mop500_i2c2_devices));
/* This board has full regulator constraints */
regulator_has_full_constraints();
}
MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
/* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
.atag_offset = 0x100,
.smp = smp_ops(ux500_smp_ops),
.map_io = u8500_map_io,
.init_irq = ux500_init_irq,
/* we re-use nomadik timer here */
.init_time = ux500_timer_init,
.init_machine = mop500_init_machine,
.init_late = ux500_init_late,
MACHINE_END
MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
.atag_offset = 0x100,
.map_io = u8500_map_io,
.init_irq = ux500_init_irq,
.init_time = ux500_timer_init,
.init_machine = mop500_init_machine,
.init_late = ux500_init_late,
MACHINE_END
MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
.atag_offset = 0x100,
.smp = smp_ops(ux500_smp_ops),
.map_io = u8500_map_io,
.init_irq = ux500_init_irq,
.init_time = ux500_timer_init,
.init_machine = hrefv60_init_machine,
.init_late = ux500_init_late,
MACHINE_END
MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
.atag_offset = 0x100,
.smp = smp_ops(ux500_smp_ops),
.map_io = u8500_map_io,
.init_irq = ux500_init_irq,
/* we re-use nomadik timer here */
.init_time = ux500_timer_init,
.init_machine = snowball_init_machine,
.init_late = NULL,
MACHINE_END

112
arch/arm/mach-ux500/board-mop500.h Normal file
View File

@@ -0,0 +1,112 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __BOARD_MOP500_H
#define __BOARD_MOP500_H
/* For NOMADIK_NR_GPIO */
#include "irqs.h"
#include <linux/platform_data/asoc-ux500-msp.h>
#include <linux/amba/mmci.h>
/* Snowball specific GPIO assignments, this board has no GPIO expander */
#define SNOWBALL_ACCEL_INT1_GPIO 163
#define SNOWBALL_ACCEL_INT2_GPIO 164
#define SNOWBALL_MAGNET_DRDY_GPIO 165
#define SNOWBALL_SDMMC_EN_GPIO 217
#define SNOWBALL_SDMMC_1V8_3V_GPIO 228
#define SNOWBALL_SDMMC_CD_GPIO 218
/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
#define HREFV60_SDMMC_1V8_3V_GPIO 5
#define HREFV60_CAMERA_FLASH_ENABLE 21
#define HREFV60_MAGNET_DRDY_GPIO 32
#define HREFV60_DISP1_RST_GPIO 65
#define HREFV60_DISP2_RST_GPIO 66
#define HREFV60_ACCEL_INT1_GPIO 82
#define HREFV60_ACCEL_INT2_GPIO 83
#define HREFV60_SDMMC_CD_GPIO 95
#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140
#define HREFV60_TOUCH_RST_GPIO 143
#define HREFV60_HAL_SW_GPIO 145
#define HREFV60_SDMMC_EN_GPIO 169
#define HREFV60_MMIO_XENON_CHARGE 170
#define HREFV60_PROX_SENSE_GPIO 217
/* MOP500 generic GPIOs */
#define CAMERA_FLASH_INT_PIN 7
#define CYPRESS_TOUCH_INT_PIN 84
#define XSHUTDOWN_PRIMARY_SENSOR 141
#define XSHUTDOWN_SECONDARY_SENSOR 142
#define CYPRESS_TOUCH_RST_GPIO 143
#define MOP500_HDMI_RST_GPIO 196
#define CYPRESS_SLAVE_SELECT_GPIO 216
/* GPIOs on the TC35892 expander */
#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x))
#define GPIO_MAGNET_DRDY MOP500_EGPIO(1)
#define GPIO_SDMMC_CD MOP500_EGPIO(3)
#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4)
#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5)
#define GPIO_PROX_SENSOR MOP500_EGPIO(7)
#define GPIO_HAL_SENSOR MOP500_EGPIO(8)
#define GPIO_ACCEL_INT1 MOP500_EGPIO(10)
#define GPIO_ACCEL_INT2 MOP500_EGPIO(11)
#define GPIO_BU21013_CS MOP500_EGPIO(13)
#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14)
#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15)
#define GPIO_SDMMC_EN MOP500_EGPIO(17)
#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18)
#define MOP500_EGPIO_END MOP500_EGPIO(24)
/*
* GPIOs on the AB8500 mixed-signals circuit
* Notice that we subtract 1 from the number passed into the macro, this is
* because the AB8500 GPIO pins are enumbered starting from 1, so the value in
* parens matches the GPIO pin number in the data sheet.
*/
#define MOP500_AB8500_PIN_GPIO(x) (MOP500_EGPIO_END + (x) - 1)
/*Snowball AB8500 GPIO */
#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */
#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */
#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */
#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */
#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */
#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */
#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
struct device;
struct i2c_board_info;
extern struct mmci_platform_data mop500_sdi0_data;
extern struct mmci_platform_data mop500_sdi1_data;
extern struct mmci_platform_data mop500_sdi2_data;
extern struct mmci_platform_data mop500_sdi4_data;
extern struct msp_i2s_platform_data msp0_platform_data;
extern struct msp_i2s_platform_data msp1_platform_data;
extern struct msp_i2s_platform_data msp2_platform_data;
extern struct msp_i2s_platform_data msp3_platform_data;
extern struct arm_pmu_platdata db8500_pmu_platdata;
extern struct amba_pl011_data uart0_plat;
extern struct amba_pl011_data uart1_plat;
extern struct amba_pl011_data uart2_plat;
extern struct pl022_ssp_controller ssp0_plat;
extern void mop500_sdi_init(struct device *parent);
extern void snowball_sdi_init(struct device *parent);
extern void hrefv60_sdi_init(struct device *parent);
extern void mop500_sdi_tc35892_init(struct device *parent);
void __init mop500_u8500uib_init(void);
void __init mop500_stuib_init(void);
void __init mop500_pinmaps_init(void);
void __init snowball_pinmaps_init(void);
void __init hrefv60_pinmaps_init(void);
void mop500_audio_init(struct device *parent);
void mop500_snowball_ethernet_clock_enable(void);
int __init mop500_uib_init(void);
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
unsigned n);
#endif

75
arch/arm/mach-ux500/cache-l2x0.c Normal file
View File

@@ -0,0 +1,75 @@
/*
* Copyright (C) ST-Ericsson SA 2011
*
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/io.h>
#include <linux/of.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include "db8500-regs.h"
#include "id.h"
static void __iomem *l2x0_base;
static int __init ux500_l2x0_unlock(void)
{
int i;
/*
* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
* apparently locks both caches before jumping to the kernel. The
* l2x0 core will not touch the unlock registers if the l2x0 is
* already enabled, so we do it right here instead. The PL310 has
* 8 sets of registers, one per possible CPU.
*/
for (i = 0; i < 8; i++) {
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
i * L2X0_LOCKDOWN_STRIDE);
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
i * L2X0_LOCKDOWN_STRIDE);
}
return 0;
}
static int __init ux500_l2x0_init(void)
{
u32 aux_val = 0x3e000000;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
/* Unlock before init */
ux500_l2x0_unlock();
/* DBx540's L2 has 128KB way size */
if (cpu_is_ux540_family())
/* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
else
/* 64KB way size */
aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
/* 64KB way size, 8 way associativity, force WA */
if (of_have_populated_dt())
l2x0_of_init(aux_val, 0xc0000fff);
else
l2x0_init(l2x0_base, aux_val, 0xc0000fff);
/*
* We can't disable l2 as we are in non secure mode, currently
* this seems be called only during kexec path. So let's
* override outer.disable with nasty assignment until we have
* some SMI service available.
*/
outer_cache.disable = NULL;
return 0;
}
early_initcall(ux500_l2x0_init);

344
arch/arm/mach-ux500/cpu-db8500.c Normal file
View File

@@ -0,0 +1,344 @@
/*
* Copyright (C) 2008-2009 ST-Ericsson SA
*
* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/regulator/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/random.h>
#include <asm/pmu.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include "setup.h"
#include "devices.h"
#include "irqs.h"
#include "devices-db8500.h"
#include "ste-dma40-db8500.h"
#include "db8500-regs.h"
#include "board-mop500.h"
#include "id.h"
/* minimum static i/o mapping required to boot U8500 platforms */
static struct map_desc u8500_uart_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
};
/* U8500 and U9540 common io_desc */
static struct map_desc u8500_common_io_desc[] __initdata = {
/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
};
/* U8500 IO map specific description */
static struct map_desc u8500_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
};
/* U9540 IO map specific description */
static struct map_desc u9540_io_desc[] __initdata = {
__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
};
void __init u8500_map_io(void)
{
/*
* Map the UARTs early so that the DEBUG_LL stuff continues to work.
*/
iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
ux500_map_io();
iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
if (cpu_is_ux540_family())
iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
else
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
}
static struct resource db8500_pmu_resources[] = {
[0] = {
.start = IRQ_DB8500_PMU,
.end = IRQ_DB8500_PMU,
.flags = IORESOURCE_IRQ,
},
};
/*
* The PMU IRQ lines of two cores are wired together into a single interrupt.
* Bounce the interrupt to the other core if it's not ours.
*/
static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
{
irqreturn_t ret = handler(irq, dev);
int other = !smp_processor_id();
if (ret == IRQ_NONE && cpu_online(other))
irq_set_affinity(irq, cpumask_of(other));
/*
* We should be able to get away with the amount of IRQ_NONEs we give,
* while still having the spurious IRQ detection code kick in if the
* interrupt really starts hitting spuriously.
*/
return ret;
}
struct arm_pmu_platdata db8500_pmu_platdata = {
.handle_irq = db8500_pmu_handler,
};
static struct platform_device db8500_pmu_device = {
.name = "arm-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(db8500_pmu_resources),
.resource = db8500_pmu_resources,
.dev.platform_data = &db8500_pmu_platdata,
};
static struct platform_device *platform_devs[] __initdata = {
&u8500_dma40_device,
&db8500_pmu_device,
};
static resource_size_t __initdata db8500_gpio_base[] = {
U8500_GPIOBANK0_BASE,
U8500_GPIOBANK1_BASE,
U8500_GPIOBANK2_BASE,
U8500_GPIOBANK3_BASE,
U8500_GPIOBANK4_BASE,
U8500_GPIOBANK5_BASE,
U8500_GPIOBANK6_BASE,
U8500_GPIOBANK7_BASE,
U8500_GPIOBANK8_BASE,
};
static void __init db8500_add_gpios(struct device *parent)
{
struct nmk_gpio_platform_data pdata = {
.supports_sleepmode = true,
};
dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
}
static int usb_db8500_rx_dma_cfg[] = {
DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
DB8500_DMA_DEV39_USB_OTG_IEP_8
};
static int usb_db8500_tx_dma_cfg[] = {
DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
DB8500_DMA_DEV39_USB_OTG_OEP_8
};
static const char *db8500_read_soc_id(void)
{
void __iomem *uid = __io_address(U8500_BB_UID_BASE);
/* Throw these device-specific numbers into the entropy pool */
add_device_randomness(uid, 0x14);
return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
readl((u32 *)uid+0),
readl((u32 *)uid+1), readl((u32 *)uid+2),
readl((u32 *)uid+3), readl((u32 *)uid+4));
}
static struct device * __init db8500_soc_device_init(void)
{
const char *soc_id = db8500_read_soc_id();
return ux500_soc_device_init(soc_id);
}
/*
* This function is called from the board init
*/
struct device * __init u8500_init_devices(void)
{
struct device *parent;
int i;
parent = db8500_soc_device_init();
db8500_add_rtc(parent);
db8500_add_gpios(parent);
db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
platform_devs[i]->dev.parent = parent;
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
return parent;
}
#ifdef CONFIG_MACH_UX500_DT
/* TODO: Once all pieces are DT:ed, remove completely. */
static struct device * __init u8500_of_init_devices(void)
{
struct device *parent = db8500_soc_device_init();
db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
u8500_dma40_device.dev.parent = parent;
/*
* Devices to be DT:ed:
* u8500_dma40_device = todo
* db8500_pmu_device = done
* db8500_prcmu_device = done
*/
platform_device_register(&u8500_dma40_device);
return parent;
}
static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
/* Requires DMA bindings. */
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
/* Requires clock name bindings. */
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
&db8500_prcmu_pdata),
OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
/* Requires device name bindings. */
OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
"pinctrl-db8500", NULL),
/* Requires clock name and DMA bindings. */
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
"ux500-msp-i2s.0", &msp0_platform_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
"ux500-msp-i2s.1", &msp1_platform_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
"ux500-msp-i2s.2", &msp2_platform_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
"ux500-msp-i2s.3", &msp3_platform_data),
{},
};
static const struct of_device_id u8500_local_bus_nodes[] = {
/* only create devices below soc node */
{ .compatible = "stericsson,db8500", },
{ .compatible = "stericsson,db8500-prcmu", },
{ .compatible = "simple-bus"},
{ },
};
static void __init u8500_init_machine(void)
{
struct device *parent = NULL;
/* Pinmaps must be in place before devices register */
if (of_machine_is_compatible("st-ericsson,mop500"))
mop500_pinmaps_init();
else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
snowball_pinmaps_init();
mop500_snowball_ethernet_clock_enable();
} else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
hrefv60_pinmaps_init();
else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
/* TODO: Add pinmaps for ccu9540 board. */
/* TODO: Export SoC, USB, cpu-freq and DMA40 */
parent = u8500_of_init_devices();
/* automatically probe child nodes of db8500 device */
of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
}
static const char * stericsson_dt_platform_compat[] = {
"st-ericsson,u8500",
"st-ericsson,u8540",
"st-ericsson,u9500",
"st-ericsson,u9540",
NULL,
};
DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
.smp = smp_ops(ux500_smp_ops),
.map_io = u8500_map_io,
.init_irq = ux500_init_irq,
/* we re-use nomadik timer here */
.init_time = ux500_timer_init,
.init_machine = u8500_init_machine,
.init_late = NULL,
.dt_compat = stericsson_dt_platform_compat,
MACHINE_END
#endif

161
arch/arm/mach-ux500/cpu.c Normal file
View File

@@ -0,0 +1,161 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/clksrc-dbx500-prcmu.h>
#include <linux/sys_soc.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/platform_data/clk-ux500.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include <asm/mach/map.h>
#include "setup.h"
#include "devices.h"
#include "board-mop500.h"
#include "db8500-regs.h"
#include "id.h"
/*
* FIXME: Should we set up the GPIO domain here?
*
* The problem is that we cannot put the interrupt resources into the platform
* device until the irqdomain has been added. Right now, we set the GIC interrupt
* domain from init_irq(), then load the gpio driver from
* core_initcall(nmk_gpio_init) and add the platform devices from
* arch_initcall(customize_machine).
*
* This feels fragile because it depends on the gpio device getting probed
* _before_ any device uses the gpio interrupts.
*/
void __init ux500_init_irq(void)
{
void __iomem *dist_base;
void __iomem *cpu_base;
gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
ux500_unknown_soc();
#ifdef CONFIG_OF
if (of_have_populated_dt())
irqchip_init();
else
#endif
gic_init(0, 29, dist_base, cpu_base);
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
if (cpu_is_u8500_family()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE);
} else if (cpu_is_u9540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE);
} else if (cpu_is_u8540()) {
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
u8540_clk_init();
}
}
void __init ux500_init_late(void)
{
mop500_uib_init();
}
static const char * __init ux500_get_machine(void)
{
return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
}
static const char * __init ux500_get_family(void)
{
return kasprintf(GFP_KERNEL, "ux500");
}
static const char * __init ux500_get_revision(void)
{
unsigned int rev = dbx500_revision();
if (rev == 0x01)
return kasprintf(GFP_KERNEL, "%s", "ED");
else if (rev >= 0xA0)
return kasprintf(GFP_KERNEL, "%d.%d",
(rev >> 4) - 0xA + 1, rev & 0xf);
return kasprintf(GFP_KERNEL, "%s", "Unknown");
}
static ssize_t ux500_get_process(struct device *dev,
struct device_attribute *attr,
char *buf)
{
if (dbx500_id.process == 0x00)
return sprintf(buf, "Standard\n");
return sprintf(buf, "%02xnm\n", dbx500_id.process);
}
static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
const char *soc_id)
{
soc_dev_attr->soc_id = soc_id;
soc_dev_attr->machine = ux500_get_machine();
soc_dev_attr->family = ux500_get_family();
soc_dev_attr->revision = ux500_get_revision();
}
struct device_attribute ux500_soc_attr =
__ATTR(process, S_IRUGO, ux500_get_process, NULL);
struct device * __init ux500_soc_device_init(const char *soc_id)
{
struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return ERR_PTR(-ENOMEM);
soc_info_populate(soc_dev_attr, soc_id);
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return NULL;
}
parent = soc_device_to_device(soc_dev);
device_create_file(parent, &ux500_soc_attr);
return parent;
}

128
arch/arm/mach-ux500/cpuidle.c Normal file
View File

@@ -0,0 +1,128 @@
/*
* Copyright (c) 2012 Linaro : Daniel Lezcano <daniel.lezcano@linaro.org> (IBM)
*
* Based on the work of Rickard Andersson <rickard.andersson@stericsson.com>
* and Jonas Aaberg <jonas.aberg@stericsson.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/cpuidle.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <linux/smp.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include "db8500-regs.h"
#include "id.h"
static atomic_t master = ATOMIC_INIT(0);
static DEFINE_SPINLOCK(master_lock);
static inline int ux500_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
int this_cpu = smp_processor_id();
bool recouple = false;
if (atomic_inc_return(&master) == num_online_cpus()) {
/* With this lock, we prevent the other cpu to exit and enter
* this function again and become the master */
if (!spin_trylock(&master_lock))
goto wfi;
/* decouple the gic from the A9 cores */
if (prcmu_gic_decouple()) {
spin_unlock(&master_lock);
goto out;
}
/* If an error occur, we will have to recouple the gic
* manually */
recouple = true;
/* At this state, as the gic is decoupled, if the other
* cpu is in WFI, we have the guarantee it won't be wake
* up, so we can safely go to retention */
if (!prcmu_is_cpu_in_wfi(this_cpu ? 0 : 1))
goto out;
/* The prcmu will be in charge of watching the interrupts
* and wake up the cpus */
if (prcmu_copy_gic_settings())
goto out;
/* Check in the meantime an interrupt did
* not occur on the gic ... */
if (prcmu_gic_pending_irq())
goto out;
/* ... and the prcmu */
if (prcmu_pending_irq())
goto out;
/* Go to the retention state, the prcmu will wait for the
* cpu to go WFI and this is what happens after exiting this
* 'master' critical section */
if (prcmu_set_power_state(PRCMU_AP_IDLE, true, true))
goto out;
/* When we switch to retention, the prcmu is in charge
* of recoupling the gic automatically */
recouple = false;
spin_unlock(&master_lock);
}
wfi:
cpu_do_idle();
out:
atomic_dec(&master);
if (recouple) {
prcmu_gic_recouple();
spin_unlock(&master_lock);
}
return index;
}
static struct cpuidle_driver ux500_idle_driver = {
.name = "ux500_idle",
.owner = THIS_MODULE,
.states = {
ARM_CPUIDLE_WFI_STATE,
{
.enter = ux500_enter_idle,
.exit_latency = 70,
.target_residency = 260,
.flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_TIMER_STOP,
.name = "ApIdle",
.desc = "ARM Retention",
},
},
.safe_state_index = 0,
.state_count = 2,
};
int __init ux500_idle_init(void)
{
if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
return -ENODEV;
/* Configure wake up reasons */
prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
PRCMU_WAKEUP(ABB));
return cpuidle_register(&ux500_idle_driver, NULL);
}
device_initcall(ux500_idle_init);

201
arch/arm/mach-ux500/db8500-regs.h Normal file
View File

@@ -0,0 +1,201 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __MACH_DB8500_REGS_H
#define __MACH_DB8500_REGS_H
/* Base address and bank offsets for ESRAM */
#define U8500_ESRAM_BASE 0x40000000
#define U8500_ESRAM_BANK_SIZE 0x00020000
#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
/*
* on V1 DMA uses 4KB for logical parameters position is right after the 64KB
* reserved for security
*/
#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
/* This address fulfills the 256k alignment requirement of the lcla base */
#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
#define U8500_PER3_BASE 0x80000000
#define U8500_STM_BASE 0x80100000
#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
#define U8500_PER2_BASE 0x80110000
#define U8500_PER1_BASE 0x80120000
#define U8500_B2R2_BASE 0x80130000
#define U8500_HSEM_BASE 0x80140000
#define U8500_PER4_BASE 0x80150000
#define U8500_TPIU_BASE 0x80190000
#define U8500_ICN_BASE 0x81000000
#define U8500_BOOT_ROM_BASE 0x90000000
/* ASIC ID is at 0xbf4 offset within this region */
#define U8500_ASIC_ID_BASE 0x9001D000
#define U9540_BOOT_ROM_BASE 0xFFFE0000
/* ASIC ID is at 0xbf4 offset within this region */
#define U9540_ASIC_ID_BASE 0xFFFFD000
#define U8500_PER6_BASE 0xa03c0000
#define U8500_PER7_BASE 0xa03d0000
#define U8500_PER5_BASE 0xa03e0000
#define U8500_SVA_BASE 0xa0100000
#define U8500_SIA_BASE 0xa0200000
#define U8500_SGA_BASE 0xa0300000
#define U8500_MCDE_BASE 0xa0350000
#define U8500_DMA_BASE 0x801C0000 /* v1 */
#define U8500_SBAG_BASE 0xa0390000
#define U8500_SCU_BASE 0xa0410000
#define U8500_GIC_CPU_BASE 0xa0410100
#define U8500_TWD_BASE 0xa0410600
#define U8500_GIC_DIST_BASE 0xa0411000
#define U8500_L2CC_BASE 0xa0412000
#define U8500_MODEM_I2C 0xb7e02000
#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
/* per6 base addresses */
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
/* per5 base addresses */
#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
/* per4 base addresses */
#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000)
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
#define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000)
#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
/* per3 base addresses */
#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
/* per2 base addresses */
#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
/* per1 base addresses */
#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
#define U8500_MCDE_SIZE 0x1000
#define U8500_DSI_LINK_SIZE 0x1000
#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
#define U8500_DSI_LINK_COUNT 0x3
/* Modem and APE physical addresses */
#define U8500_MODEM_BASE 0xe000000
#define U8500_APE_BASE 0x6000000
/* SoC identification number information */
#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
/* Offsets to specific addresses in some IP blocks for DMA */
#define MSP_TX_RX_REG_OFFSET 0
#define CRYP1_RX_REG_OFFSET 0x10
#define CRYP1_TX_REG_OFFSET 0x8
#define HASH1_TX_REG_OFFSET 0x4
/*
* Macros to get at IO space when running virtually
* We dont map all the peripherals, let ioremap do
* this for us. We map only very basic peripherals here.
*/
#define U8500_IO_VIRTUAL 0xf0000000
#define U8500_IO_PHYSICAL 0xa0000000
/* This is where we map in the ROM to check ASIC IDs */
#define UX500_VIRT_ROM 0xf0000000
/* This macro is used in assembly, so no cast */
#define IO_ADDRESS(x) \
(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
/* typesafe io address */
#define __io_address(n) IOMEM(IO_ADDRESS(n))
/* Used by some plat-nomadik code */
#define io_p2v(n) __io_address(n)
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
#endif

60
arch/arm/mach-ux500/devices-common.c Normal file
View File

@@ -0,0 +1,60 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include "irqs.h"
#include "devices-common.h"
static struct platform_device *
dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
struct nmk_gpio_platform_data *pdata)
{
struct resource resources[] = {
{
.start = addr,
.end = addr + 127,
.flags = IORESOURCE_MEM,
},
{
.start = irq,
.end = irq,
.flags = IORESOURCE_IRQ,
}
};
return platform_device_register_resndata(
parent,
"gpio",
id,
resources,
ARRAY_SIZE(resources),
pdata,
sizeof(*pdata));
}
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
int irq, struct nmk_gpio_platform_data *pdata)
{
int first = 0;
int i;
for (i = 0; i < num; i++, first += 32, irq++) {
pdata->first_gpio = first;
pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
pdata->num_gpio = 32;
dbx500_add_gpio(parent, i, base[i], irq, pdata);
}
}

149
arch/arm/mach-ux500/devices-common.h Normal file
View File

@@ -0,0 +1,149 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2.
*/
#ifndef __DEVICES_COMMON_H
#define __DEVICES_COMMON_H
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
#include <linux/amba/bus.h>
#include <linux/platform_data/i2c-nomadik.h>
#include <linux/platform_data/crypto-ux500.h>
struct spi_master_cntlr;
static inline struct amba_device *
dbx500_add_msp_spi(struct device *parent, const char *name,
resource_size_t base, int irq,
struct spi_master_cntlr *pdata)
{
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
pdata, 0);
}
static inline struct amba_device *
dbx500_add_spi(struct device *parent, const char *name, resource_size_t base,
int irq, struct spi_master_cntlr *pdata,
u32 periphid)
{
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
pdata, periphid);
}
struct mmci_platform_data;
static inline struct amba_device *
dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
int irq, struct mmci_platform_data *pdata, u32 periphid)
{
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
pdata, periphid);
}
struct amba_pl011_data;
static inline struct amba_device *
dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
int irq, struct amba_pl011_data *pdata)
{
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
}
struct nmk_i2c_controller;
static inline struct amba_device *
dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
struct nmk_i2c_controller *data)
{
/* Conjure a name similar to what the platform device used to have */
char name[16];
snprintf(name, sizeof(name), "nmk-i2c.%d", id);
return amba_apb_device_add(parent, name, base, SZ_4K, irq, 0, data, 0);
}
static inline struct amba_device *
dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
{
return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq,
0, NULL, 0);
}
struct cryp_platform_data;
static inline struct platform_device *
dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq,
struct cryp_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
DEFINE_RES_IRQ(irq),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "cryp1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct hash_platform_data;
static inline struct platform_device *
dbx500_add_hash1(struct device *parent, int id, resource_size_t base,
struct hash_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "hash1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct nmk_gpio_platform_data;
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
int irq, struct nmk_gpio_platform_data *pdata);
static inline void
dbx500_add_pinctrl(struct device *parent, const char *name,
resource_size_t base)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_8K),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = name,
.id = -1,
.res = res,
.num_res = ARRAY_SIZE(res),
};
platform_device_register_full(&pdevinfo);
}
#endif

242
arch/arm/mach-ux500/devices-db8500.c Normal file
View File

@@ -0,0 +1,242 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl022.h>
#include <linux/platform_data/dma-ste-dma40.h>
#include <linux/mfd/dbx500-prcmu.h>
#include "setup.h"
#include "irqs.h"
#include "db8500-regs.h"
#include "devices-db8500.h"
#include "ste-dma40-db8500.h"
static struct resource dma40_resources[] = {
[0] = {
.start = U8500_DMA_BASE,
.end = U8500_DMA_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "base",
},
[1] = {
.start = U8500_DMA_LCPA_BASE,
.end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
.flags = IORESOURCE_MEM,
.name = "lcpa",
},
[2] = {
.start = IRQ_DB8500_DMA,
.end = IRQ_DB8500_DMA,
.flags = IORESOURCE_IRQ,
}
};
/* Default configuration for physcial memcpy */
struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
.mode = STEDMA40_MODE_PHYSICAL,
.dir = STEDMA40_MEM_TO_MEM,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.src_info.psize = STEDMA40_PSIZE_PHY_1,
.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.psize = STEDMA40_PSIZE_PHY_1,
.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
};
/* Default configuration for logical memcpy */
struct stedma40_chan_cfg dma40_memcpy_conf_log = {
.dir = STEDMA40_MEM_TO_MEM,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.src_info.psize = STEDMA40_PSIZE_LOG_1,
.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
.dst_info.data_width = STEDMA40_BYTE_WIDTH,
.dst_info.psize = STEDMA40_PSIZE_LOG_1,
.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
};
/*
* Mapping between destination event lines and physical device address.
* The event line is tied to a device and therefore the address is constant.
* When the address comes from a primecell it will be configured in runtime
* and we set the address to -1 as a placeholder.
*/
static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
/* MUSB - these will be runtime-reconfigured */
[DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
[DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
[DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
[DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
[DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
[DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
[DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
[DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
/* PrimeCells - run-time configured */
[DB8500_DMA_DEV0_SPI0_TX] = -1,
[DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
[DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
[DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
[DB8500_DMA_DEV8_SSP0_TX] = -1,
[DB8500_DMA_DEV9_SSP1_TX] = -1,
[DB8500_DMA_DEV11_UART2_TX] = -1,
[DB8500_DMA_DEV12_UART1_TX] = -1,
[DB8500_DMA_DEV13_UART0_TX] = -1,
[DB8500_DMA_DEV28_SD_MM2_TX] = -1,
[DB8500_DMA_DEV29_SD_MM0_TX] = -1,
[DB8500_DMA_DEV32_SD_MM1_TX] = -1,
[DB8500_DMA_DEV33_SPI2_TX] = -1,
[DB8500_DMA_DEV35_SPI1_TX] = -1,
[DB8500_DMA_DEV40_SPI3_TX] = -1,
[DB8500_DMA_DEV41_SD_MM3_TX] = -1,
[DB8500_DMA_DEV42_SD_MM4_TX] = -1,
[DB8500_DMA_DEV43_SD_MM5_TX] = -1,
[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
};
/* Mapping between source event lines and physical device address */
static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
/* MUSB - these will be runtime-reconfigured */
[DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
[DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
[DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
[DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
[DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
[DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
[DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
[DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
/* PrimeCells */
[DB8500_DMA_DEV0_SPI0_RX] = -1,
[DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
[DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
[DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
[DB8500_DMA_DEV8_SSP0_RX] = -1,
[DB8500_DMA_DEV9_SSP1_RX] = -1,
[DB8500_DMA_DEV11_UART2_RX] = -1,
[DB8500_DMA_DEV12_UART1_RX] = -1,
[DB8500_DMA_DEV13_UART0_RX] = -1,
[DB8500_DMA_DEV28_SD_MM2_RX] = -1,
[DB8500_DMA_DEV29_SD_MM0_RX] = -1,
[DB8500_DMA_DEV32_SD_MM1_RX] = -1,
[DB8500_DMA_DEV33_SPI2_RX] = -1,
[DB8500_DMA_DEV35_SPI1_RX] = -1,
[DB8500_DMA_DEV40_SPI3_RX] = -1,
[DB8500_DMA_DEV41_SD_MM3_RX] = -1,
[DB8500_DMA_DEV42_SD_MM4_RX] = -1,
[DB8500_DMA_DEV43_SD_MM5_RX] = -1,
[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
};
/* Reserved event lines for memcpy only */
static int dma40_memcpy_event[] = {
DB8500_DMA_MEMCPY_TX_0,
DB8500_DMA_MEMCPY_TX_1,
DB8500_DMA_MEMCPY_TX_2,
DB8500_DMA_MEMCPY_TX_3,
DB8500_DMA_MEMCPY_TX_4,
DB8500_DMA_MEMCPY_TX_5,
};
static struct stedma40_platform_data dma40_plat_data = {
.dev_len = DB8500_DMA_NR_DEV,
.dev_rx = dma40_rx_map,
.dev_tx = dma40_tx_map,
.memcpy = dma40_memcpy_event,
.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
.memcpy_conf_phy = &dma40_memcpy_conf_phy,
.memcpy_conf_log = &dma40_memcpy_conf_log,
.disabled_channels = {-1},
};
struct platform_device u8500_dma40_device = {
.dev = {
.platform_data = &dma40_plat_data,
},
.name = "dma40",
.id = 0,
.num_resources = ARRAY_SIZE(dma40_resources),
.resource = dma40_resources
};
struct resource keypad_resources[] = {
[0] = {
.start = U8500_SKE_BASE,
.end = U8500_SKE_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DB8500_KB,
.end = IRQ_DB8500_KB,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device u8500_ske_keypad_device = {
.name = "nmk-ske-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(keypad_resources),
.resource = keypad_resources,
};
struct prcmu_pdata db8500_prcmu_pdata = {
.ab_platdata = &ab8500_platdata,
.ab_irq = IRQ_DB8500_AB8500,
.irq_base = IRQ_PRCMU_BASE,
.version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
.legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
};
static struct resource db8500_prcmu_res[] = {
{
.name = "prcmu",
.start = U8500_PRCMU_BASE,
.end = U8500_PRCMU_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "prcmu-tcdm",
.start = U8500_PRCMU_TCDM_BASE,
.end = U8500_PRCMU_TCDM_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "irq",
.start = IRQ_DB8500_PRCMU1,
.end = IRQ_DB8500_PRCMU1,
.flags = IORESOURCE_IRQ,
},
{
.name = "prcmu-tcpm",
.start = U8500_PRCMU_TCPM_BASE,
.end = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device db8500_prcmu_device = {
.name = "db8500-prcmu",
.resource = db8500_prcmu_res,
.num_resources = ARRAY_SIZE(db8500_prcmu_res),
.dev = {
.platform_data = &db8500_prcmu_pdata,
},
};

129
arch/arm/mach-ux500/devices-db8500.h Normal file
View File

@@ -0,0 +1,129 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2.
*/
#ifndef __DEVICES_DB8500_H
#define __DEVICES_DB8500_H
#include <linux/platform_data/usb-musb-ux500.h>
#include "irqs.h"
#include "db8500-regs.h"
#include "devices-common.h"
struct ske_keypad_platform_data;
struct pl022_ssp_controller;
struct platform_device;
extern struct ab8500_platform_data ab8500_platdata;
extern struct prcmu_pdata db8500_prcmu_pdata;
extern struct platform_device db8500_prcmu_device;
static inline struct platform_device *
db8500_add_ske_keypad(struct device *parent,
struct ske_keypad_platform_data *pdata,
size_t size)
{
struct resource resources[] = {
DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K),
DEFINE_RES_IRQ(IRQ_DB8500_KB),
};
return platform_device_register_resndata(parent, "nmk-ske-keypad", -1,
resources, 2, pdata, size);
}
static inline struct amba_device *
db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
int irq, struct pl022_ssp_controller *pdata)
{
return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
}
#define db8500_add_i2c0(parent, pdata) \
dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
#define db8500_add_i2c1(parent, pdata) \
dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
#define db8500_add_i2c2(parent, pdata) \
dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
#define db8500_add_i2c3(parent, pdata) \
dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
#define db8500_add_i2c4(parent, pdata) \
dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
#define db8500_add_msp0_spi(parent, pdata) \
dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
IRQ_DB8500_MSP0, pdata)
#define db8500_add_msp1_spi(parent, pdata) \
dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \
IRQ_DB8500_MSP1, pdata)
#define db8500_add_msp2_spi(parent, pdata) \
dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \
IRQ_DB8500_MSP2, pdata)
#define db8500_add_msp3_spi(parent, pdata) \
dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \
IRQ_DB8500_MSP1, pdata)
#define db8500_add_rtc(parent) \
dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC);
#define db8500_add_usb(parent, rx_cfg, tx_cfg) \
ux500_add_usb(parent, U8500_USBOTG_BASE, \
IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
#define db8500_add_sdi0(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \
IRQ_DB8500_SDMMC0, pdata, pid)
#define db8500_add_sdi1(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \
IRQ_DB8500_SDMMC1, pdata, pid)
#define db8500_add_sdi2(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \
IRQ_DB8500_SDMMC2, pdata, pid)
#define db8500_add_sdi3(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \
IRQ_DB8500_SDMMC3, pdata, pid)
#define db8500_add_sdi4(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \
IRQ_DB8500_SDMMC4, pdata, pid)
#define db8500_add_sdi5(parent, pdata, pid) \
dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \
IRQ_DB8500_SDMMC5, pdata, pid)
#define db8500_add_ssp0(parent, pdata) \
db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \
IRQ_DB8500_SSP0, pdata)
#define db8500_add_ssp1(parent, pdata) \
db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \
IRQ_DB8500_SSP1, pdata)
#define db8500_add_spi0(parent, pdata) \
dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \
IRQ_DB8500_SPI0, pdata, 0)
#define db8500_add_spi1(parent, pdata) \
dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \
IRQ_DB8500_SPI1, pdata, 0)
#define db8500_add_spi2(parent, pdata) \
dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \
IRQ_DB8500_SPI2, pdata, 0)
#define db8500_add_spi3(parent, pdata) \
dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \
IRQ_DB8500_SPI3, pdata, 0)
#define db8500_add_uart0(parent, pdata) \
dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \
IRQ_DB8500_UART0, pdata)
#define db8500_add_uart1(parent, pdata) \
dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \
IRQ_DB8500_UART1, pdata)
#define db8500_add_uart2(parent, pdata) \
dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
IRQ_DB8500_UART2, pdata)
#define db8500_add_cryp1(parent, pdata) \
dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata)
#define db8500_add_hash1(parent, pdata) \
dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata)
#endif

26
arch/arm/mach-ux500/devices.c Normal file
View File

@@ -0,0 +1,26 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/amba/bus.h>
#include "setup.h"
#include "db8500-regs.h"
void __init amba_add_devices(struct amba_device *devs[], int num)
{
int i;
for (i = 0; i < num; i++) {
struct amba_device *d = devs[i];
amba_device_register(d, &iomem_resource);
}
}

23
arch/arm/mach-ux500/devices.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __ASM_ARCH_DEVICES_H__
#define __ASM_ARCH_DEVICES_H__
struct platform_device;
struct amba_device;
extern struct platform_device u8500_gpio_devs[];
extern struct amba_device ux500_pl031_device;
extern struct platform_device ux500_hash1_device;
extern struct platform_device ux500_cryp1_device;
extern struct platform_device u8500_dma40_device;
extern struct platform_device ux500_ske_keypad_device;
#endif

39
arch/arm/mach-ux500/headsmp.S Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2009 ST-Ericsson
* This file is based ARM Realview platform
* Copyright (c) 2003 ARM Limited
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__INIT
/*
* U8500 specific entry point for secondary CPUs.
*/
ENTRY(u8500_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
add r6, r6, r4
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(u8500_secondary_startup)
.align 2
1: .long .
.long pen_release

37
arch/arm/mach-ux500/hotplug.c Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (C) STMicroelectronics 2009
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Based on ARM realview platform
*
* Author: Sundar Iyer <sundar.iyer@stericsson.com>
*
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "setup.h"
/*
* platform-specific code to shutdown a CPU
*
* Called with IRQs disabled
*/
void __ref ux500_cpu_die(unsigned int cpu)
{
/* directly enter low power state, skipping secure registers */
for (;;) {
__asm__ __volatile__("dsb\n\t" "wfi\n\t"
: : : "memory");
if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
break;
}
}
}

116
arch/arm/mach-ux500/id.c Normal file
View File

@@ -0,0 +1,116 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/cputype.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include "setup.h"
#include "db8500-regs.h"
#include "id.h"
struct dbx500_asic_id dbx500_id;
static unsigned int ux500_read_asicid(phys_addr_t addr)
{
phys_addr_t base = addr & ~0xfff;
struct map_desc desc = {
.virtual = UX500_VIRT_ROM,
.pfn = __phys_to_pfn(base),
.length = SZ_16K,
.type = MT_DEVICE,
};
iotable_init(&desc, 1);
/* As in devicemaps_init() */
local_flush_tlb_all();
flush_cache_all();
return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
}
static void ux500_print_soc_info(unsigned int asicid)
{
unsigned int rev = dbx500_revision();
pr_info("DB%4x ", dbx500_partnumber());
if (rev == 0x01)
pr_cont("Early Drop");
else if (rev >= 0xA0)
pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf);
else
pr_cont("Unknown");
pr_cont(" [%#010x]\n", asicid);
}
static unsigned int partnumber(unsigned int asicid)
{
return (asicid >> 8) & 0xffff;
}
/*
* SOC MIDR ASICID ADDRESS ASICID VALUE
* DB8500ed 0x410fc090 0x9001FFF4 0x00850001
* DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
* DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
* DB8500v2 0x412fc091 0x9001DBF4 0x008500B0
* DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2
* DB5500v1 0x412fc091 0x9001FFF4 0x005500A0
* DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
*/
void __init ux500_map_io(void)
{
unsigned int cpuid = read_cpuid_id();
unsigned int asicid = 0;
phys_addr_t addr = 0;
switch (cpuid) {
case 0x410fc090: /* DB8500ed */
case 0x411fc091: /* DB8500v1 */
addr = 0x9001FFF4;
break;
case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
asicid = ux500_read_asicid(0x9001DBF4);
if (partnumber(asicid) == 0x8500 ||
partnumber(asicid) == 0x8520)
/* DB8500v2 */
break;
/* DB5500v1 */
addr = 0x9001FFF4;
break;
case 0x413fc090: /* DB9540 */
addr = 0xFFFFDBF4;
break;
}
if (addr)
asicid = ux500_read_asicid(addr);
if (!asicid) {
pr_err("Unable to identify SoC\n");
ux500_unknown_soc();
}
dbx500_id.process = asicid >> 24;
dbx500_id.partnumber = partnumber(asicid);
dbx500_id.revision = asicid & 0xff;
ux500_print_soc_info(asicid);
}

144
arch/arm/mach-ux500/id.h Normal file
View File

@@ -0,0 +1,144 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __MACH_UX500_ID
#define __MACH_UX500_ID
/**
* struct dbx500_asic_id - fields of the ASIC ID
* @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard"
* @partnumber: hithereto 0x8500 for DB8500
* @revision: version code in the series
*/
struct dbx500_asic_id {
u16 partnumber;
u8 revision;
u8 process;
};
extern struct dbx500_asic_id dbx500_id;
static inline unsigned int __attribute_const__ dbx500_partnumber(void)
{
return dbx500_id.partnumber;
}
static inline unsigned int __attribute_const__ dbx500_revision(void)
{
return dbx500_id.revision;
}
/*
* SOCs
*/
static inline bool __attribute_const__ cpu_is_u8500(void)
{
return dbx500_partnumber() == 0x8500;
}
static inline bool __attribute_const__ cpu_is_u8520(void)
{
return dbx500_partnumber() == 0x8520;
}
static inline bool cpu_is_u8500_family(void)
{
return cpu_is_u8500() || cpu_is_u8520();
}
static inline bool __attribute_const__ cpu_is_u9540(void)
{
return dbx500_partnumber() == 0x9540;
}
static inline bool __attribute_const__ cpu_is_u8540(void)
{
return dbx500_partnumber() == 0x8540;
}
static inline bool __attribute_const__ cpu_is_u8580(void)
{
return dbx500_partnumber() == 0x8580;
}
static inline bool cpu_is_ux540_family(void)
{
return cpu_is_u9540() || cpu_is_u8540() || cpu_is_u8580();
}
/*
* 8500 revisions
*/
static inline bool __attribute_const__ cpu_is_u8500ed(void)
{
return cpu_is_u8500() && dbx500_revision() == 0x00;
}
static inline bool __attribute_const__ cpu_is_u8500v1(void)
{
return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0;
}
static inline bool __attribute_const__ cpu_is_u8500v10(void)
{
return cpu_is_u8500() && dbx500_revision() == 0xA0;
}
static inline bool __attribute_const__ cpu_is_u8500v11(void)
{
return cpu_is_u8500() && dbx500_revision() == 0xA1;
}
static inline bool __attribute_const__ cpu_is_u8500v2(void)
{
return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
}
static inline bool cpu_is_u8500v20(void)
{
return cpu_is_u8500() && (dbx500_revision() == 0xB0);
}
static inline bool cpu_is_u8500v21(void)
{
return cpu_is_u8500() && (dbx500_revision() == 0xB1);
}
static inline bool cpu_is_u8500v22(void)
{
return cpu_is_u8500() && (dbx500_revision() == 0xB2);
}
static inline bool cpu_is_u8500v20_or_later(void)
{
return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
}
/*
* 8540 revisions
*/
static inline bool __attribute_const__ cpu_is_u8540v10(void)
{
return cpu_is_u8540() && dbx500_revision() == 0xA0;
}
static inline bool __attribute_const__ cpu_is_u8580v10(void)
{
return cpu_is_u8580() && dbx500_revision() == 0xA0;
}
static inline bool ux500_is_svp(void)
{
return false;
}
#define ux500_unknown_soc() BUG()
#endif

55
arch/arm/mach-ux500/irqs-board-mop500.h Normal file
View File

@@ -0,0 +1,55 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __MACH_IRQS_BOARD_MOP500_H
#define __MACH_IRQS_BOARD_MOP500_H
/* Number of AB8500 irqs is taken from header file */
#include <linux/mfd/abx500/ab8500.h>
#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START
#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \
+ AB8500_MAX_NR_IRQS)
/* TC35892 */
#define TC35892_NR_INTERNAL_IRQS 8
#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
#define TC35892_NR_GPIOS 24
#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS
#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END
#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \
+ MOP500_EGPIO_NR_IRQS)
/* STMPE1601 irqs */
#define STMPE_NR_INTERNAL_IRQS 9
#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
#define STMPE_NR_GPIOS 24
#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END
#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x))
#define MOP500_STMPE1601_IRQ_END \
MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END
#define MOP500_IRQ_END MOP500_NR_IRQS
/*
* We may have several boards, but only one will run at a
* time, so the one with most IRQs will bump this ahead,
* but the IRQ_BOARD_START remains the same for either board.
*/
#if MOP500_IRQ_END > IRQ_BOARD_END
#undef IRQ_BOARD_END
#define IRQ_BOARD_END MOP500_IRQ_END
#endif
#endif

125
arch/arm/mach-ux500/irqs-db8500.h Normal file
View File

@@ -0,0 +1,125 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __MACH_IRQS_DB8500_H
#define __MACH_IRQS_DB8500_H
#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4)
#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6)
#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7)
#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8)
#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9)
#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10)
#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11)
#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12)
#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13)
#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14)
#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15)
#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16)
#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17)
#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18)
#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19)
#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20)
#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21)
#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22)
#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23)
#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24)
#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25)
#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26)
#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27)
#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28)
#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29)
#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31)
#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36)
#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37)
#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38)
#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39)
#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40)
#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41)
#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42)
#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43)
#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44)
#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45)
#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46)
#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47)
#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48)
#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49)
#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50)
#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51)
#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52)
#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53)
#define IRQ_DB8500_KB (IRQ_SHPI_START + 54)
#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55)
#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56)
#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57)
#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59)
#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60)
#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61)
#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62)
#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63)
#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96)
#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97)
#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98)
#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99)
#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100)
#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104)
#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105)
#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106)
#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107)
#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108)
#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109)
#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110)
#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112)
#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113)
#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114)
#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115)
#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116)
#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118)
#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119)
#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120)
#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121)
#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122)
#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123)
#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124)
#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125)
#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71)
#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66)
#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64)
#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67)
#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65)
#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83)
#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78)
#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76)
#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79)
#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77)
#ifdef CONFIG_UX500_SOC_DB8500
/* Virtual interrupts corresponding to the PRCMU wakeups. */
#define IRQ_PRCMU_BASE IRQ_SOC_START
#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
/*
* We may have several SoCs, but only one will run at a
* time, so the one with most IRQs will bump this ahead,
* but the IRQ_SOC_START remains the same for either SoC.
*/
#if IRQ_SOC_END < IRQ_PRCMU_END
#undef IRQ_SOC_END
#define IRQ_SOC_END IRQ_PRCMU_END
#endif
#endif /* CONFIG_UX500_SOC_DB8500 */
#endif

49
arch/arm/mach-ux500/irqs.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* Copyright (C) 2008 STMicroelectronics
* Copyright (C) 2009 ST-Ericsson.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef ASM_ARCH_IRQS_H
#define ASM_ARCH_IRQS_H
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
/* Shared Peripheral Interrupt (SHPI) */
#define IRQ_SHPI_START 32
/*
* MTU0 preserved for now until plat-nomadik is taught not to use it. Don't
* add any other IRQs here, use the irqs-dbx500.h files.
*/
#define IRQ_MTU0 (IRQ_SHPI_START + 4)
#define DBX500_NR_INTERNAL_IRQS 166
/* After chip-specific IRQ numbers we have the GPIO ones */
#define NOMADIK_NR_GPIO 288
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
#define IRQ_SOC_START IRQ_GPIO_END
/* This will be overridden by SoC-specific irq headers */
#define IRQ_SOC_END IRQ_SOC_START
#include "irqs-db8500.h"
#define IRQ_BOARD_START IRQ_SOC_END
/* This will be overridden by board-specific irq headers */
#define IRQ_BOARD_END IRQ_BOARD_START
#ifdef CONFIG_MACH_MOP500
#include "irqs-board-mop500.h"
#endif
#define UX500_NR_IRQS IRQ_BOARD_END
#endif /* ASM_ARCH_IRQS_H */

746
arch/arm/mach-ux500/pins-db8500.h Normal file
View File

@@ -0,0 +1,746 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License, version 2
* Author: Rabin Vincent <rabin.vincent@stericsson.com>
*/
#ifndef __MACH_PINS_DB8500_H
#define __MACH_PINS_DB8500_H
/*
* TODO: Eventually encode all non-board specific pull up/down configuration
* here.
*/
#define GPIO0_GPIO PIN_CFG(0, GPIO)
#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
#define GPIO1_GPIO PIN_CFG(1, GPIO)
#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
#define GPIO2_GPIO PIN_CFG(2, GPIO)
#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
#define GPIO2_NONE PIN_CFG(2, ALT_B)
#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
#define GPIO3_GPIO PIN_CFG(3, GPIO)
#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
#define GPIO3_NONE PIN_CFG(3, ALT_B)
#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
#define GPIO4_GPIO PIN_CFG(4, GPIO)
#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
#define GPIO5_GPIO PIN_CFG(5, GPIO)
#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
#define GPIO6_GPIO PIN_CFG(6, GPIO)
#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
#define GPIO7_GPIO PIN_CFG(7, GPIO)
#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
#define GPIO8_GPIO PIN_CFG(8, GPIO)
#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
#define GPIO9_GPIO PIN_CFG(9, GPIO)
#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
#define GPIO10_GPIO PIN_CFG(10, GPIO)
#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
#define GPIO11_GPIO PIN_CFG(11, GPIO)
#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
#define GPIO12_GPIO PIN_CFG(12, GPIO)
#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
#define GPIO13_GPIO PIN_CFG(13, GPIO)
#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
#define GPIO14_GPIO PIN_CFG(14, GPIO)
#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
#define GPIO15_GPIO PIN_CFG(15, GPIO)
#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
#define GPIO16_GPIO PIN_CFG(16, GPIO)
#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
#define GPIO17_GPIO PIN_CFG(17, GPIO)
#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
#define GPIO18_GPIO PIN_CFG(18, GPIO)
#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP)
#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
#define GPIO19_GPIO PIN_CFG(19, GPIO)
#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP)
#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
#define GPIO20_GPIO PIN_CFG(20, GPIO)
#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP)
#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
#define GPIO21_GPIO PIN_CFG(21, GPIO)
#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP)
#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
#define GPIO22_GPIO PIN_CFG(22, GPIO)
#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP)
#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
#define GPIO23_GPIO PIN_CFG(23, GPIO)
#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP)
#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
#define GPIO24_GPIO PIN_CFG(24, GPIO)
#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP)
#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
#define GPIO25_GPIO PIN_CFG(25, GPIO)
#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP)
#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
#define GPIO26_GPIO PIN_CFG(26, GPIO)
#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP)
#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
#define GPIO27_GPIO PIN_CFG(27, GPIO)
#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP)
#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
#define GPIO28_GPIO PIN_CFG(28, GPIO)
#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP)
#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
#define GPIO29_GPIO PIN_CFG(29, GPIO)
#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
#define GPIO30_GPIO PIN_CFG(30, GPIO)
#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
#define GPIO31_GPIO PIN_CFG(31, GPIO)
#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
#define GPIO32_GPIO PIN_CFG(32, GPIO)
#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
#define GPIO33_GPIO PIN_CFG(33, GPIO)
#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
#define GPIO34_GPIO PIN_CFG(34, GPIO)
#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
#define GPIO34_NONE PIN_CFG(34, ALT_B)
#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
#define GPIO35_GPIO PIN_CFG(35, GPIO)
#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
#define GPIO35_NONE PIN_CFG(35, ALT_B)
#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
#define GPIO36_GPIO PIN_CFG(36, GPIO)
#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
#define GPIO64_GPIO PIN_CFG(64, GPIO)
#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
#define GPIO65_GPIO PIN_CFG(65, GPIO)
#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
#define GPIO66_GPIO PIN_CFG(66, GPIO)
#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
#define GPIO67_GPIO PIN_CFG(67, GPIO)
#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
#define GPIO68_GPIO PIN_CFG(68, GPIO)
#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
#define GPIO69_GPIO PIN_CFG(69, GPIO)
#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
#define GPIO70_GPIO PIN_CFG(70, GPIO)
#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
#define GPIO71_GPIO PIN_CFG(71, GPIO)
#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
#define GPIO72_GPIO PIN_CFG(72, GPIO)
#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
#define GPIO73_GPIO PIN_CFG(73, GPIO)
#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
#define GPIO74_GPIO PIN_CFG(74, GPIO)
#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
#define GPIO75_GPIO PIN_CFG(75, GPIO)
#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
#define GPIO76_GPIO PIN_CFG(76, GPIO)
#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
#define GPIO77_GPIO PIN_CFG(77, GPIO)
#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
#define GPIO77_NONE PIN_CFG(77, ALT_C)
#define GPIO78_GPIO PIN_CFG(78, GPIO)
#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
#define GPIO79_GPIO PIN_CFG(79, GPIO)
#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
#define GPIO80_GPIO PIN_CFG(80, GPIO)
#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
#define GPIO81_GPIO PIN_CFG(81, GPIO)
#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
#define GPIO82_GPIO PIN_CFG(82, GPIO)
#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
#define GPIO83_GPIO PIN_CFG(83, GPIO)
#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
#define GPIO84_GPIO PIN_CFG(84, GPIO)
#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
#define GPIO85_GPIO PIN_CFG(85, GPIO)
#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
#define GPIO86_GPIO PIN_CFG(86, GPIO)
#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
#define GPIO87_GPIO PIN_CFG(87, GPIO)
#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
#define GPIO88_GPIO PIN_CFG(88, GPIO)
#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
#define GPIO89_GPIO PIN_CFG(89, GPIO)
#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
#define GPIO90_GPIO PIN_CFG(90, GPIO)
#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
#define GPIO91_GPIO PIN_CFG(91, GPIO)
#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
#define GPIO92_GPIO PIN_CFG(92, GPIO)
#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
#define GPIO93_GPIO PIN_CFG(93, GPIO)
#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
#define GPIO94_GPIO PIN_CFG(94, GPIO)
#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
#define GPIO95_GPIO PIN_CFG(95, GPIO)
#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
#define GPIO96_GPIO PIN_CFG(96, GPIO)
#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
#define GPIO97_GPIO PIN_CFG(97, GPIO)
#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
#define GPIO128_GPIO PIN_CFG(128, GPIO)
#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP)
#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
#define GPIO129_GPIO PIN_CFG(129, GPIO)
#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP)
#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
#define GPIO130_GPIO PIN_CFG(130, GPIO)
#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP)
#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
#define GPIO131_GPIO PIN_CFG(131, GPIO)
#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP)
#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
#define GPIO132_GPIO PIN_CFG(132, GPIO)
#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP)
#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
#define GPIO133_GPIO PIN_CFG(133, GPIO)
#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP)
#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
#define GPIO134_GPIO PIN_CFG(134, GPIO)
#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP)
#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
#define GPIO135_GPIO PIN_CFG(135, GPIO)
#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP)
#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
#define GPIO136_GPIO PIN_CFG(136, GPIO)
#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP)
#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
#define GPIO137_GPIO PIN_CFG(137, GPIO)
#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP)
#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
#define GPIO138_GPIO PIN_CFG(138, GPIO)
#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP)
#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
#define GPIO139_GPIO PIN_CFG(139, GPIO)
#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
#define GPIO140_GPIO PIN_CFG(140, GPIO)
#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
#define GPIO141_GPIO PIN_CFG(141, GPIO)
#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
#define GPIO142_GPIO PIN_CFG(142, GPIO)
#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
#define GPIO143_GPIO PIN_CFG(143, GPIO)
#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
#define GPIO144_GPIO PIN_CFG(144, GPIO)
#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
#define GPIO145_GPIO PIN_CFG(145, GPIO)
#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
#define GPIO146_GPIO PIN_CFG(146, GPIO)
#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
#define GPIO147_GPIO PIN_CFG(147, GPIO)
#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
#define GPIO148_GPIO PIN_CFG(148, GPIO)
#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
#define GPIO149_GPIO PIN_CFG(149, GPIO)
#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
#define GPIO150_GPIO PIN_CFG(150, GPIO)
#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
#define GPIO151_GPIO PIN_CFG(151, GPIO)
#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
#define GPIO152_GPIO PIN_CFG(152, GPIO)
#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
#define GPIO153_GPIO PIN_CFG(153, GPIO)
#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
#define GPIO154_GPIO PIN_CFG(154, GPIO)
#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
#define GPIO155_GPIO PIN_CFG(155, GPIO)
#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
#define GPIO156_GPIO PIN_CFG(156, GPIO)
#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
#define GPIO157_GPIO PIN_CFG(157, GPIO)
#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
#define GPIO158_GPIO PIN_CFG(158, GPIO)
#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
#define GPIO159_GPIO PIN_CFG(159, GPIO)
#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
#define GPIO160_GPIO PIN_CFG(160, GPIO)
#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
#define GPIO160_NONE PIN_CFG(160, ALT_C)
#define GPIO161_GPIO PIN_CFG(161, GPIO)
#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
#define GPIO162_GPIO PIN_CFG(162, GPIO)
#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
#define GPIO163_GPIO PIN_CFG(163, GPIO)
#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
#define GPIO164_GPIO PIN_CFG(164, GPIO)
#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
#define GPIO165_GPIO PIN_CFG(165, GPIO)
#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
#define GPIO166_GPIO PIN_CFG(166, GPIO)
#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
#define GPIO167_GPIO PIN_CFG(167, GPIO)
#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
#define GPIO168_GPIO PIN_CFG(168, GPIO)
#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
#define GPIO168_NONE PIN_CFG(168, ALT_C)
#define GPIO169_GPIO PIN_CFG(169, GPIO)
#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
#define GPIO170_GPIO PIN_CFG(170, GPIO)
#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
#define GPIO171_GPIO PIN_CFG(171, GPIO)
#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
#define GPIO192_GPIO PIN_CFG(192, GPIO)
#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
#define GPIO193_GPIO PIN_CFG(193, GPIO)
#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
#define GPIO194_GPIO PIN_CFG(194, GPIO)
#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
#define GPIO195_GPIO PIN_CFG(195, GPIO)
#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
#define GPIO196_GPIO PIN_CFG(196, GPIO)
#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
#define GPIO197_GPIO PIN_CFG(197, GPIO)
#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP)
#define GPIO198_GPIO PIN_CFG(198, GPIO)
#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP)
#define GPIO199_GPIO PIN_CFG(199, GPIO)
#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP)
#define GPIO200_GPIO PIN_CFG(200, GPIO)
#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP)
#define GPIO201_GPIO PIN_CFG(201, GPIO)
#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP)
#define GPIO202_GPIO PIN_CFG(202, GPIO)
#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP)
#define GPIO202_PWL PIN_CFG(202, ALT_B)
#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
#define GPIO203_GPIO PIN_CFG(203, GPIO)
#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP)
#define GPIO204_GPIO PIN_CFG(204, GPIO)
#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP)
#define GPIO205_GPIO PIN_CFG(205, GPIO)
#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP)
#define GPIO206_GPIO PIN_CFG(206, GPIO)
#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP)
#define GPIO207_GPIO PIN_CFG(207, GPIO)
#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP)
#define GPIO208_GPIO PIN_CFG(208, GPIO)
#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
#define GPIO209_GPIO PIN_CFG(209, GPIO)
#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
#define GPIO210_GPIO PIN_CFG(210, GPIO)
#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
#define GPIO211_GPIO PIN_CFG(211, GPIO)
#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
#define GPIO212_GPIO PIN_CFG(212, GPIO)
#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
#define GPIO213_GPIO PIN_CFG(213, GPIO)
#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
#define GPIO214_GPIO PIN_CFG(214, GPIO)
#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
#define GPIO215_GPIO PIN_CFG(215, GPIO)
#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C)
#define GPIO216_GPIO PIN_CFG(216, GPIO)
#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
#define GPIO217_GPIO PIN_CFG(217, GPIO)
#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C)
#define GPIO218_GPIO PIN_CFG(218, GPIO)
#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
#define GPIO219_GPIO PIN_CFG(219, GPIO)
#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
#define GPIO220_GPIO PIN_CFG(220, GPIO)
#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
#define GPIO221_GPIO PIN_CFG(221, GPIO)
#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
#define GPIO222_GPIO PIN_CFG(222, GPIO)
#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
#define GPIO223_GPIO PIN_CFG(223, GPIO)
#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
#define GPIO224_GPIO PIN_CFG(224, GPIO)
#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
#define GPIO225_GPIO PIN_CFG(225, GPIO)
#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
#define GPIO226_GPIO PIN_CFG(226, GPIO)
#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
#define GPIO226_PWL PIN_CFG(226, ALT_B)
#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
#define GPIO227_GPIO PIN_CFG(227, GPIO)
#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
#define GPIO228_GPIO PIN_CFG(228, GPIO)
#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
#define GPIO229_GPIO PIN_CFG(229, GPIO)
#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
#define GPIO229_PWL PIN_CFG(229, ALT_B)
#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
#define GPIO230_GPIO PIN_CFG(230, GPIO)
#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
#define GPIO230_PWL PIN_CFG(230, ALT_B)
#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
#define GPIO256_GPIO PIN_CFG(256, GPIO)
#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
#define GPIO257_GPIO PIN_CFG(257, GPIO)
#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
#define GPIO258_GPIO PIN_CFG(258, GPIO)
#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
#define GPIO258_NONE PIN_CFG(258, ALT_B)
#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
#define GPIO259_GPIO PIN_CFG(259, GPIO)
#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
#define GPIO260_GPIO PIN_CFG(260, GPIO)
#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
#define GPIO261_GPIO PIN_CFG(261, GPIO)
#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
#define GPIO262_GPIO PIN_CFG(262, GPIO)
#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
#define GPIO263_GPIO PIN_CFG(263, GPIO)
#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
#define GPIO264_GPIO PIN_CFG(264, GPIO)
#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
#define GPIO265_GPIO PIN_CFG(265, GPIO)
#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
#define GPIO266_GPIO PIN_CFG(266, GPIO)
#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
#define GPIO267_GPIO PIN_CFG(267, GPIO)
#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
#endif

170
arch/arm/mach-ux500/platsmp.c Normal file
View File

@@ -0,0 +1,170 @@
/*
* Copyright (C) 2002 ARM Ltd.
* Copyright (C) 2008 STMicroelctronics.
* Copyright (C) 2009 ST-Ericsson.
* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
*
* This file is based on arm realview platform
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "setup.h"
#include "db8500-regs.h"
#include "id.h"
/* This is called from headsmp.S to wakeup the secondary core */
extern void u8500_secondary_startup(void);
/*
* Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency
* or not. This is necessary for the hotplug code to work reliably.
*/
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
}
static void __iomem *scu_base_addr(void)
{
if (cpu_is_u8500_family() || cpu_is_ux540_family())
return __io_address(U8500_SCU_BASE);
else
ux500_unknown_soc();
return NULL;
}
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit ux500_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*/
write_pen_release(cpu_logical_map(cpu));
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
if (pen_release == -1)
break;
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
static void __init wakeup_secondary(void)
{
void __iomem *backupram;
if (cpu_is_u8500_family() || cpu_is_ux540_family())
backupram = __io_address(U8500_BACKUPRAM0_BASE);
else
ux500_unknown_soc();
/*
* write the address of secondary startup into the backup ram register
* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
* backup ram register at offset 0x1FF0, which is what boot rom code
* is waiting for. This would wake up the secondary core from WFE
*/
#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
__raw_writel(virt_to_phys(u8500_secondary_startup),
backupram + UX500_CPU1_JUMPADDR_OFFSET);
#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
__raw_writel(0xA1FEED01,
backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
static void __init ux500_smp_init_cpus(void)
{
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
/* sanity check */
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
ncores, nr_cpu_ids);
ncores = nr_cpu_ids;
}
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
}
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{
scu_enable(scu_base_addr());
wakeup_secondary();
}
struct smp_operations ux500_smp_ops __initdata = {
.smp_init_cpus = ux500_smp_init_cpus,
.smp_prepare_cpus = ux500_smp_prepare_cpus,
.smp_secondary_init = ux500_secondary_init,
.smp_boot_secondary = ux500_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = ux500_cpu_die,
#endif
};

167
arch/arm/mach-ux500/pm.c Normal file
View File

@@ -0,0 +1,167 @@
/*
* Copyright (C) ST-Ericsson SA 2010-2013
* Author: Rickard Andersson <rickard.andersson@stericsson.com> for
* ST-Ericsson.
* Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
* License terms: GNU General Public License (GPL) version 2
*
*/
#include <linux/kernel.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include "db8500-regs.h"
/* ARM WFI Standby signal register */
#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
#define PRCM_IOCR (prcmu_base + 0x310)
#define PRCM_IOCR_IOFORCE 0x1
/* Dual A9 core interrupt management unit registers */
#define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
static void __iomem *prcmu_base;
/* This function decouple the gic from the prcmu */
int prcmu_gic_decouple(void)
{
u32 val = readl(PRCM_A9_MASK_REQ);
/* Set bit 0 register value to 1 */
writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
PRCM_A9_MASK_REQ);
/* Make sure the register is updated */
readl(PRCM_A9_MASK_REQ);
/* Wait a few cycles for the gic mask completion */
udelay(1);
return 0;
}
/* This function recouple the gic with the prcmu */
int prcmu_gic_recouple(void)
{
u32 val = readl(PRCM_A9_MASK_REQ);
/* Set bit 0 register value to 0 */
writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
return 0;
}
#define PRCMU_GIC_NUMBER_REGS 5
/*
* This function checks if there are pending irq on the gic. It only
* makes sense if the gic has been decoupled before with the
* db8500_prcmu_gic_decouple function. Disabling an interrupt only
* disables the forwarding of the interrupt to any CPU interface. It
* does not prevent the interrupt from changing state, for example
* becoming pending, or active and pending if it is already
* active. Hence, we have to check the interrupt is pending *and* is
* active.
*/
bool prcmu_gic_pending_irq(void)
{
u32 pr; /* Pending register */
u32 er; /* Enable register */
void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
int i;
/* 5 registers. STI & PPI not skipped */
for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
if (pr & er)
return true; /* There is a pending interrupt */
}
return false;
}
/*
* This function checks if there are pending interrupt on the
* prcmu which has been delegated to monitor the irqs with the
* db8500_prcmu_copy_gic_settings function.
*/
bool prcmu_pending_irq(void)
{
u32 it, im;
int i;
for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
it = readl(PRCM_ARMITVAL31TO0 + i * 4);
im = readl(PRCM_ARMITMSK31TO0 + i * 4);
if (it & im)
return true; /* There is a pending interrupt */
}
return false;
}
/*
* This function checks if the specified cpu is in in WFI. It's usage
* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
* function. Of course passing smp_processor_id() to this function will
* always return false...
*/
bool prcmu_is_cpu_in_wfi(int cpu)
{
return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
PRCM_ARM_WFI_STANDBY_WFI0;
}
/*
* This function copies the gic SPI settings to the prcmu in order to
* monitor them and abort/finish the retention/off sequence or state.
*/
int prcmu_copy_gic_settings(void)
{
u32 er; /* Enable register */
void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
int i;
/* We skip the STI and PPI */
for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
er = readl_relaxed(dist_base +
GIC_DIST_ENABLE_SET + (i + 1) * 4);
writel(er, PRCM_ARMITMSK31TO0 + i * 4);
}
return 0;
}
void __init ux500_pm_init(u32 phy_base, u32 size)
{
prcmu_base = ioremap(phy_base, size);
if (!prcmu_base) {
pr_err("could not remap PRCMU for PM functions\n");
return;
}
/*
* On watchdog reboot the GIC is in some cases decoupled.
* This will make sure that the GIC is correctly configured.
*/
prcmu_gic_recouple();
}

50
arch/arm/mach-ux500/setup.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* Copyright (C) 2009 ST-Ericsson.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* These symbols are needed for board-specific files to call their
* own cpu-specific files
*/
#ifndef __ASM_ARCH_SETUP_H
#define __ASM_ARCH_SETUP_H
#include <asm/mach/time.h>
#include <linux/init.h>
#include <linux/mfd/abx500/ab8500.h>
void __init ux500_map_io(void);
extern void __init u8500_map_io(void);
extern struct device * __init u8500_init_devices(void);
extern void __init ux500_init_irq(void);
extern void __init ux500_init_late(void);
extern struct device *ux500_soc_device_init(const char *soc_id);
struct amba_device;
extern void __init amba_add_devices(struct amba_device *devs[], int num);
extern void ux500_timer_init(void);
#define __IO_DEV_DESC(x, sz) { \
.virtual = IO_ADDRESS(x), \
.pfn = __phys_to_pfn(x), \
.length = sz, \
.type = MT_DEVICE, \
}
#define __MEM_DEV_DESC(x, sz) { \
.virtual = IO_ADDRESS(x), \
.pfn = __phys_to_pfn(x), \
.length = sz, \
.type = MT_MEMORY_RWX, \
}
extern struct smp_operations ux500_smp_ops;
extern void ux500_cpu_die(unsigned int cpu);
#endif /* __ASM_ARCH_SETUP_H */

144
arch/arm/mach-ux500/ste-dma40-db8500.h Normal file
View File

@@ -0,0 +1,144 @@
/*
* arch/arm/mach-ux500/ste_dma40_db8500.h
* DB8500-SoC-specific configuration for DMA40
*
* Copyright (C) ST-Ericsson 2007-2010
* License terms: GNU General Public License (GPL) version 2
* Author: Per Friden <per.friden@stericsson.com>
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
*/
#ifndef STE_DMA40_DB8500_H
#define STE_DMA40_DB8500_H
#define DB8500_DMA_NR_DEV 64
enum dma_src_dev_type {
DB8500_DMA_DEV0_SPI0_RX = 0,
DB8500_DMA_DEV1_SD_MMC0_RX = 1,
DB8500_DMA_DEV2_SD_MMC1_RX = 2,
DB8500_DMA_DEV3_SD_MMC2_RX = 3,
DB8500_DMA_DEV4_I2C1_RX = 4,
DB8500_DMA_DEV5_I2C3_RX = 5,
DB8500_DMA_DEV6_I2C2_RX = 6,
DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
DB8500_DMA_DEV8_SSP0_RX = 8,
DB8500_DMA_DEV9_SSP1_RX = 9,
DB8500_DMA_DEV10_MCDE_RX = 10,
DB8500_DMA_DEV11_UART2_RX = 11,
DB8500_DMA_DEV12_UART1_RX = 12,
DB8500_DMA_DEV13_UART0_RX = 13,
DB8500_DMA_DEV14_MSP2_RX = 14,
DB8500_DMA_DEV15_I2C0_RX = 15,
DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
DB8500_DMA_DEV28_SD_MM2_RX = 28,
DB8500_DMA_DEV29_SD_MM0_RX = 29,
DB8500_DMA_DEV30_MSP1_RX = 30,
/* On DB8500v2, MSP3 RX replaces MSP1 RX */
DB8500_DMA_DEV30_MSP3_RX = 30,
DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
DB8500_DMA_DEV32_SD_MM1_RX = 32,
DB8500_DMA_DEV33_SPI2_RX = 33,
DB8500_DMA_DEV34_I2C3_RX2 = 34,
DB8500_DMA_DEV35_SPI1_RX = 35,
DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
DB8500_DMA_DEV40_SPI3_RX = 40,
DB8500_DMA_DEV41_SD_MM3_RX = 41,
DB8500_DMA_DEV42_SD_MM4_RX = 42,
DB8500_DMA_DEV43_SD_MM5_RX = 43,
DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
DB8500_DMA_DEV48_CAC1_RX = 48,
/* 49, 50 and 51 are not used */
DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
/* 56, 57, 58, 59 and 60 are not used */
DB8500_DMA_DEV61_CAC0_RX = 61,
/* 62 and 63 are not used */
};
enum dma_dest_dev_type {
DB8500_DMA_DEV0_SPI0_TX = 0,
DB8500_DMA_DEV1_SD_MMC0_TX = 1,
DB8500_DMA_DEV2_SD_MMC1_TX = 2,
DB8500_DMA_DEV3_SD_MMC2_TX = 3,
DB8500_DMA_DEV4_I2C1_TX = 4,
DB8500_DMA_DEV5_I2C3_TX = 5,
DB8500_DMA_DEV6_I2C2_TX = 6,
DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
DB8500_DMA_DEV8_SSP0_TX = 8,
DB8500_DMA_DEV9_SSP1_TX = 9,
/* 10 is not used*/
DB8500_DMA_DEV11_UART2_TX = 11,
DB8500_DMA_DEV12_UART1_TX = 12,
DB8500_DMA_DEV13_UART0_TX = 13,
DB8500_DMA_DEV14_MSP2_TX = 14,
DB8500_DMA_DEV15_I2C0_TX = 15,
DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
DB8500_DMA_DEV28_SD_MM2_TX = 28,
DB8500_DMA_DEV29_SD_MM0_TX = 29,
DB8500_DMA_DEV30_MSP1_TX = 30,
DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
DB8500_DMA_DEV32_SD_MM1_TX = 32,
DB8500_DMA_DEV33_SPI2_TX = 33,
DB8500_DMA_DEV34_I2C3_TX2 = 34,
DB8500_DMA_DEV35_SPI1_TX = 35,
DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
DB8500_DMA_DEV40_SPI3_TX = 40,
DB8500_DMA_DEV41_SD_MM3_TX = 41,
DB8500_DMA_DEV42_SD_MM4_TX = 42,
DB8500_DMA_DEV43_SD_MM5_TX = 43,
DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
DB8500_DMA_DEV48_CAC1_TX = 48,
DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
DB8500_DMA_DEV50_HAC1_TX = 50,
DB8500_DMA_MEMCPY_TX_0 = 51,
DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
DB8500_DMA_MEMCPY_TX_1 = 56,
DB8500_DMA_MEMCPY_TX_2 = 57,
DB8500_DMA_MEMCPY_TX_3 = 58,
DB8500_DMA_MEMCPY_TX_4 = 59,
DB8500_DMA_MEMCPY_TX_5 = 60,
DB8500_DMA_DEV61_CAC0_TX = 61,
DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
DB8500_DMA_DEV63_HAC0_TX = 63,
};
#endif

104
arch/arm/mach-ux500/timer.c Normal file
View File

@@ -0,0 +1,104 @@
/*
* Copyright (C) ST-Ericsson SA 2011
*
* License Terms: GNU General Public License v2
* Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
*/
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/clksrc-dbx500-prcmu.h>
#include <linux/clocksource.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <asm/smp_twd.h>
#include "setup.h"
#include "irqs.h"
#include "db8500-regs.h"
#include "id.h"
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
U8500_TWD_BASE, IRQ_LOCALTIMER);
static void __init ux500_twd_init(void)
{
struct twd_local_timer *twd_local_timer;
int err;
/* Use this to switch local timer base if changed in new ASICs */
twd_local_timer = &u8500_twd_local_timer;
if (of_have_populated_dt())
clocksource_of_init();
else {
err = twd_local_timer_register(twd_local_timer);
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
}
}
#else
#define ux500_twd_init() do { } while(0)
#endif
const static struct of_device_id prcmu_timer_of_match[] __initconst = {
{ .compatible = "stericsson,db8500-prcmu-timer-4", },
{ },
};
void __init ux500_timer_init(void)
{
void __iomem *mtu_timer_base;
void __iomem *prcmu_timer_base;
void __iomem *tmp_base;
struct device_node *np;
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
mtu_timer_base = __io_address(U8500_MTU0_BASE);
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
} else {
ux500_unknown_soc();
}
/* TODO: Once MTU has been DT:ed place code above into else. */
if (of_have_populated_dt()) {
#ifdef CONFIG_OF
np = of_find_matching_node(NULL, prcmu_timer_of_match);
if (!np)
#endif
goto dt_fail;
tmp_base = of_iomap(np, 0);
if (!tmp_base)
goto dt_fail;
prcmu_timer_base = tmp_base;
}
dt_fail:
/* Doing it the old fashioned way. */
/*
* Here we register the timerblocks active in the system.
* Localtimers (twd) is started when both cpu is up and running.
* MTU register a clocksource, clockevent and sched_clock.
* Since the MTU is located in the VAPE power domain
* it will be cleared in sleep which makes it unsuitable.
* We however need it as a timer tick (clockevent)
* during boot to calibrate delay until twd is started.
* RTC-RTT have problems as timer tick during boot since it is
* depending on delay which is not yet calibrated. RTC-RTT is in the
* always-on powerdomain and is used as clockevent instead of twd when
* sleeping.
* The PRCMU timer 4 register a clocksource and
* sched_clock with higher rating then MTU since is always-on.
*
*/
nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
clksrc_dbx500_prcmu_init(prcmu_timer_base);
ux500_twd_init();
}

158
arch/arm/mach-ux500/usb.c Normal file
View File

@@ -0,0 +1,158 @@
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/usb-musb-ux500.h>
#include <linux/platform_data/dma-ste-dma40.h>
#include "db8500-regs.h"
#define MUSB_DMA40_RX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
.dir = STEDMA40_PERIPH_TO_MEM, \
.dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
.src_info.data_width = STEDMA40_WORD_WIDTH, \
.dst_info.data_width = STEDMA40_WORD_WIDTH, \
.src_info.psize = STEDMA40_PSIZE_LOG_16, \
.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
}
#define MUSB_DMA40_TX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
.dir = STEDMA40_MEM_TO_PERIPH, \
.src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
.src_info.data_width = STEDMA40_WORD_WIDTH, \
.dst_info.data_width = STEDMA40_WORD_WIDTH, \
.src_info.psize = STEDMA40_PSIZE_LOG_16, \
.dst_info.psize = STEDMA40_PSIZE_LOG_16, \
}
static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
= {
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH
};
static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
= {
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
};
static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
&musb_dma_rx_ch[0],
&musb_dma_rx_ch[1],
&musb_dma_rx_ch[2],
&musb_dma_rx_ch[3],
&musb_dma_rx_ch[4],
&musb_dma_rx_ch[5],
&musb_dma_rx_ch[6],
&musb_dma_rx_ch[7]
};
static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
&musb_dma_tx_ch[0],
&musb_dma_tx_ch[1],
&musb_dma_tx_ch[2],
&musb_dma_tx_ch[3],
&musb_dma_tx_ch[4],
&musb_dma_tx_ch[5],
&musb_dma_tx_ch[6],
&musb_dma_tx_ch[7]
};
static struct ux500_musb_board_data musb_board_data = {
.dma_rx_param_array = ux500_dma_rx_param_array,
.dma_tx_param_array = ux500_dma_tx_param_array,
.num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
.num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
.dma_filter = stedma40_filter,
};
static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
static struct musb_hdrc_config musb_hdrc_config = {
.multipoint = true,
.dyn_fifo = true,
.num_eps = 16,
.ram_bits = 16,
};
static struct musb_hdrc_platform_data musb_platform_data = {
.mode = MUSB_OTG,
.config = &musb_hdrc_config,
.board_data = &musb_board_data,
};
static struct resource usb_resources[] = {
[0] = {
.name = "usb-mem",
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "mc", /* hard-coded in musb */
.flags = IORESOURCE_IRQ,
},
};
struct platform_device ux500_musb_device = {
.name = "musb-ux500",
.id = 0,
.dev = {
.platform_data = &musb_platform_data,
.dma_mask = &ux500_musb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
};
static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
{
u32 idx;
for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
}
static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
{
u32 idx;
for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
}
void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
int *dma_rx_cfg, int *dma_tx_cfg)
{
ux500_musb_device.resource[0].start = base;
ux500_musb_device.resource[0].end = base + SZ_64K - 1;
ux500_musb_device.resource[1].start = irq;
ux500_musb_device.resource[1].end = irq;
ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
ux500_musb_device.dev.parent = parent;
platform_device_register(&ux500_musb_device);
}