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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
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170
arch/arm/mach-sa1100/Kconfig Normal file
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if ARCH_SA1100
menu "SA11x0 Implementations"
config SA1100_ASSABET
bool "Assabet"
select ARM_SA1110_CPUFREQ
help
Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
Microprocessor Development Board (also known as the Assabet).
config ASSABET_NEPONSET
bool "Include support for Neponset"
depends on SA1100_ASSABET
select SA1111
help
Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
Microprocessor Development Board (Assabet) with the SA-1111
Development Board (Nepon).
config SA1100_CERF
bool "CerfBoard"
select ARM_SA1110_CPUFREQ
help
The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued).
More information is available at:
<http://www.intrinsyc.com/products/cerfboard/>.
Say Y if configuring for an Intrinsyc CerfBoard.
Say N otherwise.
choice
prompt "Cerf Flash available"
depends on SA1100_CERF
default SA1100_CERF_FLASH_8MB
config SA1100_CERF_FLASH_8MB
bool "8MB"
config SA1100_CERF_FLASH_16MB
bool "16MB"
config SA1100_CERF_FLASH_32MB
bool "32MB"
endchoice
config SA1100_COLLIE
bool "Sharp Zaurus SL5500"
# FIXME: select ARM_SA11x0_CPUFREQ
select SHARP_LOCOMO
select SHARP_PARAM
select SHARP_SCOOP
help
Say Y here to support the Sharp Zaurus SL5500 PDAs.
config SA1100_H3100
bool "Compaq iPAQ H3100"
select ARM_SA1110_CPUFREQ
select HTC_EGPIO
help
Say Y here if you intend to run this kernel on the Compaq iPAQ
H3100 handheld computer. Information about this machine and the
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3100>
config SA1100_H3600
bool "Compaq iPAQ H3600/H3700"
select ARM_SA1110_CPUFREQ
select HTC_EGPIO
help
Say Y here if you intend to run this kernel on the Compaq iPAQ
H3600 handheld computer. Information about this machine and the
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3600>
config SA1100_BADGE4
bool "HP Labs BadgePAD 4"
select ARM_SA1100_CPUFREQ
select SA1111
help
Say Y here if you want to build a kernel for the HP Laboratories
BadgePAD 4.
config SA1100_JORNADA720
bool "HP Jornada 720"
# FIXME: select ARM_SA11x0_CPUFREQ
select SA1111
help
Say Y here if you want to build a kernel for the HP Jornada 720
handheld computer. See
<http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#>
config SA1100_JORNADA720_SSP
bool "HP Jornada 720 Extended SSP driver"
depends on SA1100_JORNADA720
select SA1100_SSP
help
Say Y here if you have a HP Jornada 7xx handheld computer and you
want to access devices connected to the MCU. Those include the
keyboard, touchscreen, backlight and battery. This driver also activates
the generic SSP which it extends.
config SA1100_HACKKIT
bool "HackKit Core CPU Board"
select ARM_SA1100_CPUFREQ
help
Say Y here to support the HackKit Core CPU Board
<http://hackkit.eletztrick.de>;
config SA1100_LART
bool "LART"
select ARM_SA1100_CPUFREQ
help
Say Y here if you are using the Linux Advanced Radio Terminal
(also known as the LART). See <http://www.lartmaker.nl/> for
information on the LART.
config SA1100_NANOENGINE
bool "nanoEngine"
select ARM_SA1110_CPUFREQ
select PCI
select PCI_NANOENGINE
help
Say Y here if you are using the Bright Star Engineering nanoEngine.
See <http://www.brightstareng.com/arm/nanoeng.htm> for information
on the BSE nanoEngine.
config SA1100_PLEB
bool "PLEB"
select ARM_SA1100_CPUFREQ
help
Say Y here if you are using version 1 of the Portable Linux
Embedded Board (also known as PLEB).
See <http://www.disy.cse.unsw.edu.au/Hardware/PLEB/>
for more information.
config SA1100_SHANNON
bool "Shannon"
select ARM_SA1100_CPUFREQ
help
The Shannon (also known as a Tuxscreen, and also as a IS2630) was a
limited edition webphone produced by Philips. The Shannon is a SA1100
platform with a 640x480 LCD, touchscreen, CIR keyboard, PCMCIA slots,
and a telco interface.
config SA1100_SIMPAD
bool "Simpad"
select ARM_SA1110_CPUFREQ
help
The SIEMENS webpad SIMpad is based on the StrongARM 1110. There
are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB
FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a
PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same
like CL4 in additional it has a PCMCIA-Slot. For more information
visit <http://www.usa.siemens.com/> or <http://www.siemens.ch/>.
config SA1100_SSP
tristate "Generic PIO SSP"
help
Say Y here to enable support for the generic PIO SSP driver.
This isn't for audio support, but for attached sensors and
other devices, eg for BadgePAD 4 sensor support.
endmenu
endif

43
arch/arm/mach-sa1100/Makefile Normal file
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#
# Makefile for the linux kernel.
#
# Common support
obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
obj-m :=
obj-n :=
obj- :=
# Specific board support
obj-$(CONFIG_SA1100_ASSABET) += assabet.o
obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
obj-$(CONFIG_SA1100_BADGE4) += badge4.o
obj-$(CONFIG_SA1100_CERF) += cerf.o
obj-$(CONFIG_SA1100_COLLIE) += collie.o
obj-$(CONFIG_SA1100_H3100) += h3100.o h3xxx.o
obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o
obj-$(CONFIG_SA1100_HACKKIT) += hackkit.o
obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o
obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
obj-$(CONFIG_SA1100_LART) += lart.o
obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o
obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o
obj-$(CONFIG_SA1100_PLEB) += pleb.o
obj-$(CONFIG_SA1100_SHANNON) += shannon.o
obj-$(CONFIG_SA1100_SIMPAD) += simpad.o
# Miscellaneous functions
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_SA1100_SSP) += ssp.o

8
arch/arm/mach-sa1100/Makefile.boot Normal file
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ifeq ($(CONFIG_SA1111),y)
zreladdr-y += 0xc0208000
else
zreladdr-y += 0xc0008000
endif
params_phys-y := 0xc0000100
initrd_phys-y := 0xc0800000

632
arch/arm/mach-sa1100/assabet.c Normal file
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/*
* linux/arch/arm/mach-sa1100/assabet.c
*
* Author: Nicolas Pitre
*
* This file contains all Assabet-specific tweaks.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/mfd/ucb1x00.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/leds.h>
#include <linux/slab.h>
#include <video/sa1100fb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irda.h>
#include <asm/mach/map.h>
#include <mach/assabet.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/irqs.h>
#include "generic.h"
#define ASSABET_BCR_DB1110 \
(ASSABET_BCR_SPK_OFF | \
ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
ASSABET_BCR_IRDA_MD0)
#define ASSABET_BCR_DB1111 \
(ASSABET_BCR_SPK_OFF | \
ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST)
unsigned long SCR_value = ASSABET_SCR_INIT;
EXPORT_SYMBOL(SCR_value);
static unsigned long BCR_value = ASSABET_BCR_DB1110;
void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
{
unsigned long flags;
local_irq_save(flags);
BCR_value = (BCR_value & ~mask) | val;
ASSABET_BCR = BCR_value;
local_irq_restore(flags);
}
EXPORT_SYMBOL(ASSABET_BCR_frob);
static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
{
if (state == UCB_RST_PROBE)
ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
}
/*
* Assabet flash support code.
*/
#ifdef ASSABET_REV_4
/*
* Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
*/
static struct mtd_partition assabet_partitions[] = {
{
.name = "bootloader",
.size = 0x00020000,
.offset = 0,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "bootloader params",
.size = 0x00020000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "jffs",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
#else
/*
* Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
*/
static struct mtd_partition assabet_partitions[] = {
{
.name = "bootloader",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "bootloader params",
.size = 0x00040000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "jffs",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
#endif
static struct flash_platform_data assabet_flash_data = {
.map_name = "cfi_probe",
.parts = assabet_partitions,
.nr_parts = ARRAY_SIZE(assabet_partitions),
};
static struct resource assabet_flash_resources[] = {
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
};
/*
* Assabet IrDA support code.
*/
static int assabet_irda_set_power(struct device *dev, unsigned int state)
{
static unsigned int bcr_state[4] = {
ASSABET_BCR_IRDA_MD0,
ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0,
ASSABET_BCR_IRDA_MD1,
0
};
if (state < 4) {
state = bcr_state[state];
ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1|
ASSABET_BCR_IRDA_MD0));
ASSABET_BCR_set(state);
}
return 0;
}
static void assabet_irda_set_speed(struct device *dev, unsigned int speed)
{
if (speed < 4000000)
ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
else
ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
}
static struct irda_platform_data assabet_irda_data = {
.set_power = assabet_irda_set_power,
.set_speed = assabet_irda_set_speed,
};
static struct ucb1x00_plat_data assabet_ucb1x00_data = {
.reset = assabet_ucb1x00_reset,
.gpio_base = -1,
};
static struct mcp_plat_data assabet_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
.codec_pdata = &assabet_ucb1x00_data,
};
static void assabet_lcd_set_visual(u32 visual)
{
u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
if (machine_is_assabet()) {
#if 1 // phase 4 or newer Assabet's
if (is_true_color)
ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
else
ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
#else
// older Assabet's
if (is_true_color)
ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
else
ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
#endif
}
}
#ifndef ASSABET_PAL_VIDEO
static void assabet_lcd_backlight_power(int on)
{
if (on)
ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
else
ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
}
/*
* Turn on/off the backlight. When turning the backlight on, we wait
* 500us after turning it on so we don't cause the supplies to droop
* when we enable the LCD controller (and cause a hard reset.)
*/
static void assabet_lcd_power(int on)
{
if (on) {
ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
udelay(500);
} else
ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
}
/*
* The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
* takes an RGB666 signal, but we provide it with an RGB565 signal
* instead (def_rgb_16).
*/
static struct sa1100fb_mach_info lq039q2ds54_info = {
.pixclock = 171521, .bpp = 16,
.xres = 320, .yres = 240,
.hsync_len = 5, .vsync_len = 1,
.left_margin = 61, .upper_margin = 3,
.right_margin = 9, .lower_margin = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
.backlight_power = assabet_lcd_backlight_power,
.lcd_power = assabet_lcd_power,
.set_visual = assabet_lcd_set_visual,
};
#else
static void assabet_pal_backlight_power(int on)
{
ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
}
static void assabet_pal_power(int on)
{
ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
}
static struct sa1100fb_mach_info pal_info = {
.pixclock = 67797, .bpp = 16,
.xres = 640, .yres = 512,
.hsync_len = 64, .vsync_len = 6,
.left_margin = 125, .upper_margin = 70,
.right_margin = 115, .lower_margin = 36,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
.backlight_power = assabet_pal_backlight_power,
.lcd_power = assabet_pal_power,
.set_visual = assabet_lcd_set_visual,
};
#endif
#ifdef CONFIG_ASSABET_NEPONSET
static struct resource neponset_resources[] = {
DEFINE_RES_MEM(0x10000000, 0x08000000),
DEFINE_RES_MEM(0x18000000, 0x04000000),
DEFINE_RES_MEM(0x40000000, SZ_8K),
DEFINE_RES_IRQ(IRQ_GPIO25),
};
#endif
static void __init assabet_init(void)
{
/*
* Ensure that the power supply is in "high power" mode.
*/
GPSR = GPIO_GPIO16;
GPDR |= GPIO_GPIO16;
/*
* Ensure that these pins are set as outputs and are driving
* logic 0. This ensures that we won't inadvertently toggle
* the WS latch in the CPLD, and we don't float causing
* excessive power drain. --rmk
*/
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
/*
* Also set GPIO27 as an output; this is used to clock UART3
* via the FPGA and as otherwise has no pullups or pulldowns,
* so stop it floating.
*/
GPCR = GPIO_GPIO27;
GPDR |= GPIO_GPIO27;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0;
PGSR = 0;
PCFR = 0;
PSDR = 0;
PPDR |= PPC_TXD3 | PPC_TXD1;
PPSR |= PPC_TXD3 | PPC_TXD1;
sa11x0_ppc_configure_mcp();
if (machine_has_neponset()) {
/*
* Angel sets this, but other bootloaders may not.
*
* This must precede any driver calls to BCR_set()
* or BCR_clear().
*/
ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
#ifndef CONFIG_ASSABET_NEPONSET
printk( "Warning: Neponset detected but full support "
"hasn't been configured in the kernel\n" );
#else
platform_device_register_simple("neponset", 0,
neponset_resources, ARRAY_SIZE(neponset_resources));
#endif
}
#ifndef ASSABET_PAL_VIDEO
sa11x0_register_lcd(&lq039q2ds54_info);
#else
sa11x0_register_lcd(&pal_video);
#endif
sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
ARRAY_SIZE(assabet_flash_resources));
sa11x0_register_irda(&assabet_irda_data);
sa11x0_register_mcp(&assabet_mcp_data);
}
/*
* On Assabet, we must probe for the Neponset board _before_
* paging_init() has occurred to actually determine the amount
* of RAM available. To do so, we map the appropriate IO section
* in the page table here in order to access GPIO registers.
*/
static void __init map_sa1100_gpio_regs( void )
{
unsigned long phys = __PREG(GPLR) & PMD_MASK;
unsigned long virt = (unsigned long)io_p2v(phys);
int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
pmd_t *pmd;
pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
*pmd = __pmd(phys | prot);
flush_pmd_entry(pmd);
}
/*
* Read System Configuration "Register"
* (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
* User's Guide", section 4.4.1)
*
* This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
* to set up the serial port for decompression status messages. We
* repeat it here because the kernel may not be loaded as a zImage, and
* also because it's a hassle to communicate the SCR value to the kernel
* from the decompressor.
*
* Note that IRQs are guaranteed to be disabled.
*/
static void __init get_assabet_scr(void)
{
unsigned long uninitialized_var(scr), i;
GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
for(i = 100; i--; ) /* Read GPIO 9:2 */
scr = GPLR;
GPDR |= 0x3fc; /* restore correct pin direction */
scr &= 0x3fc; /* save as system configuration byte. */
SCR_value = scr;
}
static void __init
fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi)
{
/* This must be done before any call to machine_has_neponset() */
map_sa1100_gpio_regs();
get_assabet_scr();
if (machine_has_neponset())
printk("Neponset expansion board detected\n");
}
static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
if (port->mapbase == _Ser1UTCR0) {
if (state)
ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
ASSABET_BCR_COM_RTS |
ASSABET_BCR_COM_DTR);
else
ASSABET_BCR_set(ASSABET_BCR_RS232EN |
ASSABET_BCR_COM_RTS |
ASSABET_BCR_COM_DTR);
}
}
/*
* Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
* and UART3 (radio module). We only handle them for UART1 here.
*/
static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
{
if (port->mapbase == _Ser1UTCR0) {
u_int set = 0, clear = 0;
if (mctrl & TIOCM_RTS)
clear |= ASSABET_BCR_COM_RTS;
else
set |= ASSABET_BCR_COM_RTS;
if (mctrl & TIOCM_DTR)
clear |= ASSABET_BCR_COM_DTR;
else
set |= ASSABET_BCR_COM_DTR;
ASSABET_BCR_clear(clear);
ASSABET_BCR_set(set);
}
}
static u_int assabet_get_mctrl(struct uart_port *port)
{
u_int ret = 0;
u_int bsr = ASSABET_BSR;
/* need 2 reads to read current value */
bsr = ASSABET_BSR;
if (port->mapbase == _Ser1UTCR0) {
if (bsr & ASSABET_BSR_COM_DCD)
ret |= TIOCM_CD;
if (bsr & ASSABET_BSR_COM_CTS)
ret |= TIOCM_CTS;
if (bsr & ASSABET_BSR_COM_DSR)
ret |= TIOCM_DSR;
} else if (port->mapbase == _Ser3UTCR0) {
if (bsr & ASSABET_BSR_RAD_DCD)
ret |= TIOCM_CD;
if (bsr & ASSABET_BSR_RAD_CTS)
ret |= TIOCM_CTS;
if (bsr & ASSABET_BSR_RAD_DSR)
ret |= TIOCM_DSR;
if (bsr & ASSABET_BSR_RAD_RI)
ret |= TIOCM_RI;
} else {
ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
}
return ret;
}
static struct sa1100_port_fns assabet_port_fns __initdata = {
.set_mctrl = assabet_set_mctrl,
.get_mctrl = assabet_get_mctrl,
.pm = assabet_uart_pm,
};
static struct map_desc assabet_io_desc[] __initdata = {
{ /* Board Control Register */
.virtual = 0xf1000000,
.pfn = __phys_to_pfn(0x12000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* MQ200 */
.virtual = 0xf2800000,
.pfn = __phys_to_pfn(0x4b800000),
.length = 0x00800000,
.type = MT_DEVICE
}
};
static void __init assabet_map_io(void)
{
sa1100_map_io();
iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
/*
* Set SUS bit in SDCR0 so serial port 1 functions.
* Its called GPCLKR0 in my SA1110 manual.
*/
Ser1SDCR0 |= SDCR0_SUS;
if (!machine_has_neponset())
sa1100_register_uart_fns(&assabet_port_fns);
/*
* When Neponset is attached, the first UART should be
* UART3. That's what Angel is doing and many documents
* are stating this.
*
* We do the Neponset mapping even if Neponset support
* isn't compiled in so the user will still get something on
* the expected physical serial port.
*
* We no longer do this; not all boot loaders support it,
* and UART3 appears to be somewhat unreliable with blob.
*/
sa1100_register_uart(0, 1);
sa1100_register_uart(2, 3);
}
/* LEDs */
#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
struct assabet_led {
struct led_classdev cdev;
u32 mask;
};
/*
* The triggers lines up below will only be used if the
* LED triggers are compiled in.
*/
static const struct {
const char *name;
const char *trigger;
} assabet_leds[] = {
{ "assabet:red", "cpu0",},
{ "assabet:green", "heartbeat", },
};
/*
* The LED control in Assabet is reversed:
* - setting bit means turn off LED
* - clearing bit means turn on LED
*/
static void assabet_led_set(struct led_classdev *cdev,
enum led_brightness b)
{
struct assabet_led *led = container_of(cdev,
struct assabet_led, cdev);
if (b != LED_OFF)
ASSABET_BCR_clear(led->mask);
else
ASSABET_BCR_set(led->mask);
}
static enum led_brightness assabet_led_get(struct led_classdev *cdev)
{
struct assabet_led *led = container_of(cdev,
struct assabet_led, cdev);
return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
}
static int __init assabet_leds_init(void)
{
int i;
if (!machine_is_assabet())
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
struct assabet_led *led;
led = kzalloc(sizeof(*led), GFP_KERNEL);
if (!led)
break;
led->cdev.name = assabet_leds[i].name;
led->cdev.brightness_set = assabet_led_set;
led->cdev.brightness_get = assabet_led_get;
led->cdev.default_trigger = assabet_leds[i].trigger;
if (!i)
led->mask = ASSABET_BCR_LED_RED;
else
led->mask = ASSABET_BCR_LED_GREEN;
if (led_classdev_register(NULL, &led->cdev) < 0) {
kfree(led);
break;
}
}
return 0;
}
/*
* Since we may have triggers on any subsystem, defer registration
* until after subsystem_init.
*/
fs_initcall(assabet_leds_init);
#endif
MACHINE_START(ASSABET, "Intel-Assabet")
.atag_offset = 0x100,
.fixup = fixup_assabet,
.map_io = assabet_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = assabet_init,
.init_late = sa11x0_init_late,
#ifdef CONFIG_SA1111
.dma_zone_size = SZ_1M,
#endif
.restart = sa11x0_restart,
MACHINE_END

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arch/arm/mach-sa1100/badge4.c Normal file
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/*
* linux/arch/arm/mach-sa1100/badge4.c
*
* BadgePAD 4 specific initialization
*
* Tim Connors <connors@hpl.hp.com>
* Christopher Hoover <ch@hpl.hp.com>
*
* Copyright (C) 2002 Hewlett-Packard Company
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/tty.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <mach/irqs.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/hardware/sa1111.h>
#include <mach/badge4.h>
#include "generic.h"
static struct resource sa1111_resources[] = {
[0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000),
[1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111),
};
static int badge4_sa1111_enable(void *data, unsigned devid)
{
if (devid == SA1111_DEVID_USB)
badge4_set_5V(BADGE4_5V_USB, 1);
return 0;
}
static void badge4_sa1111_disable(void *data, unsigned devid)
{
if (devid == SA1111_DEVID_USB)
badge4_set_5V(BADGE4_5V_USB, 0);
}
static struct sa1111_platform_data sa1111_info = {
.disable_devs = SA1111_DEVID_PS2_MSE,
.enable = badge4_sa1111_enable,
.disable = badge4_sa1111_disable,
};
static u64 sa1111_dmamask = 0xffffffffUL;
static struct platform_device sa1111_device = {
.name = "sa1111",
.id = 0,
.dev = {
.dma_mask = &sa1111_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &sa1111_info,
},
.num_resources = ARRAY_SIZE(sa1111_resources),
.resource = sa1111_resources,
};
/* LEDs */
struct gpio_led badge4_gpio_leds[] = {
{
.name = "badge4:red",
.default_trigger = "heartbeat",
.gpio = 7,
},
{
.name = "badge4:green",
.default_trigger = "cpu0",
.gpio = 9,
},
};
static struct gpio_led_platform_data badge4_gpio_led_info = {
.leds = badge4_gpio_leds,
.num_leds = ARRAY_SIZE(badge4_gpio_leds),
};
static struct platform_device badge4_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &badge4_gpio_led_info,
}
};
static struct platform_device *devices[] __initdata = {
&sa1111_device,
&badge4_leds,
};
static int __init badge4_sa1111_init(void)
{
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state
*/
sa1110_mb_disable();
/*
* Probe for SA1111.
*/
return platform_add_devices(devices, ARRAY_SIZE(devices));
}
/*
* 1 x Intel 28F320C3 Advanced+ Boot Block Flash (32 Mi bit)
* Eight 4 KiW Parameter Bottom Blocks (64 KiB)
* Sixty-three 32 KiW Main Blocks (4032 Ki b)
*
* <or>
*
* 1 x Intel 28F640C3 Advanced+ Boot Block Flash (64 Mi bit)
* Eight 4 KiW Parameter Bottom Blocks (64 KiB)
* One-hundred-twenty-seven 32 KiW Main Blocks (8128 Ki b)
*/
static struct mtd_partition badge4_partitions[] = {
{
.name = "BLOB boot loader",
.offset = 0,
.size = 0x0000A000
}, {
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = 0x00006000
}, {
.name = "root",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL
}
};
static struct flash_platform_data badge4_flash_data = {
.map_name = "cfi_probe",
.parts = badge4_partitions,
.nr_parts = ARRAY_SIZE(badge4_partitions),
};
static struct resource badge4_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M);
static int five_v_on __initdata = 0;
static int __init five_v_on_setup(char *ignore)
{
five_v_on = 1;
return 1;
}
__setup("five_v_on", five_v_on_setup);
static int __init badge4_init(void)
{
int ret;
if (!machine_is_badge4())
return -ENODEV;
/* LCD */
GPCR = (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 |
BADGE4_GPIO_LGP6 | BADGE4_GPIO_LGP7 |
BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
BADGE4_GPIO_GPC_VID);
GPDR &= ~BADGE4_GPIO_INT_VID;
GPDR |= (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 |
BADGE4_GPIO_LGP6 | BADGE4_GPIO_LGP7 |
BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
BADGE4_GPIO_GPC_VID);
/* SDRAM SPD i2c */
GPCR = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
GPDR |= (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
/* uart */
GPCR = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
GPDR |= (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
/* CPLD muxsel0 input for mux/adc chip select */
GPCR = BADGE4_GPIO_MUXSEL0;
GPDR |= BADGE4_GPIO_MUXSEL0;
/* test points: J5, J6 as inputs, J7 outputs */
GPDR &= ~(BADGE4_GPIO_TESTPT_J5 | BADGE4_GPIO_TESTPT_J6);
GPCR = BADGE4_GPIO_TESTPT_J7;
GPDR |= BADGE4_GPIO_TESTPT_J7;
/* 5V supply rail. */
GPCR = BADGE4_GPIO_PCMEN5V; /* initially off */
GPDR |= BADGE4_GPIO_PCMEN5V;
/* CPLD sdram type inputs; set up by blob */
//GPDR |= (BADGE4_GPIO_SDTYP1 | BADGE4_GPIO_SDTYP0);
printk(KERN_DEBUG __FILE__ ": SDRAM CPLD typ1=%d typ0=%d\n",
!!(GPLR & BADGE4_GPIO_SDTYP1),
!!(GPLR & BADGE4_GPIO_SDTYP0));
/* SA1111 reset pin; set up by blob */
//GPSR = BADGE4_GPIO_SA1111_NRST;
//GPDR |= BADGE4_GPIO_SA1111_NRST;
/* power management cruft */
PGSR = 0;
PWER = 0;
PCFR = 0;
PSDR = 0;
PWER |= PWER_GPIO26; /* wake up on an edge from TESTPT_J5 */
PWER |= PWER_RTC; /* wake up if rtc fires */
/* drive sa1111_nrst during sleep */
PGSR |= BADGE4_GPIO_SA1111_NRST;
/* drive CPLD as is during sleep */
PGSR |= (GPLR & (BADGE4_GPIO_SDTYP0|BADGE4_GPIO_SDTYP1));
/* Now bring up the SA-1111. */
ret = badge4_sa1111_init();
if (ret < 0)
printk(KERN_ERR
"%s: SA-1111 initialization failed (%d)\n",
__func__, ret);
/* maybe turn on 5v0 from the start */
badge4_set_5V(BADGE4_5V_INITIALLY, five_v_on);
sa11x0_register_mtd(&badge4_flash_data, &badge4_flash_resource, 1);
return 0;
}
arch_initcall(badge4_init);
static unsigned badge4_5V_bitmap = 0;
void badge4_set_5V(unsigned subsystem, int on)
{
unsigned long flags;
unsigned old_5V_bitmap;
local_irq_save(flags);
old_5V_bitmap = badge4_5V_bitmap;
if (on) {
badge4_5V_bitmap |= subsystem;
} else {
badge4_5V_bitmap &= ~subsystem;
}
/* detect on->off and off->on transitions */
if ((!old_5V_bitmap) && (badge4_5V_bitmap)) {
/* was off, now on */
printk(KERN_INFO "%s: enabling 5V supply rail\n", __func__);
GPSR = BADGE4_GPIO_PCMEN5V;
} else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) {
/* was on, now off */
printk(KERN_INFO "%s: disabling 5V supply rail\n", __func__);
GPCR = BADGE4_GPIO_PCMEN5V;
}
local_irq_restore(flags);
}
EXPORT_SYMBOL(badge4_set_5V);
static struct map_desc badge4_io_desc[] __initdata = {
{ /* SRAM bank 1 */
.virtual = 0xf1000000,
.pfn = __phys_to_pfn(0x08000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* SRAM bank 2 */
.virtual = 0xf2000000,
.pfn = __phys_to_pfn(0x10000000),
.length = 0x00100000,
.type = MT_DEVICE
}
};
static void
badge4_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
if (!state) {
Ser1SDCR0 |= SDCR0_UART;
}
}
static struct sa1100_port_fns badge4_port_fns __initdata = {
//.get_mctrl = badge4_get_mctrl,
//.set_mctrl = badge4_set_mctrl,
.pm = badge4_uart_pm,
};
static void __init badge4_map_io(void)
{
sa1100_map_io();
iotable_init(badge4_io_desc, ARRAY_SIZE(badge4_io_desc));
sa1100_register_uart_fns(&badge4_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
.atag_offset = 0x100,
.map_io = badge4_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_late = sa11x0_init_late,
.init_time = sa1100_timer_init,
#ifdef CONFIG_SA1111
.dma_zone_size = SZ_1M,
#endif
.restart = sa11x0_restart,
MACHINE_END

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/*
* linux/arch/arm/mach-sa1100/cerf.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Apr-2003 : Removed some old PDA crud [FB]
* Oct-2003 : Added uart2 resource [FB]
* Jan-2004 : Removed io map for flash [FB]
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <mach/cerf.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/irqs.h>
#include "generic.h"
static struct resource cerfuart2_resources[] = {
[0] = DEFINE_RES_MEM(0x80030000, SZ_64K),
};
static struct platform_device cerfuart2_device = {
.name = "sa11x0-uart",
.id = 2,
.num_resources = ARRAY_SIZE(cerfuart2_resources),
.resource = cerfuart2_resources,
};
/* LEDs */
struct gpio_led cerf_gpio_leds[] = {
{
.name = "cerf:d0",
.default_trigger = "heartbeat",
.gpio = 0,
},
{
.name = "cerf:d1",
.default_trigger = "cpu0",
.gpio = 1,
},
{
.name = "cerf:d2",
.default_trigger = "default-on",
.gpio = 2,
},
{
.name = "cerf:d3",
.default_trigger = "default-on",
.gpio = 3,
},
};
static struct gpio_led_platform_data cerf_gpio_led_info = {
.leds = cerf_gpio_leds,
.num_leds = ARRAY_SIZE(cerf_gpio_leds),
};
static struct platform_device cerf_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cerf_gpio_led_info,
}
};
static struct platform_device *cerf_devices[] __initdata = {
&cerfuart2_device,
&cerf_leds,
};
#ifdef CONFIG_SA1100_CERF_FLASH_32MB
# define CERF_FLASH_SIZE 0x02000000
#elif defined CONFIG_SA1100_CERF_FLASH_16MB
# define CERF_FLASH_SIZE 0x01000000
#elif defined CONFIG_SA1100_CERF_FLASH_8MB
# define CERF_FLASH_SIZE 0x00800000
#else
# error "Undefined flash size for CERF"
#endif
static struct mtd_partition cerf_partitions[] = {
{
.name = "Bootloader",
.size = 0x00020000,
.offset = 0x00000000,
}, {
.name = "Params",
.size = 0x00040000,
.offset = 0x00020000,
}, {
.name = "Kernel",
.size = 0x00100000,
.offset = 0x00060000,
}, {
.name = "Filesystem",
.size = CERF_FLASH_SIZE-0x00160000,
.offset = 0x00160000,
}
};
static struct flash_platform_data cerf_flash_data = {
.map_name = "cfi_probe",
.parts = cerf_partitions,
.nr_parts = ARRAY_SIZE(cerf_partitions),
};
static struct resource cerf_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
static void __init cerf_init_irq(void)
{
sa1100_init_irq();
irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
}
static struct map_desc cerf_io_desc[] __initdata = {
{ /* Crystal Ethernet Chip */
.virtual = 0xf0000000,
.pfn = __phys_to_pfn(0x08000000),
.length = 0x00100000,
.type = MT_DEVICE
}
};
static void __init cerf_map_io(void)
{
sa1100_map_io();
iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 2); /* disable this and the uart2 device for sa1100_fir */
sa1100_register_uart(2, 1);
/* set some GPDR bits here while it's safe */
GPDR |= CERF_GPIO_CF_RESET;
}
static struct mcp_plat_data cerf_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
};
static void __init cerf_init(void)
{
sa11x0_ppc_configure_mcp();
platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
sa11x0_register_mcp(&cerf_mcp_data);
}
MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
/* Maintainer: support@intrinsyc.com */
.map_io = cerf_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = cerf_init_irq,
.init_time = sa1100_timer_init,
.init_machine = cerf_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

100
arch/arm/mach-sa1100/clock.c Normal file
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/*
* linux/arch/arm/mach-sa1100/clock.c
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <mach/hardware.h>
struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
};
struct clk {
const struct clkops *ops;
unsigned int enabled;
};
#define DEFINE_CLK(_name, _ops) \
struct clk clk_##_name = { \
.ops = _ops, \
}
static DEFINE_SPINLOCK(clocks_lock);
static void clk_gpio27_enable(struct clk *clk)
{
/*
* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
* (SA-1110 Developer's Manual, section 9.1.2.1)
*/
GAFR |= GPIO_32_768kHz;
GPDR |= GPIO_32_768kHz;
TUCR = TUCR_3_6864MHz;
}
static void clk_gpio27_disable(struct clk *clk)
{
TUCR = 0;
GPDR &= ~GPIO_32_768kHz;
GAFR &= ~GPIO_32_768kHz;
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
if (clk) {
spin_lock_irqsave(&clocks_lock, flags);
if (clk->enabled++ == 0)
clk->ops->enable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
}
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (clk) {
WARN_ON(clk->enabled == 0);
spin_lock_irqsave(&clocks_lock, flags);
if (--clk->enabled == 0)
clk->ops->disable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
}
}
EXPORT_SYMBOL(clk_disable);
const struct clkops clk_gpio27_ops = {
.enable = clk_gpio27_enable,
.disable = clk_gpio27_disable,
};
static DEFINE_CLK(gpio27, &clk_gpio27_ops);
static struct clk_lookup sa11xx_clkregs[] = {
CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
CLKDEV_INIT("sa1100-rtc", NULL, NULL),
};
static int __init sa11xx_clk_init(void)
{
clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
return 0;
}
core_initcall(sa11xx_clk_init);

406
arch/arm/mach-sa1100/collie.c Normal file
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/*
* linux/arch/arm/mach-sa1100/collie.c
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains all Collie-specific tweaks.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* ChangeLog:
* 2006 Pavel Machek <pavel@ucw.cz>
* 03-06-2004 John Lenz <lenz@cs.wisc.edu>
* 06-04-2002 Chris Larson <kergoth@digitalnemesis.net>
* 04-16-2001 Lineo Japan,Inc. ...
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/mfd/ucb1x00.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/timer.h>
#include <linux/gpio.h>
#include <linux/pda_power.h>
#include <video/sa1100fb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <mach/collie.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/hardware/scoop.h>
#include <asm/mach/sharpsl_param.h>
#include <asm/hardware/locomo.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/irqs.h>
#include "generic.h"
static struct resource collie_scoop_resources[] = {
[0] = DEFINE_RES_MEM(0x40800000, SZ_4K),
};
static struct scoop_config collie_scoop_setup = {
.io_dir = COLLIE_SCOOP_IO_DIR,
.io_out = COLLIE_SCOOP_IO_OUT,
.gpio_base = COLLIE_SCOOP_GPIO_BASE,
};
struct platform_device colliescoop_device = {
.name = "sharp-scoop",
.id = -1,
.dev = {
.platform_data = &collie_scoop_setup,
},
.num_resources = ARRAY_SIZE(collie_scoop_resources),
.resource = collie_scoop_resources,
};
static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = {
{
.dev = &colliescoop_device.dev,
.irq = COLLIE_IRQ_GPIO_CF_IRQ,
.cd_irq = COLLIE_IRQ_GPIO_CF_CD,
.cd_irq_str = "PCMCIA0 CD",
},
};
static struct scoop_pcmcia_config collie_pcmcia_config = {
.devs = &collie_pcmcia_scoop[0],
.num_devs = 1,
};
static struct ucb1x00_plat_data collie_ucb1x00_data = {
.gpio_base = COLLIE_TC35143_GPIO_BASE,
};
static struct mcp_plat_data collie_mcp_data = {
.mccr0 = MCCR0_ADM | MCCR0_ExtClk,
.sclk_rate = 9216000,
.codec_pdata = &collie_ucb1x00_data,
};
/*
* Collie AC IN
*/
static int collie_power_init(struct device *dev)
{
int ret = gpio_request(COLLIE_GPIO_AC_IN, "ac in");
if (ret)
goto err_gpio_req;
ret = gpio_direction_input(COLLIE_GPIO_AC_IN);
if (ret)
goto err_gpio_in;
return 0;
err_gpio_in:
gpio_free(COLLIE_GPIO_AC_IN);
err_gpio_req:
return ret;
}
static void collie_power_exit(struct device *dev)
{
gpio_free(COLLIE_GPIO_AC_IN);
}
static int collie_power_ac_online(void)
{
return gpio_get_value(COLLIE_GPIO_AC_IN) == 2;
}
static char *collie_ac_supplied_to[] = {
"main-battery",
"backup-battery",
};
static struct pda_power_pdata collie_power_data = {
.init = collie_power_init,
.is_ac_online = collie_power_ac_online,
.exit = collie_power_exit,
.supplied_to = collie_ac_supplied_to,
.num_supplicants = ARRAY_SIZE(collie_ac_supplied_to),
};
static struct resource collie_power_resource[] = {
{
.name = "ac",
.flags = IORESOURCE_IRQ |
IORESOURCE_IRQ_HIGHEDGE |
IORESOURCE_IRQ_LOWEDGE,
},
};
static struct platform_device collie_power_device = {
.name = "pda-power",
.id = -1,
.dev.platform_data = &collie_power_data,
.resource = collie_power_resource,
.num_resources = ARRAY_SIZE(collie_power_resource),
};
#ifdef CONFIG_SHARP_LOCOMO
/*
* low-level UART features.
*/
struct platform_device collie_locomo_device;
static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
{
if (mctrl & TIOCM_RTS)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
if (mctrl & TIOCM_DTR)
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
else
locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
}
static u_int collie_uart_get_mctrl(struct uart_port *port)
{
int ret = TIOCM_CD;
unsigned int r;
r = locomo_gpio_read_output(&collie_locomo_device.dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR);
if (r == -ENODEV)
return ret;
if (r & LOCOMO_GPIO_CTS)
ret |= TIOCM_CTS;
if (r & LOCOMO_GPIO_DSR)
ret |= TIOCM_DSR;
return ret;
}
static struct sa1100_port_fns collie_port_fns __initdata = {
.set_mctrl = collie_uart_set_mctrl,
.get_mctrl = collie_uart_get_mctrl,
};
static int collie_uart_probe(struct locomo_dev *dev)
{
return 0;
}
static int collie_uart_remove(struct locomo_dev *dev)
{
return 0;
}
static struct locomo_driver collie_uart_driver = {
.drv = {
.name = "collie_uart",
},
.devid = LOCOMO_DEVID_UART,
.probe = collie_uart_probe,
.remove = collie_uart_remove,
};
static int __init collie_uart_init(void)
{
return locomo_driver_register(&collie_uart_driver);
}
device_initcall(collie_uart_init);
#endif
static struct resource locomo_resources[] = {
[0] = DEFINE_RES_MEM(0x40000000, SZ_8K),
[1] = DEFINE_RES_IRQ(IRQ_GPIO25),
};
static struct locomo_platform_data locomo_info = {
.irq_base = IRQ_BOARD_START,
};
struct platform_device collie_locomo_device = {
.name = "locomo",
.id = 0,
.dev = {
.platform_data = &locomo_info,
},
.num_resources = ARRAY_SIZE(locomo_resources),
.resource = locomo_resources,
};
static struct platform_device *devices[] __initdata = {
&collie_locomo_device,
&colliescoop_device,
&collie_power_device,
};
static struct mtd_partition collie_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = 0x000C0000,
.mask_flags = MTD_WRITEABLE
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0x00100000,
}, {
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = 0x00e20000,
}
};
static int collie_flash_init(void)
{
int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable");
if (rc)
return rc;
rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1);
if (rc)
gpio_free(COLLIE_GPIO_VPEN);
return rc;
}
static void collie_set_vpp(int vpp)
{
gpio_set_value(COLLIE_GPIO_VPEN, vpp);
}
static void collie_flash_exit(void)
{
gpio_free(COLLIE_GPIO_VPEN);
}
static struct flash_platform_data collie_flash_data = {
.map_name = "cfi_probe",
.init = collie_flash_init,
.set_vpp = collie_set_vpp,
.exit = collie_flash_exit,
.parts = collie_partitions,
.nr_parts = ARRAY_SIZE(collie_partitions),
};
static struct resource collie_flash_resources[] = {
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
};
static struct sa1100fb_mach_info collie_lcd_info = {
.pixclock = 171521, .bpp = 16,
.xres = 320, .yres = 240,
.hsync_len = 5, .vsync_len = 1,
.left_margin = 11, .upper_margin = 2,
.right_margin = 30, .lower_margin = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
#ifdef CONFIG_BACKLIGHT_LOCOMO
.lcd_power = locomolcd_power
#endif
};
static void __init collie_init(void)
{
int ret = 0;
/* cpu initialize */
GAFR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK |
GPIO_MCP_CLK | GPIO_32_768kHz;
GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
_COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON |
_COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PWER = _COLLIE_GPIO_AC_IN | _COLLIE_GPIO_CO | _COLLIE_GPIO_ON_KEY |
_COLLIE_GPIO_WAKEUP | _COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
PGSR = _COLLIE_GPIO_nREMOCON_ON;
PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
PCFR = PCFR_OPDE;
GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
sa11x0_ppc_configure_mcp();
platform_scoop_config = &collie_pcmcia_config;
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if (ret) {
printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
}
sa11x0_register_lcd(&collie_lcd_info);
sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
ARRAY_SIZE(collie_flash_resources));
sa11x0_register_mcp(&collie_mcp_data);
sharpsl_save_param();
}
static struct map_desc collie_io_desc[] __initdata = {
{ /* 32M main flash (cs0) */
.virtual = 0xe8000000,
.pfn = __phys_to_pfn(0x00000000),
.length = 0x02000000,
.type = MT_DEVICE
}, { /* 32M boot flash (cs1) */
.virtual = 0xea000000,
.pfn = __phys_to_pfn(0x08000000),
.length = 0x02000000,
.type = MT_DEVICE
}
};
static void __init collie_map_io(void)
{
sa1100_map_io();
iotable_init(collie_io_desc, ARRAY_SIZE(collie_io_desc));
#ifdef CONFIG_SHARP_LOCOMO
sa1100_register_uart_fns(&collie_port_fns);
#endif
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
MACHINE_START(COLLIE, "Sharp-Collie")
.map_io = collie_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = collie_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

454
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/*
* linux/arch/arm/mach-sa1100/generic.c
*
* Author: Nicolas Pitre
*
* Code common to all SA11x0 machines.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <video/sa1100fb.h>
#include <asm/div64.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/irq.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "generic.h"
unsigned int reset_status;
EXPORT_SYMBOL(reset_status);
#define NR_FREQS 16
/*
* This table is setup for a 3.6864MHz Crystal.
*/
static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
590, /* 59.0 MHz */
737, /* 73.7 MHz */
885, /* 88.5 MHz */
1032, /* 103.2 MHz */
1180, /* 118.0 MHz */
1327, /* 132.7 MHz */
1475, /* 147.5 MHz */
1622, /* 162.2 MHz */
1769, /* 176.9 MHz */
1917, /* 191.7 MHz */
2064, /* 206.4 MHz */
2212, /* 221.2 MHz */
2359, /* 235.9 MHz */
2507, /* 250.7 MHz */
2654, /* 265.4 MHz */
2802 /* 280.2 MHz */
};
/* rounds up(!) */
unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
{
int i;
khz /= 100;
for (i = 0; i < NR_FREQS; i++)
if (cclk_frequency_100khz[i] >= khz)
break;
return i;
}
unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
{
unsigned int freq = 0;
if (idx < NR_FREQS)
freq = cclk_frequency_100khz[idx] * 100;
return freq;
}
/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
* this platform, anyway.
*/
int sa11x0_verify_speed(struct cpufreq_policy *policy)
{
unsigned int tmp;
if (policy->cpu)
return -EINVAL;
cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
/* make sure that at least one frequency is within the policy */
tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
if (tmp > policy->max)
policy->max = tmp;
cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
return 0;
}
unsigned int sa11x0_getspeed(unsigned int cpu)
{
if (cpu)
return 0;
return cclk_frequency_100khz[PPCR & 0xf] * 100;
}
/*
* Default power-off for SA1100
*/
static void sa1100_power_off(void)
{
mdelay(100);
local_irq_disable();
/* disable internal oscillator, float CS lines */
PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
/* enable wake-up on GPIO0 (Assabet...) */
PWER = GFER = GRER = 1;
/*
* set scratchpad to zero, just in case it is used as a
* restart address by the bootloader.
*/
PSPR = 0;
/* enter sleep mode */
PMCR = PMCR_SF;
}
void sa11x0_restart(char mode, const char *cmd)
{
if (mode == 's') {
/* Jump into ROM at address 0 */
soft_restart(0);
} else {
/* Use on-chip reset capability */
RSRR = RSRR_SWR;
}
}
static void sa11x0_register_device(struct platform_device *dev, void *data)
{
int err;
dev->dev.platform_data = data;
err = platform_device_register(dev);
if (err)
printk(KERN_ERR "Unable to register device %s: %d\n",
dev->name, err);
}
static struct resource sa11x0udc_resources[] = {
[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
};
static u64 sa11x0udc_dma_mask = 0xffffffffUL;
static struct platform_device sa11x0udc_device = {
.name = "sa11x0-udc",
.id = -1,
.dev = {
.dma_mask = &sa11x0udc_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(sa11x0udc_resources),
.resource = sa11x0udc_resources,
};
static struct resource sa11x0uart1_resources[] = {
[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
};
static struct platform_device sa11x0uart1_device = {
.name = "sa11x0-uart",
.id = 1,
.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
.resource = sa11x0uart1_resources,
};
static struct resource sa11x0uart3_resources[] = {
[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
};
static struct platform_device sa11x0uart3_device = {
.name = "sa11x0-uart",
.id = 3,
.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
.resource = sa11x0uart3_resources,
};
static struct resource sa11x0mcp_resources[] = {
[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
};
static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
static struct platform_device sa11x0mcp_device = {
.name = "sa11x0-mcp",
.id = -1,
.dev = {
.dma_mask = &sa11x0mcp_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
.resource = sa11x0mcp_resources,
};
void __init sa11x0_ppc_configure_mcp(void)
{
/* Setup the PPC unit for the MCP */
PPDR &= ~PPC_RXD4;
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PSDR |= PPC_RXD4;
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
}
void sa11x0_register_mcp(struct mcp_plat_data *data)
{
sa11x0_register_device(&sa11x0mcp_device, data);
}
static struct resource sa11x0ssp_resources[] = {
[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
};
static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
static struct platform_device sa11x0ssp_device = {
.name = "sa11x0-ssp",
.id = -1,
.dev = {
.dma_mask = &sa11x0ssp_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
.resource = sa11x0ssp_resources,
};
static struct resource sa11x0fb_resources[] = {
[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
[1] = DEFINE_RES_IRQ(IRQ_LCD),
};
static struct platform_device sa11x0fb_device = {
.name = "sa11x0-fb",
.id = -1,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(sa11x0fb_resources),
.resource = sa11x0fb_resources,
};
void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
{
sa11x0_register_device(&sa11x0fb_device, inf);
}
static struct platform_device sa11x0pcmcia_device = {
.name = "sa11x0-pcmcia",
.id = -1,
};
static struct platform_device sa11x0mtd_device = {
.name = "sa1100-mtd",
.id = -1,
};
void sa11x0_register_mtd(struct flash_platform_data *flash,
struct resource *res, int nr)
{
flash->name = "sa1100";
sa11x0mtd_device.resource = res;
sa11x0mtd_device.num_resources = nr;
sa11x0_register_device(&sa11x0mtd_device, flash);
}
static struct resource sa11x0ir_resources[] = {
DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
DEFINE_RES_IRQ(IRQ_Ser2ICP),
};
static struct platform_device sa11x0ir_device = {
.name = "sa11x0-ir",
.id = -1,
.num_resources = ARRAY_SIZE(sa11x0ir_resources),
.resource = sa11x0ir_resources,
};
void sa11x0_register_irda(struct irda_platform_data *irda)
{
sa11x0_register_device(&sa11x0ir_device, irda);
}
static struct resource sa1100_rtc_resources[] = {
DEFINE_RES_MEM(0x90010000, 0x40),
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};
static struct platform_device sa11x0rtc_device = {
.name = "sa1100-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(sa1100_rtc_resources),
.resource = sa1100_rtc_resources,
};
static struct resource sa11x0dma_resources[] = {
DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
DEFINE_RES_IRQ(IRQ_DMA0),
DEFINE_RES_IRQ(IRQ_DMA1),
DEFINE_RES_IRQ(IRQ_DMA2),
DEFINE_RES_IRQ(IRQ_DMA3),
DEFINE_RES_IRQ(IRQ_DMA4),
DEFINE_RES_IRQ(IRQ_DMA5),
};
static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
static struct platform_device sa11x0dma_device = {
.name = "sa11x0-dma",
.id = -1,
.dev = {
.dma_mask = &sa11x0dma_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(sa11x0dma_resources),
.resource = sa11x0dma_resources,
};
static struct platform_device *sa11x0_devices[] __initdata = {
&sa11x0udc_device,
&sa11x0uart1_device,
&sa11x0uart3_device,
&sa11x0ssp_device,
&sa11x0pcmcia_device,
&sa11x0rtc_device,
&sa11x0dma_device,
};
static int __init sa1100_init(void)
{
pm_power_off = sa1100_power_off;
return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}
arch_initcall(sa1100_init);
void __init sa11x0_init_late(void)
{
sa11x0_pm_init();
}
/*
* Common I/O mapping:
*
* Typically, static virtual address mappings are as follow:
*
* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
* 0xf4000000-0xf4ffffff: SA-1111
* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
* 0xffff0000-0xffff0fff: SA1100 exception vectors
* 0xffff2000-0xffff2fff: Minicache copy_user_page area
*
* Below 0xe8000000 is reserved for vm allocation.
*
* The machine specific code must provide the extra mapping beside the
* default mapping provided here.
*/
static struct map_desc standard_io_desc[] __initdata = {
{ /* PCM */
.virtual = 0xf8000000,
.pfn = __phys_to_pfn(0x80000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* SCM */
.virtual = 0xfa000000,
.pfn = __phys_to_pfn(0x90000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* MER */
.virtual = 0xfc000000,
.pfn = __phys_to_pfn(0xa0000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* LCD + DMA */
.virtual = 0xfe000000,
.pfn = __phys_to_pfn(0xb0000000),
.length = 0x00200000,
.type = MT_DEVICE
},
};
void __init sa1100_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}
/*
* Disable the memory bus request/grant signals on the SA1110 to
* ensure that we don't receive spurious memory requests. We set
* the MBGNT signal false to ensure the SA1111 doesn't own the
* SDRAM bus.
*/
void sa1110_mb_disable(void)
{
unsigned long flags;
local_irq_save(flags);
PGSR &= ~GPIO_MBGNT;
GPCR = GPIO_MBGNT;
GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
local_irq_restore(flags);
}
/*
* If the system is going to use the SA-1111 DMA engines, set up
* the memory bus request/grant pins.
*/
void sa1110_mb_enable(void)
{
unsigned long flags;
local_irq_save(flags);
PGSR &= ~GPIO_MBGNT;
GPCR = GPIO_MBGNT;
GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
TUCR |= TUCR_MR;
local_irq_restore(flags);
}

48
arch/arm/mach-sa1100/generic.h Normal file
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/*
* linux/arch/arm/mach-sa1100/generic.h
*
* Author: Nicolas Pitre
*/
extern void sa1100_timer_init(void);
extern void __init sa1100_map_io(void);
extern void __init sa1100_init_irq(void);
extern void __init sa1100_init_gpio(void);
extern void sa11x0_restart(char, const char *);
extern void sa11x0_init_late(void);
#define SET_BANK(__nr,__start,__size) \
mi->bank[__nr].start = (__start), \
mi->bank[__nr].size = (__size)
extern void sa1110_mb_enable(void);
extern void sa1110_mb_disable(void);
struct cpufreq_policy;
extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz);
extern int sa11x0_verify_speed(struct cpufreq_policy *policy);
extern unsigned int sa11x0_getspeed(unsigned int cpu);
extern unsigned int sa11x0_ppcr_to_freq(unsigned int idx);
struct flash_platform_data;
struct resource;
void sa11x0_register_mtd(struct flash_platform_data *flash,
struct resource *res, int nr);
struct irda_platform_data;
void sa11x0_register_irda(struct irda_platform_data *irda);
struct mcp_plat_data;
void sa11x0_ppc_configure_mcp(void);
void sa11x0_register_mcp(struct mcp_plat_data *data);
struct sa1100fb_mach_info;
void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
#ifdef CONFIG_PM
int sa11x0_pm_init(void);
#else
static inline int sa11x0_pm_init(void) { return 0; }
#endif

116
arch/arm/mach-sa1100/h3100.c Normal file
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/*
* Support for Compaq iPAQ H3100 handheld computer
*
* Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
* Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <video/sa1100fb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irda.h>
#include <mach/h3xxx.h>
#include <mach/irqs.h>
#include "generic.h"
/*
* helper for sa1100fb
*/
static void h3100_lcd_power(int enable)
{
if (!gpio_request(H3XXX_EGPIO_LCD_ON, "LCD ON")) {
gpio_set_value(H3100_GPIO_LCD_3V_ON, enable);
gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
gpio_free(H3XXX_EGPIO_LCD_ON);
} else {
pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
}
}
static struct sa1100fb_mach_info h3100_lcd_info = {
.pixclock = 406977, .bpp = 4,
.xres = 320, .yres = 240,
.hsync_len = 26, .vsync_len = 41,
.left_margin = 4, .upper_margin = 0,
.right_margin = 4, .lower_margin = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.cmap_greyscale = 1,
.cmap_inverse = 1,
.lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
.lcd_power = h3100_lcd_power,
};
static void __init h3100_map_io(void)
{
h3xxx_map_io();
/* Older bootldrs put GPIO2-9 in alternate mode on the
assumption that they are used for video */
GAFR &= ~0x000001fb;
}
/*
* This turns the IRDA power on or off on the Compaq H3100
*/
static int h3100_irda_set_power(struct device *dev, unsigned int state)
{
gpio_set_value(H3100_GPIO_IR_ON, state);
return 0;
}
static void h3100_irda_set_speed(struct device *dev, unsigned int speed)
{
gpio_set_value(H3100_GPIO_IR_FSEL, !(speed < 4000000));
}
static struct irda_platform_data h3100_irda_data = {
.set_power = h3100_irda_set_power,
.set_speed = h3100_irda_set_speed,
};
static struct gpio_default_state h3100_default_gpio[] = {
{ H3100_GPIO_IR_ON, GPIO_MODE_OUT0, "IrDA power" },
{ H3100_GPIO_IR_FSEL, GPIO_MODE_OUT0, "IrDA fsel" },
{ H3XXX_GPIO_COM_DCD, GPIO_MODE_IN, "COM DCD" },
{ H3XXX_GPIO_COM_CTS, GPIO_MODE_IN, "COM CTS" },
{ H3XXX_GPIO_COM_RTS, GPIO_MODE_OUT0, "COM RTS" },
{ H3100_GPIO_LCD_3V_ON, GPIO_MODE_OUT0, "LCD 3v" },
};
static void __init h3100_mach_init(void)
{
h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
h3xxx_mach_init();
sa11x0_register_lcd(&h3100_lcd_info);
sa11x0_register_irda(&h3100_irda_data);
}
MACHINE_START(H3100, "Compaq iPAQ H3100")
.atag_offset = 0x100,
.map_io = h3100_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = h3100_mach_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

166
arch/arm/mach-sa1100/h3600.c Normal file
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/*
* Support for Compaq iPAQ H3600 handheld computer
*
* Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
* Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <video/sa1100fb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irda.h>
#include <mach/h3xxx.h>
#include <mach/irqs.h>
#include "generic.h"
/*
* helper for sa1100fb
*/
static void h3600_lcd_power(int enable)
{
if (gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power")) {
pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
goto err1;
}
if (gpio_request(H3600_EGPIO_LCD_PCI, "LCD control")) {
pr_err("%s: can't request H3XXX_EGPIO_LCD_PCI\n", __func__);
goto err2;
}
if (gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v")) {
pr_err("%s: can't request H3XXX_EGPIO_LCD_5V_ON\n", __func__);
goto err3;
}
if (gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v")) {
pr_err("%s: can't request H3600_EGPIO_LVDD_ON\n", __func__);
goto err4;
}
gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
gpio_free(H3600_EGPIO_LVDD_ON);
err4: gpio_free(H3600_EGPIO_LCD_5V_ON);
err3: gpio_free(H3600_EGPIO_LCD_PCI);
err2: gpio_free(H3XXX_EGPIO_LCD_ON);
err1: return;
}
static const struct sa1100fb_rgb h3600_rgb_16 = {
.red = { .offset = 12, .length = 4, },
.green = { .offset = 7, .length = 4, },
.blue = { .offset = 1, .length = 4, },
.transp = { .offset = 0, .length = 0, },
};
static struct sa1100fb_mach_info h3600_lcd_info = {
.pixclock = 174757, .bpp = 16,
.xres = 320, .yres = 240,
.hsync_len = 3, .vsync_len = 3,
.left_margin = 12, .upper_margin = 10,
.right_margin = 17, .lower_margin = 1,
.cmap_static = 1,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
.rgb[RGB_16] = &h3600_rgb_16,
.lcd_power = h3600_lcd_power,
};
static void __init h3600_map_io(void)
{
h3xxx_map_io();
}
/*
* This turns the IRDA power on or off on the Compaq H3600
*/
static int h3600_irda_set_power(struct device *dev, unsigned int state)
{
gpio_set_value(H3600_EGPIO_IR_ON, state);
return 0;
}
static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
{
gpio_set_value(H3600_EGPIO_IR_FSEL, !(speed < 4000000));
}
static int h3600_irda_startup(struct device *dev)
{
int err = gpio_request(H3600_EGPIO_IR_ON, "IrDA power");
if (err)
goto err1;
err = gpio_direction_output(H3600_EGPIO_IR_ON, 0);
if (err)
goto err2;
err = gpio_request(H3600_EGPIO_IR_FSEL, "IrDA fsel");
if (err)
goto err2;
err = gpio_direction_output(H3600_EGPIO_IR_FSEL, 0);
if (err)
goto err3;
return 0;
err3: gpio_free(H3600_EGPIO_IR_FSEL);
err2: gpio_free(H3600_EGPIO_IR_ON);
err1: return err;
}
static void h3600_irda_shutdown(struct device *dev)
{
gpio_free(H3600_EGPIO_IR_ON);
gpio_free(H3600_EGPIO_IR_FSEL);
}
static struct irda_platform_data h3600_irda_data = {
.set_power = h3600_irda_set_power,
.set_speed = h3600_irda_set_speed,
.startup = h3600_irda_startup,
.shutdown = h3600_irda_shutdown,
};
static struct gpio_default_state h3600_default_gpio[] = {
{ H3XXX_GPIO_COM_DCD, GPIO_MODE_IN, "COM DCD" },
{ H3XXX_GPIO_COM_CTS, GPIO_MODE_IN, "COM CTS" },
{ H3XXX_GPIO_COM_RTS, GPIO_MODE_OUT0, "COM RTS" },
};
static void __init h3600_mach_init(void)
{
h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
h3xxx_mach_init();
sa11x0_register_lcd(&h3600_lcd_info);
sa11x0_register_irda(&h3600_irda_data);
}
MACHINE_START(H3600, "Compaq iPAQ H3600")
.atag_offset = 0x100,
.map_io = h3600_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = h3600_mach_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

306
arch/arm/mach-sa1100/h3xxx.c Normal file
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/*
* Support for Compaq iPAQ H3100 and H3600 handheld computers (common code)
*
* Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks)
* Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/mfd/htc-egpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <mach/h3xxx.h>
#include "generic.h"
void h3xxx_init_gpio(struct gpio_default_state *s, size_t n)
{
while (n--) {
const char *name = s->name;
int err;
if (!name)
name = "[init]";
err = gpio_request(s->gpio, name);
if (err) {
printk(KERN_ERR "gpio%u: unable to request: %d\n",
s->gpio, err);
continue;
}
if (s->mode >= 0) {
err = gpio_direction_output(s->gpio, s->mode);
} else {
err = gpio_direction_input(s->gpio);
}
if (err) {
printk(KERN_ERR "gpio%u: unable to set direction: %d\n",
s->gpio, err);
continue;
}
if (!s->name)
gpio_free(s->gpio);
s++;
}
}
/*
* H3xxx flash support
*/
static struct mtd_partition h3xxx_partitions[] = {
{
.name = "H3XXX boot firmware",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
.name = "H3XXX rootfs",
.size = MTDPART_SIZ_FULL,
.offset = 0x00040000,
}
};
static void h3xxx_set_vpp(int vpp)
{
gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp);
}
static int h3xxx_flash_init(void)
{
int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp");
if (err) {
pr_err("%s: can't request H3XXX_EGPIO_VPP_ON\n", __func__);
return err;
}
err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0);
if (err)
gpio_free(H3XXX_EGPIO_VPP_ON);
return err;
}
static void h3xxx_flash_exit(void)
{
gpio_free(H3XXX_EGPIO_VPP_ON);
}
static struct flash_platform_data h3xxx_flash_data = {
.map_name = "cfi_probe",
.set_vpp = h3xxx_set_vpp,
.init = h3xxx_flash_init,
.exit = h3xxx_flash_exit,
.parts = h3xxx_partitions,
.nr_parts = ARRAY_SIZE(h3xxx_partitions),
};
static struct resource h3xxx_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
/*
* H3xxx uart support
*/
static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl)
{
if (port->mapbase == _Ser3UTCR0) {
gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS));
}
}
static u_int h3xxx_uart_get_mctrl(struct uart_port *port)
{
u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
if (port->mapbase == _Ser3UTCR0) {
/*
* DCD and CTS bits are inverted in GPLR by RS232 transceiver
*/
if (gpio_get_value(H3XXX_GPIO_COM_DCD))
ret &= ~TIOCM_CD;
if (gpio_get_value(H3XXX_GPIO_COM_CTS))
ret &= ~TIOCM_CTS;
}
return ret;
}
static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
if (port->mapbase == _Ser3UTCR0) {
if (!gpio_request(H3XXX_EGPIO_RS232_ON, "RS232 transceiver")) {
gpio_direction_output(H3XXX_EGPIO_RS232_ON, !state);
gpio_free(H3XXX_EGPIO_RS232_ON);
} else {
pr_err("%s: can't request H3XXX_EGPIO_RS232_ON\n",
__func__);
}
}
}
/*
* Enable/Disable wake up events for this serial port.
* Obviously, we only support this on the normal COM port.
*/
static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable)
{
int err = -EINVAL;
if (port->mapbase == _Ser3UTCR0) {
if (enable)
PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */
else
PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */
err = 0;
}
return err;
}
static struct sa1100_port_fns h3xxx_port_fns __initdata = {
.set_mctrl = h3xxx_uart_set_mctrl,
.get_mctrl = h3xxx_uart_get_mctrl,
.pm = h3xxx_uart_pm,
.set_wake = h3xxx_uart_set_wake,
};
/*
* EGPIO
*/
static struct resource egpio_resources[] = {
[0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
};
static struct htc_egpio_chip egpio_chips[] = {
[0] = {
.reg_start = 0,
.gpio_base = H3XXX_EGPIO_BASE,
.num_gpios = 16,
.direction = HTC_EGPIO_OUTPUT,
.initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */
},
};
static struct htc_egpio_platform_data egpio_info = {
.reg_width = 16,
.bus_width = 16,
.chip = egpio_chips,
.num_chips = ARRAY_SIZE(egpio_chips),
};
static struct platform_device h3xxx_egpio = {
.name = "htc-egpio",
.id = -1,
.resource = egpio_resources,
.num_resources = ARRAY_SIZE(egpio_resources),
.dev = {
.platform_data = &egpio_info,
},
};
/*
* GPIO keys
*/
static struct gpio_keys_button h3xxx_button_table[] = {
{
.code = KEY_POWER,
.gpio = H3XXX_GPIO_PWR_BUTTON,
.desc = "Power Button",
.active_low = 1,
.type = EV_KEY,
.wakeup = 1,
}, {
.code = KEY_ENTER,
.gpio = H3XXX_GPIO_ACTION_BUTTON,
.active_low = 1,
.desc = "Action button",
.type = EV_KEY,
.wakeup = 0,
},
};
static struct gpio_keys_platform_data h3xxx_keys_data = {
.buttons = h3xxx_button_table,
.nbuttons = ARRAY_SIZE(h3xxx_button_table),
};
static struct platform_device h3xxx_keys = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &h3xxx_keys_data,
},
};
static struct platform_device *h3xxx_devices[] = {
&h3xxx_egpio,
&h3xxx_keys,
};
void __init h3xxx_mach_init(void)
{
sa1100_register_uart_fns(&h3xxx_port_fns);
sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
}
static struct map_desc h3600_io_desc[] __initdata = {
{ /* static memory bank 2 CS#2 */
.virtual = H3600_BANK_2_VIRT,
.pfn = __phys_to_pfn(SA1100_CS2_PHYS),
.length = 0x02800000,
.type = MT_DEVICE
}, { /* static memory bank 4 CS#4 */
.virtual = H3600_BANK_4_VIRT,
.pfn = __phys_to_pfn(SA1100_CS4_PHYS),
.length = 0x00800000,
.type = MT_DEVICE
}, { /* EGPIO 0 CS#5 */
.virtual = H3600_EGPIO_VIRT,
.pfn = __phys_to_pfn(H3600_EGPIO_PHYS),
.length = 0x01000000,
.type = MT_DEVICE
}
};
/*
* Common map_io initialization
*/
void __init h3xxx_map_io(void)
{
sa1100_map_io();
iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
sa1100_register_uart(0, 3); /* Common serial port */
// sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */
/* Ensure those pins are outputs and driving low */
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
/* Configure suspend conditions */
PGSR = 0;
PCFR = PCFR_OPDE;
PSDR = 0;
GPCR = 0x0fffffff; /* All outputs are set low by default */
GPDR = 0; /* Configure all GPIOs as input */
}

236
arch/arm/mach-sa1100/hackkit.c Normal file
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/*
* linux/arch/arm/mach-sa1100/hackkit.c
*
* Copyright (C) 2002 Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
*
* This file contains all HackKit tweaks. Based on original work from
* Nicolas Pitre's assabet fixes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/serial_core.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/tty.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "generic.h"
/**********************************************************************
* prototypes
*/
/* init funcs */
static void __init hackkit_map_io(void);
static u_int hackkit_get_mctrl(struct uart_port *port);
static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl);
static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate);
/**********************************************************************
* global data
*/
/**********************************************************************
* static data
*/
static struct map_desc hackkit_io_desc[] __initdata = {
{ /* Flash bank 0 */
.virtual = 0xe8000000,
.pfn = __phys_to_pfn(0x00000000),
.length = 0x01000000,
.type = MT_DEVICE
},
};
static struct sa1100_port_fns hackkit_port_fns __initdata = {
.set_mctrl = hackkit_set_mctrl,
.get_mctrl = hackkit_get_mctrl,
.pm = hackkit_uart_pm,
};
/**********************************************************************
* Static functions
*/
static void __init hackkit_map_io(void)
{
sa1100_map_io();
iotable_init(hackkit_io_desc, ARRAY_SIZE(hackkit_io_desc));
sa1100_register_uart_fns(&hackkit_port_fns);
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 3); /* radio module */
Ser1SDCR0 |= SDCR0_SUS;
}
/**
* hackkit_uart_pm - powermgmt callback function for system 3 UART
* @port: uart port structure
* @state: pm state
* @oldstate: old pm state
*
*/
static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
/* TODO: switch on/off uart in powersave mode */
}
/*
* Note! this can be called from IRQ context.
* FIXME: No modem ctrl lines yet.
*/
static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl)
{
#if 0
if (port->mapbase == _Ser1UTCR0) {
u_int set = 0, clear = 0;
if (mctrl & TIOCM_RTS)
set |= PT_CTRL2_RS1_RTS;
else
clear |= PT_CTRL2_RS1_RTS;
if (mctrl & TIOCM_DTR)
set |= PT_CTRL2_RS1_DTR;
else
clear |= PT_CTRL2_RS1_DTR;
PTCTRL2_clear(clear);
PTCTRL2_set(set);
}
#endif
}
static u_int hackkit_get_mctrl(struct uart_port *port)
{
u_int ret = 0;
#if 0
u_int irqsr = PT_IRQSR;
/* need 2 reads to read current value */
irqsr = PT_IRQSR;
/* TODO: check IRQ source register for modem/com
status lines and set them correctly. */
#endif
ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
return ret;
}
static struct mtd_partition hackkit_partitions[] = {
{
.name = "BLOB",
.size = 0x00040000,
.offset = 0x00000000,
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
.name = "config",
.size = 0x00040000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "kernel",
.size = 0x00100000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "initrd",
.size = 0x00180000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "rootfs",
.size = 0x700000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "data",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct flash_platform_data hackkit_flash_data = {
.map_name = "cfi_probe",
.parts = hackkit_partitions,
.nr_parts = ARRAY_SIZE(hackkit_partitions),
};
static struct resource hackkit_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
/* LEDs */
struct gpio_led hackkit_gpio_leds[] = {
{
.name = "hackkit:red",
.default_trigger = "cpu0",
.gpio = 22,
},
{
.name = "hackkit:green",
.default_trigger = "heartbeat",
.gpio = 23,
},
};
static struct gpio_led_platform_data hackkit_gpio_led_info = {
.leds = hackkit_gpio_leds,
.num_leds = ARRAY_SIZE(hackkit_gpio_leds),
};
static struct platform_device hackkit_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &hackkit_gpio_led_info,
}
};
static void __init hackkit_init(void)
{
sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
platform_device_register(&hackkit_leds);
}
/**********************************************************************
* Exported Functions
*/
MACHINE_START(HACKKIT, "HackKit Cpu Board")
.atag_offset = 0x100,
.map_io = hackkit_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = hackkit_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

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/*
* SA-1101.h
*
* Copyright (c) Peter Danielsson 1999
*
* Definition of constants related to the sa1101
* support chip for the sa1100
*
*/
/* Be sure that virtual mapping is defined right */
#ifndef __ASM_ARCH_HARDWARE_H
#error You must include hardware.h not SA-1101.h
#endif
#ifndef SA1101_BASE
#error You must define SA-1101 physical base address
#endif
#ifndef LANGUAGE
# ifdef __ASSEMBLY__
# define LANGUAGE Assembly
# else
# define LANGUAGE C
# endif
#endif
/*
* We have mapped the sa1101 depending on the value of SA1101_BASE.
* It then appears from 0xf4000000.
*/
#define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000)
#define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE)
#ifndef SA1101_p2v
#define SA1101_p2v(PhAdd) (PhAdd)
#endif
#include <mach/bitfield.h>
#define C 0
#define Assembly 1
/*
* Memory map
*/
#define __SHMEM_CONTROL0 0x00000000
#define __SYSTEM_CONTROL1 0x00000400
#define __ARBITER 0x00020000
#define __SYSTEM_CONTROL2 0x00040000
#define __SYSTEM_CONTROL3 0x00060000
#define __PARALLEL_PORT 0x00080000
#define __VIDMEM_CONTROL 0x00100000
#define __UPDATE_FIFO 0x00120000
#define __SHMEM_CONTROL1 0x00140000
#define __INTERRUPT_CONTROL 0x00160000
#define __USB_CONTROL 0x00180000
#define __TRACK_INTERFACE 0x001a0000
#define __MOUSE_INTERFACE 0x001b0000
#define __KEYPAD_INTERFACE 0x001c0000
#define __PCMCIA_INTERFACE 0x001e0000
#define __VGA_CONTROL 0x00200000
#define __GPIO_INTERFACE 0x00300000
/*
* Macro that calculates real address for registers in the SA-1101
*/
#define _SA1101( x ) ((x) + SA1101_BASE)
/*
* Interface and shared memory controller registers
*
* Registers
* SKCR SA-1101 control register (read/write)
* SMCR Shared Memory Controller Register
* SNPR Snoop Register
*/
#define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
#define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
#define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */
#if LANGUAGE == C
#define SKCR (*((volatile Word *) SA1101_p2v (_SKCR)))
#define SMCR (*((volatile Word *) SA1101_p2v (_SMCR)))
#define SNPR (*((volatile Word *) SA1101_p2v (_SNPR)))
#define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */
#define SKCR_BCLKEn 0x0002 /* Enables BCLK */
#define SKCR_Sleep 0x0004 /* Sleep Mode */
#define SKCR_IRefEn 0x0008 /* DAC Iref input enable */
#define SKCR_VCOON 0x0010 /* VCO bias */
#define SKCR_ScanTestEn 0x0020 /* Enables scan test */
#define SKCR_ClockTestEn 0x0040 /* Enables clock test */
#define SMCR_DCAC Fld(2,0) /* Number of column address bits */
#define SMCR_DRAC Fld(2,2) /* Number of row address bits */
#define SMCR_ArbiterBias 0x0008 /* favor video or USB */
#define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */
#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \
(( (x) - 8 ) << FShft (SMCR_DCAC))
#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\
(( (x) - 9 ) << FShft (SMCR_DRAC))
#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
#define SNPR_WholeBank (1 << 23) /* Whole bank bit */
#define SNPR_BankSelect Fld(2,27) /* Bank select */
#define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */
#define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \
( (x) << FShft (SNPR_VFBsize))
#define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \
(( (x) + 1 ) << FShft (SNPR_BankSelect ))
#endif /* LANGUAGE == C */
/*
* Video Memory Controller
*
* Registers
* VMCCR Configuration register
* VMCAR VMC address register
* VMCDR VMC data register
*
*/
#define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */
#define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */
#define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */
#if LANGUAGE == C
#define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR)))
#define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR)))
#define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR)))
#define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */
#define VMCCR_Config 0x0001 /* DRAM size */
#define VMCCR_RefPeriod Fld(2,3) /* Refresh period */
#define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */
#define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/
#define VMCCR_RefTest (1<<10) /* refresh test */
#define VMCCR_RefLow Fld(6,11) /* refresh low counter */
#define VMCCR_RefHigh Fld(7,17) /* refresh high counter */
#define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */
#define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */
#endif LANGUAGE == C
/* Update FIFO
*
* Registers
* UFCR Update FIFO Control Register
* UFSR Update FIFO Status Register
* UFLVLR update FIFO level register
* UFDR update FIFO data register
*/
#define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */
#define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */
#define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */
#define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */
#if LANGUAGE == C
#define UFCR (*((volatile Word *) SA1101_p2v (_UFCR)))
#define UFSR (*((volatile Word *) SA1101_p2v (_UFSR)))
#define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR)))
#define UFDR (*((volatile Word *) SA1101_p2v (_UFDR)))
#define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */
#define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */
#endif /* LANGUAGE == C */
/* System Controller
*
* Registers
* SKPCR Power Control Register
* SKCDR Clock Divider Register
* DACDR1 DAC1 Data register
* DACDR2 DAC2 Data register
*/
#define _SKPCR _SA1101(0x00000400)
#define _SKCDR _SA1101(0x00040000)
#define _DACDR1 _SA1101(0x00060000)
#define _DACDR2 _SA1101(0x00060400)
#if LANGUAGE == C
#define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR)))
#define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR)))
#define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1)))
#define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2)))
#define SKPCR_UCLKEn 0x01 /* USB Enable */
#define SKPCR_PCLKEn 0x02 /* PS/2 Enable */
#define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */
#define SKPCR_VCLKEn 0x08 /* Video Controller Enable */
#define SKPCR_PICLKEn 0x10 /* parallel port Enable */
#define SKPCR_DCLKEn 0x20 /* DACs Enable */
#define SKPCR_nKPADEn 0x40 /* Multiplexer */
#define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */
#define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */
#define SKDCR_BCLKEn (1<<9) /* BCLK Divider */
#define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */
#define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */
#define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */
#define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */
#define SKDCR_ChargePump (1<<25) /* Charge pump control */
#define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */
#define SKDCR_ClkTestEn (1<<27) /* Test clock generator */
#define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */
#define DACDR_DACCount Fld(8,0) /* Count value */
#define DACDR1_DACCount DACDR_DACCount
#define DACDR2_DACCount DACDR_DACCount
#endif /* LANGUAGE == C */
/*
* Parallel Port Interface
*
* Registers
* IEEE_Config IEEE mode selection and programmable attributes
* IEEE_Control Controls the states of IEEE port control outputs
* IEEE_Data Forward transfer data register
* IEEE_Addr Forward transfer address register
* IEEE_Status Port IO signal status register
* IEEE_IntStatus Port interrupts status register
* IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels
* IEEE_InitTime Forward timeout counter initial value
* IEEE_TimerStatus Forward timeout counter current value
* IEEE_FifoReset Reset forward transfer FIFO
* IEEE_ReloadValue Counter reload value
* IEEE_TestControl Control testmode
* IEEE_TestDataIn Test data register
* IEEE_TestDataInEn Enable test data
* IEEE_TestCtrlIn Test control signals
* IEEE_TestCtrlInEn Enable test control signals
* IEEE_TestDataStat Current data bus value
*
*/
/*
* The control registers are defined as offsets from a base address
*/
#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
#define _IEEE_Config _IEEE( 0x0000 )
#define _IEEE_Control _IEEE( 0x0400 )
#define _IEEE_Data _IEEE( 0x4000 )
#define _IEEE_Addr _IEEE( 0x0800 )
#define _IEEE_Status _IEEE( 0x0c00 )
#define _IEEE_IntStatus _IEEE( 0x1000 )
#define _IEEE_FifoLevels _IEEE( 0x1400 )
#define _IEEE_InitTime _IEEE( 0x1800 )
#define _IEEE_TimerStatus _IEEE( 0x1c00 )
#define _IEEE_FifoReset _IEEE( 0x2000 )
#define _IEEE_ReloadValue _IEEE( 0x3c00 )
#define _IEEE_TestControl _IEEE( 0x2400 )
#define _IEEE_TestDataIn _IEEE( 0x2800 )
#define _IEEE_TestDataInEn _IEEE( 0x2c00 )
#define _IEEE_TestCtrlIn _IEEE( 0x3000 )
#define _IEEE_TestCtrlInEn _IEEE( 0x3400 )
#define _IEEE_TestDataStat _IEEE( 0x3800 )
#if LANGUAGE == C
#define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
#define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
#define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
#define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
#define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
#define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
#define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
#define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
#define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
#define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
#define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
#define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
#define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
#define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
#define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
#define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
#define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
#define IEEE_Config_M Fld(3,0) /* Mode select */
#define IEEE_Config_D 0x04 /* FIFO access enable */
#define IEEE_Config_B 0x08 /* 9-bit word enable */
#define IEEE_Config_T 0x10 /* Data transfer enable */
#define IEEE_Config_A 0x20 /* Data transfer direction */
#define IEEE_Config_E 0x40 /* Timer enable */
#define IEEE_Control_A 0x08 /* AutoFd output */
#define IEEE_Control_E 0x04 /* Selectin output */
#define IEEE_Control_T 0x02 /* Strobe output */
#define IEEE_Control_I 0x01 /* Port init output */
#define IEEE_Data_C (1<<31) /* Byte count */
#define IEEE_Data_Db Fld(9,16) /* Data byte 2 */
#define IEEE_Data_Da Fld(9,0) /* Data byte 1 */
#define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */
#define IEEE_Status_A 0x0100 /* nAutoFd port output status */
#define IEEE_Status_E 0x0080 /* nSelectIn port output status */
#define IEEE_Status_T 0x0040 /* nStrobe port output status */
#define IEEE_Status_I 0x0020 /* nInit port output status */
#define IEEE_Status_B 0x0010 /* Busy port inout status */
#define IEEE_Status_S 0x0008 /* Select port input status */
#define IEEE_Status_K 0x0004 /* nAck port input status */
#define IEEE_Status_F 0x0002 /* nFault port input status */
#define IEEE_Status_R 0x0001 /* pError port input status */
#define IEEE_IntStatus_IntReqDat 0x0100
#define IEEE_IntStatus_IntReqEmp 0x0080
#define IEEE_IntStatus_IntReqInt 0x0040
#define IEEE_IntStatus_IntReqRav 0x0020
#define IEEE_IntStatus_IntReqTim 0x0010
#define IEEE_IntStatus_RevAddrComp 0x0008
#define IEEE_IntStatus_RevDataComp 0x0004
#define IEEE_IntStatus_FwdAddrComp 0x0002
#define IEEE_IntStatus_FwdDataComp 0x0001
#define IEEE_FifoLevels_RevFifoLevel 2
#define IEEE_FifoLevels_FwdFifoLevel 1
#define IEEE_InitTime_TimValInit Fld(22,0)
#define IEEE_TimerStatus_TimValStat Fld(22,0)
#define IEEE_ReloadValue_Reload Fld(4,0)
#define IEEE_TestControl_RegClk 0x04
#define IEEE_TestControl_ClockSelect Fld(2,1)
#define IEEE_TestControl_TimerTestModeEn 0x01
#define IEEE_TestCtrlIn_PError 0x10
#define IEEE_TestCtrlIn_nFault 0x08
#define IEEE_TestCtrlIn_nAck 0x04
#define IEEE_TestCtrlIn_PSel 0x02
#define IEEE_TestCtrlIn_Busy 0x01
#endif /* LANGUAGE == C */
/*
* VGA Controller
*
* Registers
* VideoControl Video Control Register
* VgaTiming0 VGA Timing Register 0
* VgaTiming1 VGA Timing Register 1
* VgaTiming2 VGA Timing Register 2
* VgaTiming3 VGA Timing Register 3
* VgaBorder VGA Border Color Register
* VgaDBAR VGADMA Base Address Register
* VgaDCAR VGADMA Channel Current Address Register
* VgaStatus VGA Status Register
* VgaInterruptMask VGA Interrupt Mask Register
* VgaPalette VGA Palette Registers
* DacControl DAC Control Register
* VgaTest VGA Controller Test Register
*/
#define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL )
#define _VideoControl _VGA( 0x0000 )
#define _VgaTiming0 _VGA( 0x0400 )
#define _VgaTiming1 _VGA( 0x0800 )
#define _VgaTiming2 _VGA( 0x0c00 )
#define _VgaTiming3 _VGA( 0x1000 )
#define _VgaBorder _VGA( 0x1400 )
#define _VgaDBAR _VGA( 0x1800 )
#define _VgaDCAR _VGA( 0x1c00 )
#define _VgaStatus _VGA( 0x2000 )
#define _VgaInterruptMask _VGA( 0x2400 )
#define _VgaPalette _VGA( 0x40000 )
#define _DacControl _VGA( 0x3000 )
#define _VgaTest _VGA( 0x2c00 )
#if (LANGUAGE == C)
#define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl)))
#define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
#define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
#define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
#define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
#define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder)))
#define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
#define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus)))
#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette)))
#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)))
#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest)))
#define VideoControl_VgaEn 0x00000000
#define VideoControl_BGR 0x00000001
#define VideoControl_VCompVal Fld(2,2)
#define VideoControl_VgaReq Fld(4,4)
#define VideoControl_VBurstL Fld(4,8)
#define VideoControl_VMode (1<<12)
#define VideoControl_PalRead (1<<13)
#define VgaTiming0_PPL Fld(6,2)
#define VgaTiming0_HSW Fld(8,8)
#define VgaTiming0_HFP Fld(8,16)
#define VgaTiming0_HBP Fld(8,24)
#define VgaTiming1_LPS Fld(10,0)
#define VgaTiming1_VSW Fld(6,10)
#define VgaTiming1_VFP Fld(8,16)
#define VgaTiming1_VBP Fld(8,24)
#define VgaTiming2_IVS 0x01
#define VgaTiming2_IHS 0x02
#define VgaTiming2_CVS 0x04
#define VgaTiming2_CHS 0x08
#define VgaTiming3_HBS Fld(8,0)
#define VgaTiming3_HBE Fld(8,8)
#define VgaTiming3_VBS Fld(8,16)
#define VgaTiming3_VBE Fld(8,24)
#define VgaBorder_BCOL Fld(24,0)
#define VgaStatus_VFUF 0x01
#define VgaStatus_VNext 0x02
#define VgaStatus_VComp 0x04
#define VgaInterruptMask_VFUFMask 0x00
#define VgaInterruptMask_VNextMask 0x01
#define VgaInterruptMask_VCompMask 0x02
#define VgaPalette_R Fld(8,0)
#define VgaPalette_G Fld(8,8)
#define VgaPalette_B Fld(8,16)
#define DacControl_DACON 0x0001
#define DacControl_COMPON 0x0002
#define DacControl_PEDON 0x0004
#define DacControl_RTrim Fld(5,4)
#define DacControl_GTrim Fld(5,9)
#define DacControl_BTrim Fld(5,14)
#define VgaTest_TDAC 0x00
#define VgaTest_Datatest Fld(4,1)
#define VgaTest_DACTESTDAC 0x10
#define VgaTest_DACTESTOUT Fld(3,5)
#endif /* LANGUAGE == C */
/*
* USB Host Interface Controller
*
* Registers
* Revision
* Control
* CommandStatus
* InterruptStatus
* InterruptEnable
* HCCA
* PeriodCurrentED
* ControlHeadED
* BulkHeadED
* BulkCurrentED
* DoneHead
* FmInterval
* FmRemaining
* FmNumber
* PeriodicStart
* LSThreshold
* RhDescriptorA
* RhDescriptorB
* RhStatus
* RhPortStatus
* USBStatus
* USBReset
* USTAR
* USWER
* USRFR
* USNFR
* USTCSR
* USSR
*
*/
#define _USB( x ) _SA1101( ( x ) + __USB_CONTROL )
#define _Revision _USB( 0x0000 )
#define _Control _USB( 0x0888 )
#define _CommandStatus _USB( 0x0c00 )
#define _InterruptStatus _USB( 0x1000 )
#define _InterruptEnable _USB( 0x1400 )
#define _HCCA _USB( 0x1800 )
#define _PeriodCurrentED _USB( 0x1c00 )
#define _ControlHeadED _USB( 0x2000 )
#define _BulkHeadED _USB( 0x2800 )
#define _BulkCurrentED _USB( 0x2c00 )
#define _DoneHead _USB( 0x3000 )
#define _FmInterval _USB( 0x3400 )
#define _FmRemaining _USB( 0x3800 )
#define _FmNumber _USB( 0x3c00 )
#define _PeriodicStart _USB( 0x4000 )
#define _LSThreshold _USB( 0x4400 )
#define _RhDescriptorA _USB( 0x4800 )
#define _RhDescriptorB _USB( 0x4c00 )
#define _RhStatus _USB( 0x5000 )
#define _RhPortStatus _USB( 0x5400 )
#define _USBStatus _USB( 0x11800 )
#define _USBReset _USB( 0x11c00 )
#define _USTAR _USB( 0x10400 )
#define _USWER _USB( 0x10800 )
#define _USRFR _USB( 0x10c00 )
#define _USNFR _USB( 0x11000 )
#define _USTCSR _USB( 0x11400 )
#define _USSR _USB( 0x11800 )
#if (LANGUAGE == C)
#define Revision (*((volatile Word *) SA1101_p2v (_Revision)))
#define Control (*((volatile Word *) SA1101_p2v (_Control)))
#define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus)))
#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
#define HCCA (*((volatile Word *) SA1101_p2v (_HCCA)))
#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
#define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
#define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
#define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
#define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead)))
#define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval)))
#define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining)))
#define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber)))
#define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
#define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold)))
#define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
#define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
#define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus)))
#define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
#define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus)))
#define USBReset (*((volatile Word *) SA1101_p2v (_USBReset)))
#define USTAR (*((volatile Word *) SA1101_p2v (_USTAR)))
#define USWER (*((volatile Word *) SA1101_p2v (_USWER)))
#define USRFR (*((volatile Word *) SA1101_p2v (_USRFR)))
#define USNFR (*((volatile Word *) SA1101_p2v (_USNFR)))
#define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR)))
#define USSR (*((volatile Word *) SA1101_p2v (_USSR)))
#define USBStatus_IrqHciRmtWkp (1<<7)
#define USBStatus_IrqHciBuffAcc (1<<8)
#define USBStatus_nIrqHciM (1<<9)
#define USBStatus_nHciMFClr (1<<10)
#define USBReset_ForceIfReset 0x01
#define USBReset_ForceHcReset 0x02
#define USBReset_ClkGenReset 0x04
#define USTCR_RdBstCntrl Fld(3,0)
#define USTCR_ByteEnable Fld(4,3)
#define USTCR_WriteEn (1<<7)
#define USTCR_FifoCir (1<<8)
#define USTCR_TestXferSel (1<<9)
#define USTCR_FifoCirAtEnd (1<<10)
#define USTCR_nSimScaleDownClk (1<<11)
#define USSR_nAppMDEmpty 0x01
#define USSR_nAppMDFirst 0x02
#define USSR_nAppMDLast 0x04
#define USSR_nAppMDFull 0x08
#define USSR_nAppMAFull 0x10
#define USSR_XferReq 0x20
#define USSR_XferEnd 0x40
#endif /* LANGUAGE == C */
/*
* Interrupt Controller
*
* Registers
* INTTEST0 Test register 0
* INTTEST1 Test register 1
* INTENABLE0 Interrupt Enable register 0
* INTENABLE1 Interrupt Enable register 1
* INTPOL0 Interrupt Polarity selection 0
* INTPOL1 Interrupt Polarity selection 1
* INTTSTSEL Interrupt source selection
* INTSTATCLR0 Interrupt Status 0
* INTSTATCLR1 Interrupt Status 1
* INTSET0 Interrupt Set 0
* INTSET1 Interrupt Set 1
*/
#define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL)
#define _INTTEST0 _INT( 0x1000 )
#define _INTTEST1 _INT( 0x1400 )
#define _INTENABLE0 _INT( 0x2000 )
#define _INTENABLE1 _INT( 0x2400 )
#define _INTPOL0 _INT( 0x3000 )
#define _INTPOL1 _INT( 0x3400 )
#define _INTTSTSEL _INT( 0x5000 )
#define _INTSTATCLR0 _INT( 0x6000 )
#define _INTSTATCLR1 _INT( 0x6400 )
#define _INTSET0 _INT( 0x7000 )
#define _INTSET1 _INT( 0x7400 )
#if ( LANGUAGE == C )
#define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0)))
#define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1)))
#define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
#define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
#define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0)))
#define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1)))
#define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
#define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
#define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
#define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0)))
#define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1)))
#endif /* LANGUAGE == C */
/*
* PS/2 Trackpad and Mouse Interfaces
*
* Registers (prefix kbd applies to trackpad interface, mse to mouse)
* KBDCR Control Register
* KBDSTAT Status Register
* KBDDATA Transmit/Receive Data register
* KBDCLKDIV Clock Division Register
* KBDPRECNT Clock Precount Register
* KBDTEST1 Test register 1
* KBDTEST2 Test register 2
* KBDTEST3 Test register 3
* KBDTEST4 Test register 4
* MSECR
* MSESTAT
* MSEDATA
* MSECLKDIV
* MSEPRECNT
* MSETEST1
* MSETEST2
* MSETEST3
* MSETEST4
*
*/
#define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE )
#define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE )
#define _KBDCR _KBD( 0x0000 )
#define _KBDSTAT _KBD( 0x0400 )
#define _KBDDATA _KBD( 0x0800 )
#define _KBDCLKDIV _KBD( 0x0c00 )
#define _KBDPRECNT _KBD( 0x1000 )
#define _KBDTEST1 _KBD( 0x2000 )
#define _KBDTEST2 _KBD( 0x2400 )
#define _KBDTEST3 _KBD( 0x2800 )
#define _KBDTEST4 _KBD( 0x2c00 )
#define _MSECR _MSE( 0x0000 )
#define _MSESTAT _MSE( 0x0400 )
#define _MSEDATA _MSE( 0x0800 )
#define _MSECLKDIV _MSE( 0x0c00 )
#define _MSEPRECNT _MSE( 0x1000 )
#define _MSETEST1 _MSE( 0x2000 )
#define _MSETEST2 _MSE( 0x2400 )
#define _MSETEST3 _MSE( 0x2800 )
#define _MSETEST4 _MSE( 0x2c00 )
#if ( LANGUAGE == C )
#define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR)))
#define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
#define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA)))
#define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
#define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
#define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
#define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
#define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
#define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
#define MSECR (*((volatile Word *) SA1101_p2v (_MSECR)))
#define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT)))
#define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA)))
#define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
#define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
#define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1)))
#define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2)))
#define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3)))
#define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4)))
#define KBDCR_ENA 0x08
#define KBDCR_FKD 0x02
#define KBDCR_FKC 0x01
#define KBDSTAT_TXE 0x80
#define KBDSTAT_TXB 0x40
#define KBDSTAT_RXF 0x20
#define KBDSTAT_RXB 0x10
#define KBDSTAT_ENA 0x08
#define KBDSTAT_RXP 0x04
#define KBDSTAT_KBD 0x02
#define KBDSTAT_KBC 0x01
#define KBDCLKDIV_DivVal Fld(4,0)
#define MSECR_ENA 0x08
#define MSECR_FKD 0x02
#define MSECR_FKC 0x01
#define MSESTAT_TXE 0x80
#define MSESTAT_TXB 0x40
#define MSESTAT_RXF 0x20
#define MSESTAT_RXB 0x10
#define MSESTAT_ENA 0x08
#define MSESTAT_RXP 0x04
#define MSESTAT_MSD 0x02
#define MSESTAT_MSC 0x01
#define MSECLKDIV_DivVal Fld(4,0)
#define KBDTEST1_CD 0x80
#define KBDTEST1_RC1 0x40
#define KBDTEST1_MC 0x20
#define KBDTEST1_C Fld(2,3)
#define KBDTEST1_T2 0x40
#define KBDTEST1_T1 0x20
#define KBDTEST1_T0 0x10
#define KBDTEST2_TICBnRES 0x08
#define KBDTEST2_RKC 0x04
#define KBDTEST2_RKD 0x02
#define KBDTEST2_SEL 0x01
#define KBDTEST3_ms_16 0x80
#define KBDTEST3_us_64 0x40
#define KBDTEST3_us_16 0x20
#define KBDTEST3_DIV8 0x10
#define KBDTEST3_DIn 0x08
#define KBDTEST3_CIn 0x04
#define KBDTEST3_KD 0x02
#define KBDTEST3_KC 0x01
#define KBDTEST4_BC12 0x80
#define KBDTEST4_BC11 0x40
#define KBDTEST4_TRES 0x20
#define KBDTEST4_CLKOE 0x10
#define KBDTEST4_CRES 0x08
#define KBDTEST4_RXB 0x04
#define KBDTEST4_TXB 0x02
#define KBDTEST4_SRX 0x01
#define MSETEST1_CD 0x80
#define MSETEST1_RC1 0x40
#define MSETEST1_MC 0x20
#define MSETEST1_C Fld(2,3)
#define MSETEST1_T2 0x40
#define MSETEST1_T1 0x20
#define MSETEST1_T0 0x10
#define MSETEST2_TICBnRES 0x08
#define MSETEST2_RKC 0x04
#define MSETEST2_RKD 0x02
#define MSETEST2_SEL 0x01
#define MSETEST3_ms_16 0x80
#define MSETEST3_us_64 0x40
#define MSETEST3_us_16 0x20
#define MSETEST3_DIV8 0x10
#define MSETEST3_DIn 0x08
#define MSETEST3_CIn 0x04
#define MSETEST3_KD 0x02
#define MSETEST3_KC 0x01
#define MSETEST4_BC12 0x80
#define MSETEST4_BC11 0x40
#define MSETEST4_TRES 0x20
#define MSETEST4_CLKOE 0x10
#define MSETEST4_CRES 0x08
#define MSETEST4_RXB 0x04
#define MSETEST4_TXB 0x02
#define MSETEST4_SRX 0x01
#endif /* LANGUAGE == C */
/*
* General-Purpose I/O Interface
*
* Registers
* PADWR Port A Data Write Register
* PBDWR Port B Data Write Register
* PADRR Port A Data Read Register
* PBDRR Port B Data Read Register
* PADDR Port A Data Direction Register
* PBDDR Port B Data Direction Register
* PASSR Port A Sleep State Register
* PBSSR Port B Sleep State Register
*
*/
#define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE )
#define _PADWR _PIO( 0x0000 )
#define _PBDWR _PIO( 0x0400 )
#define _PADRR _PIO( 0x0000 )
#define _PBDRR _PIO( 0x0400 )
#define _PADDR _PIO( 0x0800 )
#define _PBDDR _PIO( 0x0c00 )
#define _PASSR _PIO( 0x1000 )
#define _PBSSR _PIO( 0x1400 )
#if ( LANGUAGE == C )
#define PADWR (*((volatile Word *) SA1101_p2v (_PADWR)))
#define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR)))
#define PADRR (*((volatile Word *) SA1101_p2v (_PADRR)))
#define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR)))
#define PADDR (*((volatile Word *) SA1101_p2v (_PADDR)))
#define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR)))
#define PASSR (*((volatile Word *) SA1101_p2v (_PASSR)))
#define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR)))
#endif
/*
* Keypad Interface
*
* Registers
* PXDWR
* PXDRR
* PYDWR
* PYDRR
*
*/
#define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE )
#define _PXDWR _KEYPAD( 0x0000 )
#define _PXDRR _KEYPAD( 0x0000 )
#define _PYDWR _KEYPAD( 0x0400 )
#define _PYDRR _KEYPAD( 0x0400 )
#if ( LANGUAGE == C )
#define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR)))
#define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR)))
#define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR)))
#define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR)))
#endif
/*
* PCMCIA Interface
*
* Registers
* PCSR Status Register
* PCCR Control Register
* PCSSR Sleep State Register
*
*/
#define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE )
#define _PCSR _CARD( 0x0000 )
#define _PCCR _CARD( 0x0400 )
#define _PCSSR _CARD( 0x0800 )
#if ( LANGUAGE == C )
#define PCSR (*((volatile Word *) SA1101_p2v (_PCSR)))
#define PCCR (*((volatile Word *) SA1101_p2v (_PCCR)))
#define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR)))
#define PCSR_S0_ready 0x0001
#define PCSR_S1_ready 0x0002
#define PCSR_S0_detected 0x0004
#define PCSR_S1_detected 0x0008
#define PCSR_S0_VS1 0x0010
#define PCSR_S0_VS2 0x0020
#define PCSR_S1_VS1 0x0040
#define PCSR_S1_VS2 0x0080
#define PCSR_S0_WP 0x0100
#define PCSR_S1_WP 0x0200
#define PCSR_S0_BVD1_nSTSCHG 0x0400
#define PCSR_S0_BVD2_nSPKR 0x0800
#define PCSR_S1_BVD1_nSTSCHG 0x1000
#define PCSR_S1_BVD2_nSPKR 0x2000
#define PCCR_S0_VPP0 0x0001
#define PCCR_S0_VPP1 0x0002
#define PCCR_S0_VCC0 0x0004
#define PCCR_S0_VCC1 0x0008
#define PCCR_S1_VPP0 0x0010
#define PCCR_S1_VPP1 0x0020
#define PCCR_S1_VCC0 0x0040
#define PCCR_S1_VCC1 0x0080
#define PCCR_S0_reset 0x0100
#define PCCR_S1_reset 0x0200
#define PCCR_S0_float 0x0400
#define PCCR_S1_float 0x0800
#define PCSSR_S0_VCC0 0x0001
#define PCSSR_S0_VCC1 0x0002
#define PCSSR_S0_VPP0 0x0004
#define PCSSR_S0_VPP1 0x0008
#define PCSSR_S0_control 0x0010
#define PCSSR_S1_VCC0 0x0020
#define PCSSR_S1_VCC1 0x0040
#define PCSSR_S1_VPP0 0x0080
#define PCSSR_S1_VPP1 0x0100
#define PCSSR_S1_control 0x0200
#endif
#undef C
#undef Assembly

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/*
* arch/arm/mach-sa1100/include/mach/assabet.h
*
* Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
*
* This file contains the hardware specific definitions for Assabet
* Only include this file from SA1100-specific files.
*
* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
* Definitions for Neponset added.
*/
#ifndef __ASM_ARCH_ASSABET_H
#define __ASM_ARCH_ASSABET_H
/* System Configuration Register flags */
#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */
#define ASSABET_SCR_INIT -1
extern unsigned long SCR_value;
#ifdef CONFIG_ASSABET_NEPONSET
#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0)
#else
#define machine_has_neponset() (0)
#endif
/* Board Control Register */
#define ASSABET_BCR_BASE 0xf1000000
#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
#define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
#define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */
#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */
#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */
#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */
#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */
#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */
#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */
#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */
#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */
#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */
#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
#ifdef CONFIG_SA1100_ASSABET
extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
#else
#define ASSABET_BCR_frob(x,y) do { } while (0)
#endif
#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x))
#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0)
#define ASSABET_BSR_BASE 0xf1000000
#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
#define ASSABET_BSR_RS232_VALID (1 << 24)
#define ASSABET_BSR_COM_DCD (1 << 25)
#define ASSABET_BSR_COM_CTS (1 << 26)
#define ASSABET_BSR_COM_DSR (1 << 27)
#define ASSABET_BSR_RAD_CTS (1 << 28)
#define ASSABET_BSR_RAD_DSR (1 << 29)
#define ASSABET_BSR_RAD_DCD (1 << 30)
#define ASSABET_BSR_RAD_RI (1 << 31)
/* GPIOs (bitmasks) for which the generic definition doesn't say much */
#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
/* These are gpiolib GPIO numbers, not bitmasks */
#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */
#define ASSABET_GPIO_CF_CD 22 /* CF CD */
#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */
#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
#endif

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/*
* arch/arm/mach-sa1100/include/mach/badge4.h
*
* Tim Connors <connors@hpl.hp.com>
* Christopher Hoover <ch@hpl.hp.com>
*
* Copyright (C) 2002 Hewlett-Packard Company
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#error "include <mach/hardware.h> instead"
#endif
#define BADGE4_SA1111_BASE (0x48000000)
/* GPIOs on the BadgePAD 4 */
#define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */
#define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */
#define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */
#define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */
#define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */
#define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */
#define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */
#define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */
#define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */
#define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */
#define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */
#define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */
#define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */
#define BADGE4_GPIO_UART_HS1 GPIO_GPIO13
#define BADGE4_GPIO_UART_HS2 GPIO_GPIO14
#define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15
#define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16
#define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */
#define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */
#define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */
#define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */
#define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */
#define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */
#define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23
#define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */
#define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */
#define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26
#define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */
/* Interrupts on the BadgePAD 4 */
#define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */
/* PCM5ENV Usage tracking */
#define BADGE4_5V_PCMCIA_SOCK0 (1<<0)
#define BADGE4_5V_PCMCIA_SOCK1 (1<<1)
#define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n))
#define BADGE4_5V_USB (1<<2)
#define BADGE4_5V_INITIALLY (1<<3)
#ifndef __ASSEMBLY__
extern void badge4_set_5V(unsigned subsystem, int on);
#endif

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/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

23
arch/arm/mach-sa1100/include/mach/cerf.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/cerf.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Apr-2003 : Removed some old PDA crud [FB]
*/
#ifndef _INCLUDE_CERF_H_
#define _INCLUDE_CERF_H_
#define CERF_ETH_IO 0xf0000000
#define CERF_ETH_IRQ IRQ_GPIO26
#define CERF_GPIO_CF_BVD2 19
#define CERF_GPIO_CF_BVD1 20
#define CERF_GPIO_CF_RESET 21
#define CERF_GPIO_CF_IRQ 22
#define CERF_GPIO_CF_CD 23
#endif // _INCLUDE_CERF_H_

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/*
* arch/arm/mach-sa1100/include/mach/collie.h
*
* This file contains the hardware specific definitions for Collie
* Only include this file from SA1100-specific files.
*
* ChangeLog:
* 04-06-2001 Lineo Japan, Inc.
* 04-16-2001 SHARP Corporation
* 07-07-2002 Chris Larson <clarson@digi.com>
*
*/
#ifndef __ASM_ARCH_COLLIE_H
#define __ASM_ARCH_COLLIE_H
extern void locomolcd_power(int on);
#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12
#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13
#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14
#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15
#define COLLIE_SCP_5VON SCOOP_GPCR_PA16
#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17
#define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7)
#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19
#define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
COLLIE_SCP_LB_VOL_CHG)
#define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R)
/* GPIOs for gpiolib */
#define COLLIE_GPIO_ON_KEY (0)
#define COLLIE_GPIO_AC_IN (1)
#define COLLIE_GPIO_SDIO_INT (11)
#define COLLIE_GPIO_CF_IRQ (14)
#define COLLIE_GPIO_nREMOCON_INT (15)
#define COLLIE_GPIO_UCB1x00_RESET (16)
#define COLLIE_GPIO_nMIC_ON (17)
#define COLLIE_GPIO_nREMOCON_ON (18)
#define COLLIE_GPIO_CO (20)
#define COLLIE_GPIO_MCP_CLK (21)
#define COLLIE_GPIO_CF_CD (22)
#define COLLIE_GPIO_UCB1x00_IRQ (23)
#define COLLIE_GPIO_WAKEUP (24)
#define COLLIE_GPIO_GA_INT (25)
#define COLLIE_GPIO_MAIN_BAT_LOW (26)
/* GPIO definitions for direct register access */
#define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0)
#define _COLLIE_GPIO_AC_IN GPIO_GPIO(1)
#define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15)
#define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16)
#define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17)
#define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18)
#define _COLLIE_GPIO_CO GPIO_GPIO(20)
#define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24)
/* Interrupts */
#define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0
#define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1
#define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11
#define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14
#define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15
#define COLLIE_IRQ_GPIO_CO IRQ_GPIO20
#define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22
#define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23
#define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24
#define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25
#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26
/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
#define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13)
#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0
#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1
#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2
#define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3
#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4
#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5
#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5
#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6
#define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7)
#define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8)
#define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9)
#define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5)
#define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \
| UCB_IO_6)
#endif

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arch/arm/mach-sa1100/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-sa1100/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/hardware.h>
.macro addruart, rp, rv, tmp
mrc p15, 0, \rp, c1, c0
tst \rp, #1 @ MMU enabled?
moveq \rp, #0x80000000 @ physical base address
movne \rp, #0xf8000000 @ virtual address
@ We probe for the active serial port here, coherently with
@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
@ We assume r1 can be clobbered.
@ see if Ser3 is active
add \rp, \rp, #0x00050000
ldr \rv, [\rp, #UTCR3]
tst \rv, #UTCR3_TXE
@ if Ser3 is inactive, then try Ser1
addeq \rp, \rp, #(0x00010000 - 0x00050000)
ldreq \rv, [\rp, #UTCR3]
tsteq \rv, #UTCR3_TXE
@ if Ser1 is inactive, then try Ser2
addeq \rp, \rp, #(0x00030000 - 0x00010000)
ldreq \rv, [\rp, #UTCR3]
tsteq \rv, #UTCR3_TXE
@ clear top bits, and generate both phys and virt addresses
lsl \rp, \rp, #8
lsr \rp, \rp, #8
orr \rv, \rp, #0xf8000000 @ virtual
orr \rp, \rp, #0x80000000 @ physical
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UTDR]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TNF
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TBY
bne 1001b
.endm

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arch/arm/mach-sa1100/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-sa1100/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for SA1100-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro get_irqnr_preamble, base, tmp
mov \base, #0xfa000000 @ ICIP = 0xfa050000
add \base, \base, #0x00050000
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base] @ get irqs
ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0
beq 1001f
tst \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tst \irqstat, #0x0f
moveq \irqstat, \irqstat, lsr #4
addeq \irqnr, \irqnr, #4
tst \irqstat, #0x03
moveq \irqstat, \irqstat, lsr #2
addeq \irqnr, \irqnr, #2
tst \irqstat, #0x01
addeqs \irqnr, \irqnr, #1
1001:
.endm

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#include "../../generic.h"

55
arch/arm/mach-sa1100/include/mach/gpio.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/gpio.h
*
* SA1100 GPIO wrappers for arch-neutral GPIO calls
*
* Written by Philipp Zabel <philipp.zabel@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_SA1100_GPIO_H
#define __ASM_ARCH_SA1100_GPIO_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm-generic/gpio.h>
#define __ARM_GPIOLIB_COMPLEX
static inline int gpio_get_value(unsigned gpio)
{
if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
return GPLR & GPIO_GPIO(gpio);
else
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
if (value)
GPSR = GPIO_GPIO(gpio);
else
GPCR = GPIO_GPIO(gpio);
else
__gpio_set_value(gpio, value);
}
#define gpio_cansleep __gpio_cansleep
#endif

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arch/arm/mach-sa1100/include/mach/h3xxx.h Normal file
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/*
* Definitions for Compaq iPAQ H3100 and H3600 handheld computers
*
* (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks)
* (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _INCLUDE_H3XXX_H_
#define _INCLUDE_H3XXX_H_
/* Physical memory regions corresponding to chip selects */
#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
#define H3600_BANK_2_PHYS SA1100_CS2_PHYS
#define H3600_BANK_4_PHYS SA1100_CS4_PHYS
/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
#define H3600_EGPIO_VIRT 0xf0000000
#define H3600_BANK_2_VIRT 0xf1000000
#define H3600_BANK_4_VIRT 0xf3800000
/*
* gpiolib numbers for all iPAQs
*/
#define H3XXX_GPIO_PWR_BUTTON 0
#define H3XXX_GPIO_PCMCIA_CD1 10
#define H3XXX_GPIO_PCMCIA_IRQ1 11
#define H3XXX_GPIO_PCMCIA_CD0 17
#define H3XXX_GPIO_ACTION_BUTTON 18
#define H3XXX_GPIO_SYS_CLK 19
#define H3XXX_GPIO_PCMCIA_IRQ0 21
#define H3XXX_GPIO_COM_DCD 23
#define H3XXX_GPIO_OPTION 24
#define H3XXX_GPIO_COM_CTS 25
#define H3XXX_GPIO_COM_RTS 26
/* machine-specific gpios */
#define H3100_GPIO_BT_ON 2
#define H3100_GPIO_QMUTE 4
#define H3100_GPIO_LCD_3V_ON 5
#define H3100_GPIO_AUD_ON 6
#define H3100_GPIO_AUD_PWR_ON 7
#define H3100_GPIO_IR_ON 8
#define H3100_GPIO_IR_FSEL 9
#define H3600_GPIO_CLK_SET0 12 /* audio sample rate clock generator */
#define H3600_GPIO_CLK_SET1 13
#define H3600_GPIO_SOFT_RESET 20 /* also known as BATT_FAULT */
#define H3600_GPIO_OPT_LOCK 22
#define H3600_GPIO_OPT_DET 27
/* H3100 / 3600 EGPIO pins */
#define H3XXX_EGPIO_BASE (GPIO_MAX + 1)
#define H3XXX_EGPIO_VPP_ON (H3XXX_EGPIO_BASE + 0)
#define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */
#define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */
#define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */
#define H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */
#define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */
#define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */
#define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */
/* H3600 only EGPIO pins */
#define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */
#define H3600_EGPIO_IR_ON (H3XXX_EGPIO_BASE + 9) /* apply power to IR module. active high. */
#define H3600_EGPIO_AUD_AMP_ON (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp. active high. */
#define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */
#define H3600_EGPIO_QMUTE (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341. active high. */
#define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */
#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
struct gpio_default_state {
int gpio;
int mode;
const char *name;
};
#define GPIO_MODE_IN -1
#define GPIO_MODE_OUT0 0
#define GPIO_MODE_OUT1 1
void h3xxx_init_gpio(struct gpio_default_state *s, size_t n);
void __init h3xxx_map_io(void);
void __init h3xxx_mach_init(void);
#endif /* _INCLUDE_H3XXX_H_ */

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arch/arm/mach-sa1100/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/hardware.h
*
* Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net>
*
* This file contains the hardware definitions for SA1100 architecture
*
* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
* Definitions for SA1111 added.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#define UNCACHEABLE_ADDR 0xfa050000
/*
* SA1100 internal I/O mappings
*
* We have the following mapping:
* phys virt
* 80000000 f8000000
* 90000000 fa000000
* a0000000 fc000000
* b0000000 fe000000
*/
#define VIO_BASE 0xf8000000 /* virtual start of IO space */
#define VIO_SHIFT 3 /* x = IO space shrink power */
#define PIO_START 0x80000000 /* physical start of IO space */
#define io_p2v( x ) \
IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
#define io_v2p( x ) \
( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
#define CPU_SA1110_A0 (0)
#define CPU_SA1110_B0 (4)
#define CPU_SA1110_B1 (5)
#define CPU_SA1110_B2 (6)
#define CPU_SA1110_B4 (8)
#define CPU_SA1100_ID (0x4401a110)
#define CPU_SA1100_MASK (0xfffffff0)
#define CPU_SA1110_ID (0x6901b110)
#define CPU_SA1110_MASK (0xfffffff0)
#define __MREG(x) IOMEM(io_p2v(x))
#ifndef __ASSEMBLY__
#include <asm/cputype.h>
#define CPU_REVISION (read_cpuid_id() & 15)
#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
# define __PREG(x) (io_v2p((unsigned long)&(x)))
static inline unsigned long get_clock_tick_rate(void)
{
return 3686400;
}
#else
# define __REG(x) io_p2v(x)
# define __PREG(x) io_v2p(x)
#endif
#include "SA-1100.h"
#ifdef CONFIG_SA1101
#include "SA-1101.h"
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

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/*
* arch/arm/mach-sa1100/include/mach/irqs.h
*
* Copyright (C) 1996 Russell King
* Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
* Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
*
* 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
*/
#define IRQ_GPIO0 0
#define IRQ_GPIO1 1
#define IRQ_GPIO2 2
#define IRQ_GPIO3 3
#define IRQ_GPIO4 4
#define IRQ_GPIO5 5
#define IRQ_GPIO6 6
#define IRQ_GPIO7 7
#define IRQ_GPIO8 8
#define IRQ_GPIO9 9
#define IRQ_GPIO10 10
#define IRQ_GPIO11_27 11
#define IRQ_LCD 12 /* LCD controller */
#define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */
#define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */
#define IRQ_Ser1UART 15 /* Ser. port 1 UART */
#define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */
#define IRQ_Ser3UART 17 /* Ser. port 3 UART */
#define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */
#define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */
#define IRQ_DMA0 20 /* DMA controller channel 0 */
#define IRQ_DMA1 21 /* DMA controller channel 1 */
#define IRQ_DMA2 22 /* DMA controller channel 2 */
#define IRQ_DMA3 23 /* DMA controller channel 3 */
#define IRQ_DMA4 24 /* DMA controller channel 4 */
#define IRQ_DMA5 25 /* DMA controller channel 5 */
#define IRQ_OST0 26 /* OS Timer match 0 */
#define IRQ_OST1 27 /* OS Timer match 1 */
#define IRQ_OST2 28 /* OS Timer match 2 */
#define IRQ_OST3 29 /* OS Timer match 3 */
#define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */
#define IRQ_RTCAlrm 31 /* RTC Alarm */
#define IRQ_GPIO11 32
#define IRQ_GPIO12 33
#define IRQ_GPIO13 34
#define IRQ_GPIO14 35
#define IRQ_GPIO15 36
#define IRQ_GPIO16 37
#define IRQ_GPIO17 38
#define IRQ_GPIO18 39
#define IRQ_GPIO19 40
#define IRQ_GPIO20 41
#define IRQ_GPIO21 42
#define IRQ_GPIO22 43
#define IRQ_GPIO23 44
#define IRQ_GPIO24 45
#define IRQ_GPIO25 46
#define IRQ_GPIO26 47
#define IRQ_GPIO27 48
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase IRQ_BOARD_END, but keep it
* within sensible limits. IRQs 49 to 64 are available.
*/
#define IRQ_BOARD_START 49
#define IRQ_BOARD_END 65
/*
* Figure out the MAX IRQ number.
*
* Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
* allocate their IRQs above NR_IRQS.
*
* LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
* to be included in the NR_IRQS calculation.
*/
#ifdef CONFIG_SHARP_LOCOMO
#define NR_IRQS_LOCOMO 4
#else
#define NR_IRQS_LOCOMO 0
#endif
#ifndef NR_IRQS
#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
#endif
#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)

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arch/arm/mach-sa1100/include/mach/jornada720.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/jornada720.h
*
* SSP/MCU communication definitions for HP Jornada 710/720/728
*
* Copyright 2007,2008 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
* Copyright 2000 John Ankcorn <jca@lcs.mit.edu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/* HP Jornada 7xx microprocessor commands */
#define GETBATTERYDATA 0xc0
#define GETSCANKEYCODE 0x90
#define GETTOUCHSAMPLES 0xa0
#define GETCONTRAST 0xD0
#define SETCONTRAST 0xD1
#define GETBRIGHTNESS 0xD2
#define SETBRIGHTNESS 0xD3
#define CONTRASTOFF 0xD8
#define BRIGHTNESSOFF 0xD9
#define PWMOFF 0xDF
#define TXDUMMY 0x11
#define ERRORCODE 0x00
extern void jornada_ssp_start(void);
extern void jornada_ssp_end(void);
extern int jornada_ssp_inout(u8 byte);
extern int jornada_ssp_byte(u8 byte);

41
arch/arm/mach-sa1100/include/mach/memory.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/memory.h
*
* Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net>
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <asm/sizes.h>
/*
* Physical DRAM offset is 0xc0000000 on the SA1100
*/
#define PLAT_PHYS_OFFSET UL(0xc0000000)
/*
* Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much convenient to use Linux's SparseMEM support to implement
* our memory map representation. Assuming all memory nodes have equal access
* characteristics, we then have generic discontiguous memory support.
*
* The sparsemem banks are matched with the physical memory bank addresses
* which are incidentally the same as virtual addresses.
*
* node 0: 0xc0000000 - 0xc7ffffff
* node 1: 0xc8000000 - 0xcfffffff
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
#define MAX_PHYSMEM_BITS 32
#define SECTION_SIZE_BITS 27
/*
* Cache flushing area - SA1100 zero bank
*/
#define FLUSH_BASE_PHYS 0xe0000000
#define FLUSH_BASE 0xf5000000
#define FLUSH_BASE_MINICACHE 0xf5100000
#endif

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arch/arm/mach-sa1100/include/mach/mtd-xip.h Normal file
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/*
* MTD primitives for XIP support. Architecture specific functions
*
* Do not include this file directly. It's included from linux/mtd/xip.h
*
* Author: Nicolas Pitre
* Created: Nov 2, 2004
* Copyright: (C) 2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_SA1100_MTD_XIP_H__
#define __ARCH_SA1100_MTD_XIP_H__
#include <mach/hardware.h>
#define xip_irqpending() (ICIP & ICMR)
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
#define xip_currtime() (OSCR)
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
#endif /* __ARCH_SA1100_MTD_XIP_H__ */

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arch/arm/mach-sa1100/include/mach/nanoengine.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/nanoengine.h
*
* This file contains the hardware specific definitions for nanoEngine.
* Only include this file from SA1100-specific files.
*
* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_NANOENGINE_H
#define __ASM_ARCH_NANOENGINE_H
#include <mach/irqs.h>
#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/
#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */
#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */
#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */
#define GPIO_PC_RESET0 15 /* reset socket 0 */
#define GPIO_PC_RESET1 16 /* reset socket 1 */
#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12
#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13
#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14
/*
* nanoEngine Memory Map:
*
* 0000.0000 - 003F.0000 - 4 MB Flash
* C000.0000 - C1FF.FFFF - 32 MB SDRAM
* 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
* 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space
* 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
* 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
*
*/
#define NANO_PCI_MEM_RW_PHYS 0x18600000
#define NANO_PCI_MEM_RW_VIRT 0xf1000000
#define NANO_PCI_MEM_RW_SIZE SZ_1M
#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000
#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000
#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K
#endif

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arch/arm/mach-sa1100/include/mach/neponset.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/neponset.h
*
* Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
*
* This file contains the hardware specific definitions for Assabet
* Only include this file from SA1100-specific files.
*
* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
* Definitions for Neponset added.
*/
#ifndef __ASM_ARCH_NEPONSET_H
#define __ASM_ARCH_NEPONSET_H
/*
* Neponset definitions:
*/
#define NCR_GP01_OFF (1<<0)
#define NCR_TP_PWR_EN (1<<1)
#define NCR_MS_PWR_EN (1<<2)
#define NCR_ENET_OSC_EN (1<<3)
#define NCR_SPI_KB_WK_UP (1<<4)
#define NCR_A0VPP (1<<5)
#define NCR_A1VPP (1<<6)
void neponset_ncr_frob(unsigned int, unsigned int);
#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
#endif

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arch/arm/mach-sa1100/include/mach/reset.h Normal file
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#ifndef __ASM_ARCH_RESET_H
#define __ASM_ARCH_RESET_H
#include "hardware.h"
#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
#define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */
#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
#define RESET_STATUS_ALL (0xf)
extern unsigned int reset_status;
static inline void clear_reset_status(unsigned int mask)
{
RCSR = mask;
}
#endif /* __ASM_ARCH_RESET_H */

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arch/arm/mach-sa1100/include/mach/shannon.h Normal file
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#ifndef _INCLUDE_SHANNON_H
#define _INCLUDE_SHANNON_H
/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT,
* written by <forsyth@vitanuova.com> */
#define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */
#define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */
/* lcd lower = GPIO 2-9 */
#define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */
#define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */
#define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */
#define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */
#define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */
#define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14
#define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */
#define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */
#define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16
#define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */
#define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */
#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
#define SHANNON_GPIO_DISP_EN 22 /* out */
/* XXX GPIO 23 unaccounted for */
#define SHANNON_GPIO_EJECT_0 24 /* in */
#define SHANNON_GPIO_EJECT_1 25 /* in */
#define SHANNON_GPIO_RDY_0 26 /* in */
#define SHANNON_GPIO_RDY_1 27 /* in */
/* MCP UCB codec GPIO pins... */
#define SHANNON_UCB_GPIO_BACKLIGHT 9
#define SHANNON_UCB_GPIO_BRIGHT_MASK 7
#define SHANNON_UCB_GPIO_BRIGHT 6
#define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f
#define SHANNON_UCB_GPIO_CONTRAST 0
#endif

158
arch/arm/mach-sa1100/include/mach/simpad.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/simpad.h
*
* based of assabet.h same as HUW_Webpanel
*
* This file contains the hardware specific definitions for SIMpad
*
* 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch>
*/
#ifndef __ASM_ARCH_SIMPAD_H
#define __ASM_ARCH_SIMPAD_H
#define GPIO_UART1_RTS GPIO_GPIO14
#define GPIO_UART1_DTR GPIO_GPIO7
#define GPIO_UART1_CTS GPIO_GPIO8
#define GPIO_UART1_DCD GPIO_GPIO23
#define GPIO_UART1_DSR GPIO_GPIO6
#define GPIO_UART3_RTS GPIO_GPIO12
#define GPIO_UART3_DTR GPIO_GPIO16
#define GPIO_UART3_CTS GPIO_GPIO13
#define GPIO_UART3_DCD GPIO_GPIO18
#define GPIO_UART3_DSR GPIO_GPIO17
#define GPIO_POWER_BUTTON GPIO_GPIO0
#define GPIO_UCB1300_IRQ GPIO_GPIO22 /* UCB GPIO and touchscreen */
#define IRQ_UART1_CTS IRQ_GPIO15
#define IRQ_UART1_DCD GPIO_GPIO23
#define IRQ_UART1_DSR GPIO_GPIO6
#define IRQ_UART3_CTS GPIO_GPIO13
#define IRQ_UART3_DCD GPIO_GPIO18
#define IRQ_UART3_DSR GPIO_GPIO17
#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0
/*--- PCMCIA ---*/
#define GPIO_CF_CD 24
#define GPIO_CF_IRQ 1
/*--- SmartCard ---*/
#define GPIO_SMART_CARD GPIO_GPIO10
#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10
/*--- ucb1x00 GPIO ---*/
#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1)
#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE)
#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1)
#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2)
#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3)
#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4)
#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5)
#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6)
#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7)
#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8)
#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9)
/*--- CS3 Latch ---*/
#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11)
#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE)
#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1)
#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2)
#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3)
#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4)
#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5)
#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6)
#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7)
#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8)
#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9)
#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10)
#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11)
#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12)
#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13)
#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14)
#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15)
#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16)
#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17)
#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18)
#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19)
#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20)
#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21)
#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22)
#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23)
#define CS3_BASE IOMEM(0xf1000000)
long simpad_get_cs3_ro(void);
long simpad_get_cs3_shadow(void);
void simpad_set_cs3_bit(int value);
void simpad_clear_cs3_bit(int value);
#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */
#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */
#define EN1 0x0004 /* This is only for EPROM's */
#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */
#define DISPLAY_ON 0x0010
#define PCMCIA_BUFF_DIS 0x0020
#define MQ_RESET 0x0040
#define PCMCIA_RESET 0x0080
#define DECT_POWER_ON 0x0100
#define IRDA_SD 0x0200 /* Shutdown for powersave */
#define RS232_ON 0x0400
#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */
#define LED2_ON 0x1000
#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */
#define ENABLE_5V 0x4000 /* Enable 5V circuit */
#define RESET_SIMCARD 0x8000
#define PCMCIA_BVD1 0x01
#define PCMCIA_BVD2 0x02
#define PCMCIA_VS1 0x04
#define PCMCIA_VS2 0x08
#define LOCK_IND 0x10
#define CHARGING_STATE 0x20
#define PCMCIA_SHORT 0x40
/*--- Battery ---*/
struct simpad_battery {
unsigned char ac_status; /* line connected yes/no */
unsigned char status; /* battery loading yes/no */
unsigned char percentage; /* percentage loaded */
unsigned short life; /* life till empty */
};
/* These should match the apm_bios.h definitions */
#define SIMPAD_AC_STATUS_AC_OFFLINE 0x00
#define SIMPAD_AC_STATUS_AC_ONLINE 0x01
#define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */
#define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff
/* These bitfields are rarely "or'd" together */
#define SIMPAD_BATT_STATUS_HIGH 0x01
#define SIMPAD_BATT_STATUS_LOW 0x02
#define SIMPAD_BATT_STATUS_CRITICAL 0x04
#define SIMPAD_BATT_STATUS_CHARGING 0x08
#define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10
#define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */
#define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */
#define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */
#define SIMPAD_BATT_STATUS_NOBATT 0x80
#define SIMPAD_BATT_STATUS_UNKNOWN 0xff
extern int simpad_get_battery(struct simpad_battery* );
#endif // __ASM_ARCH_SIMPAD_H

12
arch/arm/mach-sa1100/include/mach/timex.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/timex.h
*
* SA1100 architecture timex specifications
*
* Copyright (C) 1998
*/
/*
* SA1100 timer
*/
#define CLOCK_TICK_RATE 3686400

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arch/arm/mach-sa1100/include/mach/uncompress.h Normal file
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/*
* arch/arm/mach-sa1100/include/mach/uncompress.h
*
* (C) 1999 Nicolas Pitre <nico@fluxnic.net>
*
* Reorganised to be machine independent.
*/
#include "hardware.h"
#define IOMEM(x) (x)
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. We search for the first enabled
* port in the most probable order. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*/
#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
static void putc(int c)
{
unsigned long serial_port;
do {
serial_port = _Ser3UTCR0;
if (UART(UTCR3) & UTCR3_TXE) break;
serial_port = _Ser1UTCR0;
if (UART(UTCR3) & UTCR3_TXE) break;
serial_port = _Ser2UTCR0;
if (UART(UTCR3) & UTCR3_TXE) break;
return;
} while (0);
/* wait for space in the UART's transmitter */
while (!(UART(UTSR1) & UTSR1_TNF))
barrier();
/* send the character out. */
UART(UTDR) = c;
}
static inline void flush(void)
{
}
/*
* Nothing to do for these
*/
#define arch_decomp_setup()

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arch/arm/mach-sa1100/irq.c Normal file
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/*
* linux/arch/arm/mach-sa1100/irq.c
*
* Copyright (C) 1999-2001 Nicolas Pitre
*
* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/syscore_ops.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>
#include "generic.h"
/*
* SA1100 GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* Use this instead of directly setting GRER/GFER.
*/
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int GPIO_IRQ_mask = (1 << 11) - 1;
/*
* To get the GPIO number from an IRQ number
*/
#define GPIO_11_27_IRQ(i) ((i) - 21)
#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
{
unsigned int mask;
if (d->irq <= 10)
mask = 1 << d->irq;
else
mask = GPIO11_27_MASK(d->irq);
if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & IRQ_TYPE_EDGE_RISING) {
GPIO_IRQ_rising_edge |= mask;
} else
GPIO_IRQ_rising_edge &= ~mask;
if (type & IRQ_TYPE_EDGE_FALLING) {
GPIO_IRQ_falling_edge |= mask;
} else
GPIO_IRQ_falling_edge &= ~mask;
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
return 0;
}
/*
* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
*/
static void sa1100_low_gpio_ack(struct irq_data *d)
{
GEDR = (1 << d->irq);
}
static void sa1100_low_gpio_mask(struct irq_data *d)
{
ICMR &= ~(1 << d->irq);
}
static void sa1100_low_gpio_unmask(struct irq_data *d)
{
ICMR |= 1 << d->irq;
}
static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
{
if (on)
PWER |= 1 << d->irq;
else
PWER &= ~(1 << d->irq);
return 0;
}
static struct irq_chip sa1100_low_gpio_chip = {
.name = "GPIO-l",
.irq_ack = sa1100_low_gpio_ack,
.irq_mask = sa1100_low_gpio_mask,
.irq_unmask = sa1100_low_gpio_unmask,
.irq_set_type = sa1100_gpio_type,
.irq_set_wake = sa1100_low_gpio_wake,
};
/*
* IRQ11 (GPIO11 through 27) handler. We enter here with the
* irq_controller_lock held, and IRQs disabled. Decode the IRQ
* and call the handler.
*/
static void
sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int mask;
mask = GEDR & 0xfffff800;
do {
/*
* clear down all currently active IRQ sources.
* We will be processing them all.
*/
GEDR = mask;
irq = IRQ_GPIO11;
mask >>= 11;
do {
if (mask & 1)
generic_handle_irq(irq);
mask >>= 1;
irq++;
} while (mask);
mask = GEDR & 0xfffff800;
} while (mask);
}
/*
* Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
* In addition, the IRQs are all collected up into one bit in the
* interrupt controller registers.
*/
static void sa1100_high_gpio_ack(struct irq_data *d)
{
unsigned int mask = GPIO11_27_MASK(d->irq);
GEDR = mask;
}
static void sa1100_high_gpio_mask(struct irq_data *d)
{
unsigned int mask = GPIO11_27_MASK(d->irq);
GPIO_IRQ_mask &= ~mask;
GRER &= ~mask;
GFER &= ~mask;
}
static void sa1100_high_gpio_unmask(struct irq_data *d)
{
unsigned int mask = GPIO11_27_MASK(d->irq);
GPIO_IRQ_mask |= mask;
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
}
static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
{
if (on)
PWER |= GPIO11_27_MASK(d->irq);
else
PWER &= ~GPIO11_27_MASK(d->irq);
return 0;
}
static struct irq_chip sa1100_high_gpio_chip = {
.name = "GPIO-h",
.irq_ack = sa1100_high_gpio_ack,
.irq_mask = sa1100_high_gpio_mask,
.irq_unmask = sa1100_high_gpio_unmask,
.irq_set_type = sa1100_gpio_type,
.irq_set_wake = sa1100_high_gpio_wake,
};
/*
* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
* this is for internal IRQs i.e. from 11 to 31.
*/
static void sa1100_mask_irq(struct irq_data *d)
{
ICMR &= ~(1 << d->irq);
}
static void sa1100_unmask_irq(struct irq_data *d)
{
ICMR |= (1 << d->irq);
}
/*
* Apart form GPIOs, only the RTC alarm can be a wakeup event.
*/
static int sa1100_set_wake(struct irq_data *d, unsigned int on)
{
if (d->irq == IRQ_RTCAlrm) {
if (on)
PWER |= PWER_RTC;
else
PWER &= ~PWER_RTC;
return 0;
}
return -EINVAL;
}
static struct irq_chip sa1100_normal_chip = {
.name = "SC",
.irq_ack = sa1100_mask_irq,
.irq_mask = sa1100_mask_irq,
.irq_unmask = sa1100_unmask_irq,
.irq_set_wake = sa1100_set_wake,
};
static struct resource irq_resource =
DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
static struct sa1100irq_state {
unsigned int saved;
unsigned int icmr;
unsigned int iclr;
unsigned int iccr;
} sa1100irq_state;
static int sa1100irq_suspend(void)
{
struct sa1100irq_state *st = &sa1100irq_state;
st->saved = 1;
st->icmr = ICMR;
st->iclr = ICLR;
st->iccr = ICCR;
/*
* Disable all GPIO-based interrupts.
*/
ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
IC_GPIO1|IC_GPIO0);
/*
* Set the appropriate edges for wakeup.
*/
GRER = PWER & GPIO_IRQ_rising_edge;
GFER = PWER & GPIO_IRQ_falling_edge;
/*
* Clear any pending GPIO interrupts.
*/
GEDR = GEDR;
return 0;
}
static void sa1100irq_resume(void)
{
struct sa1100irq_state *st = &sa1100irq_state;
if (st->saved) {
ICCR = st->iccr;
ICLR = st->iclr;
GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
ICMR = st->icmr;
}
}
static struct syscore_ops sa1100irq_syscore_ops = {
.suspend = sa1100irq_suspend,
.resume = sa1100irq_resume,
};
static int __init sa1100irq_init_devicefs(void)
{
register_syscore_ops(&sa1100irq_syscore_ops);
return 0;
}
device_initcall(sa1100irq_init_devicefs);
void __init sa1100_init_irq(void)
{
unsigned int irq;
request_resource(&iomem_resource, &irq_resource);
/* disable all IRQs */
ICMR = 0;
/* all IRQs are IRQ, not FIQ */
ICLR = 0;
/* clear all GPIO edge detects */
GFER = 0;
GRER = 0;
GEDR = -1;
/*
* Whatever the doc says, this has to be set for the wait-on-irq
* instruction to work... on a SA1100 rev 9 at least.
*/
ICCR = 1;
for (irq = 0; irq <= 10; irq++) {
irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = 12; irq <= 31; irq++) {
irq_set_chip_and_handler(irq, &sa1100_normal_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = 32; irq <= 48; irq++) {
irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/*
* Install handler for GPIO 11-27 edge detect interrupts
*/
irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
sa1100_init_gpio();
}

356
arch/arm/mach-sa1100/jornada720.c Normal file
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/*
* linux/arch/arm/mach-sa1100/jornada720.c
*
* HP Jornada720 init code
*
* Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
* Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
* Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <video/s1d13xxxfb.h>
#include <asm/hardware/sa1111.h>
#include <asm/page.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "generic.h"
/*
* HP Documentation referred in this file:
* http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
*/
/* line 110 of HP's doc */
#define TUCR_VAL 0x20000400
/* memory space (line 52 of HP's doc) */
#define SA1111REGSTART 0x40000000
#define SA1111REGLEN 0x00002000
#define EPSONREGSTART 0x48000000
#define EPSONREGLEN 0x00100000
#define EPSONFBSTART 0x48200000
/* 512kB framebuffer */
#define EPSONFBLEN 512*1024
static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
/* line 344 of HP's doc */
{0x0001,0x00}, // Miscellaneous Register
{0x01FC,0x00}, // Display Mode Register
{0x0004,0x00}, // General IO Pins Configuration Register 0
{0x0005,0x00}, // General IO Pins Configuration Register 1
{0x0008,0x00}, // General IO Pins Control Register 0
{0x0009,0x00}, // General IO Pins Control Register 1
{0x0010,0x01}, // Memory Clock Configuration Register
{0x0014,0x11}, // LCD Pixel Clock Configuration Register
{0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
{0x001C,0x01}, // MediaPlug Clock Configuration Register
{0x001E,0x01}, // CPU To Memory Wait State Select Register
{0x0020,0x00}, // Memory Configuration Register
{0x0021,0x45}, // DRAM Refresh Rate Register
{0x002A,0x01}, // DRAM Timings Control Register 0
{0x002B,0x03}, // DRAM Timings Control Register 1
{0x0030,0x1c}, // Panel Type Register
{0x0031,0x00}, // MOD Rate Register
{0x0032,0x4F}, // LCD Horizontal Display Width Register
{0x0034,0x07}, // LCD Horizontal Non-Display Period Register
{0x0035,0x01}, // TFT FPLINE Start Position Register
{0x0036,0x0B}, // TFT FPLINE Pulse Width Register
{0x0038,0xEF}, // LCD Vertical Display Height Register 0
{0x0039,0x00}, // LCD Vertical Display Height Register 1
{0x003A,0x13}, // LCD Vertical Non-Display Period Register
{0x003B,0x0B}, // TFT FPFRAME Start Position Register
{0x003C,0x01}, // TFT FPFRAME Pulse Width Register
{0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
{0x0041,0x00}, // LCD Miscellaneous Register
{0x0042,0x00}, // LCD Display Start Address Register 0
{0x0043,0x00}, // LCD Display Start Address Register 1
{0x0044,0x00}, // LCD Display Start Address Register 2
{0x0046,0x80}, // LCD Memory Address Offset Register 0
{0x0047,0x02}, // LCD Memory Address Offset Register 1
{0x0048,0x00}, // LCD Pixel Panning Register
{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
{0x0053,0x01}, // CRT/TV HRTC Start Position Register
{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
{0x0059,0x09}, // CRT/TV VRTC Start Position Register
{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
{0x005B,0x10}, // TV Output Control Register
{0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
{0x0062,0x00}, // CRT/TV Display Start Address Register 0
{0x0063,0x00}, // CRT/TV Display Start Address Register 1
{0x0064,0x00}, // CRT/TV Display Start Address Register 2
{0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
{0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
{0x0068,0x00}, // CRT/TV Pixel Panning Register
{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
{0x0070,0x00}, // LCD Ink/Cursor Control Register
{0x0071,0x01}, // LCD Ink/Cursor Start Address Register
{0x0072,0x00}, // LCD Cursor X Position Register 0
{0x0073,0x00}, // LCD Cursor X Position Register 1
{0x0074,0x00}, // LCD Cursor Y Position Register 0
{0x0075,0x00}, // LCD Cursor Y Position Register 1
{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
{0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
{0x0082,0x00}, // CRT/TV Cursor X Position Register 0
{0x0083,0x00}, // CRT/TV Cursor X Position Register 1
{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
{0x0100,0x00}, // BitBlt Control Register 0
{0x0101,0x00}, // BitBlt Control Register 1
{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
{0x0103,0x00}, // BitBlt Operation Register
{0x0104,0x00}, // BitBlt Source Start Address Register 0
{0x0105,0x00}, // BitBlt Source Start Address Register 1
{0x0106,0x00}, // BitBlt Source Start Address Register 2
{0x0108,0x00}, // BitBlt Destination Start Address Register 0
{0x0109,0x00}, // BitBlt Destination Start Address Register 1
{0x010A,0x00}, // BitBlt Destination Start Address Register 2
{0x010C,0x00}, // BitBlt Memory Address Offset Register 0
{0x010D,0x00}, // BitBlt Memory Address Offset Register 1
{0x0110,0x00}, // BitBlt Width Register 0
{0x0111,0x00}, // BitBlt Width Register 1
{0x0112,0x00}, // BitBlt Height Register 0
{0x0113,0x00}, // BitBlt Height Register 1
{0x0114,0x00}, // BitBlt Background Color Register 0
{0x0115,0x00}, // BitBlt Background Color Register 1
{0x0118,0x00}, // BitBlt Foreground Color Register 0
{0x0119,0x00}, // BitBlt Foreground Color Register 1
{0x01E0,0x00}, // Look-Up Table Mode Register
{0x01E2,0x00}, // Look-Up Table Address Register
/* not sure, wouldn't like to mess with the driver */
{0x01E4,0x00}, // Look-Up Table Data Register
/* jornada doc says 0x00, but I trust the driver */
{0x01F0,0x10}, // Power Save Configuration Register
{0x01F1,0x00}, // Power Save Status Register
{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
{0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
};
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL
};
static struct resource s1d13xxxfb_resources[] = {
[0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
[1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
static struct resource sa1111_resources[] = {
[0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
[1] = DEFINE_RES_IRQ(IRQ_GPIO1),
};
static struct sa1111_platform_data sa1111_info = {
.disable_devs = SA1111_DEVID_PS2_MSE,
};
static u64 sa1111_dmamask = 0xffffffffUL;
static struct platform_device sa1111_device = {
.name = "sa1111",
.id = 0,
.dev = {
.dma_mask = &sa1111_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &sa1111_info,
},
.num_resources = ARRAY_SIZE(sa1111_resources),
.resource = sa1111_resources,
};
static struct platform_device jornada_ssp_device = {
.name = "jornada_ssp",
.id = -1,
};
static struct platform_device jornada_kbd_device = {
.name = "jornada720_kbd",
.id = -1,
};
static struct platform_device jornada_ts_device = {
.name = "jornada_ts",
.id = -1,
};
static struct platform_device *devices[] __initdata = {
&sa1111_device,
&jornada_ssp_device,
&s1d13xxxfb_device,
&jornada_kbd_device,
&jornada_ts_device,
};
static int __init jornada720_init(void)
{
int ret = -ENODEV;
if (machine_is_jornada720()) {
/* we want to use gpio20 as input to drive the clock of our uart 3 */
GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */
TUCR = TUCR_VAL;
GPSR = GPIO_GPIO20; /* start gpio20 pin */
udelay(1);
GPCR = GPIO_GPIO20; /* stop gpio20 */
udelay(1);
GPSR = GPIO_GPIO20; /* restart gpio20 */
udelay(20); /* give it some time to restart */
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
}
return ret;
}
arch_initcall(jornada720_init);
static struct map_desc jornada720_io_desc[] __initdata = {
{ /* Epson registers */
.virtual = 0xf0000000,
.pfn = __phys_to_pfn(EPSONREGSTART),
.length = EPSONREGLEN,
.type = MT_DEVICE
}, { /* Epson frame buffer */
.virtual = 0xf1000000,
.pfn = __phys_to_pfn(EPSONFBSTART),
.length = EPSONFBLEN,
.type = MT_DEVICE
}
};
static void __init jornada720_map_io(void)
{
sa1100_map_io();
iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static struct mtd_partition jornada720_partitions[] = {
{
.name = "JORNADA720 boot firmware",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
.name = "JORNADA720 kernel",
.size = 0x000c0000,
.offset = 0x00040000,
}, {
.name = "JORNADA720 params",
.size = 0x00040000,
.offset = 0x00100000,
}, {
.name = "JORNADA720 initrd",
.size = 0x00100000,
.offset = 0x00140000,
}, {
.name = "JORNADA720 root cramfs",
.size = 0x00300000,
.offset = 0x00240000,
}, {
.name = "JORNADA720 usr cramfs",
.size = 0x00800000,
.offset = 0x00540000,
}, {
.name = "JORNADA720 usr local",
.size = 0, /* will expand to the end of the flash */
.offset = 0x00d00000,
}
};
static void jornada720_set_vpp(int vpp)
{
if (vpp)
/* enabling flash write (line 470 of HP's doc) */
PPSR |= PPC_LDD7;
else
/* disabling flash write (line 470 of HP's doc) */
PPSR &= ~PPC_LDD7;
PPDR |= PPC_LDD7;
}
static struct flash_platform_data jornada720_flash_data = {
.map_name = "cfi_probe",
.set_vpp = jornada720_set_vpp,
.parts = jornada720_partitions,
.nr_parts = ARRAY_SIZE(jornada720_partitions),
};
static struct resource jornada720_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
static void __init jornada720_mach_init(void)
{
sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
}
MACHINE_START(JORNADA720, "HP Jornada 720")
/* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
.atag_offset = 0x100,
.map_io = jornada720_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = jornada720_mach_init,
.init_late = sa11x0_init_late,
#ifdef CONFIG_SA1111
.dma_zone_size = SZ_1M,
#endif
.restart = sa11x0_restart,
MACHINE_END

203
arch/arm/mach-sa1100/jornada720_ssp.c Normal file
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/**
* arch/arm/mac-sa1100/jornada720_ssp.c
*
* Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
* Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* SSP driver for the HP Jornada 710/720/728
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/jornada720.h>
#include <asm/hardware/ssp.h>
static DEFINE_SPINLOCK(jornada_ssp_lock);
static unsigned long jornada_ssp_flags;
/**
* jornada_ssp_reverse - reverses input byte
*
* we need to reverse all data we receive from the mcu due to its physical location
* returns : 01110111 -> 11101110
*/
u8 inline jornada_ssp_reverse(u8 byte)
{
return
((0x80 & byte) >> 7) |
((0x40 & byte) >> 5) |
((0x20 & byte) >> 3) |
((0x10 & byte) >> 1) |
((0x08 & byte) << 1) |
((0x04 & byte) << 3) |
((0x02 & byte) << 5) |
((0x01 & byte) << 7);
};
EXPORT_SYMBOL(jornada_ssp_reverse);
/**
* jornada_ssp_byte - waits for ready ssp bus and sends byte
*
* waits for fifo buffer to clear and then transmits, if it doesn't then we will
* timeout after <timeout> rounds. Needs mcu running before its called.
*
* returns : %mcu output on success
* : %-ETIMEDOUT on timeout
*/
int jornada_ssp_byte(u8 byte)
{
int timeout = 400000;
u16 ret;
while ((GPLR & GPIO_GPIO10)) {
if (!--timeout) {
printk(KERN_WARNING "SSP: timeout while waiting for transmit\n");
return -ETIMEDOUT;
}
cpu_relax();
}
ret = jornada_ssp_reverse(byte) << 8;
ssp_write_word(ret);
ssp_read_word(&ret);
return jornada_ssp_reverse(ret);
};
EXPORT_SYMBOL(jornada_ssp_byte);
/**
* jornada_ssp_inout - decide if input is command or trading byte
*
* returns : (jornada_ssp_byte(byte)) on success
* : %-ETIMEDOUT on timeout failure
*/
int jornada_ssp_inout(u8 byte)
{
int ret, i;
/* true means command byte */
if (byte != TXDUMMY) {
ret = jornada_ssp_byte(byte);
/* Proper return to commands is TxDummy */
if (ret != TXDUMMY) {
for (i = 0; i < 256; i++)/* flushing bus */
if (jornada_ssp_byte(TXDUMMY) == -1)
break;
return -ETIMEDOUT;
}
} else /* Exchange TxDummy for data */
ret = jornada_ssp_byte(TXDUMMY);
return ret;
};
EXPORT_SYMBOL(jornada_ssp_inout);
/**
* jornada_ssp_start - enable mcu
*
*/
void jornada_ssp_start(void)
{
spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
GPCR = GPIO_GPIO25;
udelay(50);
return;
};
EXPORT_SYMBOL(jornada_ssp_start);
/**
* jornada_ssp_end - disable mcu and turn off lock
*
*/
void jornada_ssp_end(void)
{
GPSR = GPIO_GPIO25;
spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
return;
};
EXPORT_SYMBOL(jornada_ssp_end);
static int jornada_ssp_probe(struct platform_device *dev)
{
int ret;
GPSR = GPIO_GPIO25;
ret = ssp_init();
/* worked fine, lets not bother with anything else */
if (!ret) {
printk(KERN_INFO "SSP: device initialized with irq\n");
return ret;
}
printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n");
/* init of Serial 4 port */
Ser4MCCR0 = 0;
Ser4SSCR0 = 0x0387;
Ser4SSCR1 = 0x18;
/* clear out any left over data */
ssp_flush();
/* enable MCU */
jornada_ssp_start();
/* see if return value makes sense */
ret = jornada_ssp_inout(GETBRIGHTNESS);
/* seems like it worked, just feed it with TxDummy to get rid of data */
if (ret == TXDUMMY)
jornada_ssp_inout(TXDUMMY);
jornada_ssp_end();
/* failed, lets just kill everything */
if (ret == -ETIMEDOUT) {
printk(KERN_WARNING "SSP: attempts failed, bailing\n");
ssp_exit();
return -ENODEV;
}
/* all fine */
printk(KERN_INFO "SSP: device initialized\n");
return 0;
};
static int jornada_ssp_remove(struct platform_device *dev)
{
/* Note that this doesn't actually remove the driver, since theres nothing to remove
* It just makes sure everything is turned off */
GPSR = GPIO_GPIO25;
ssp_exit();
return 0;
};
struct platform_driver jornadassp_driver = {
.probe = jornada_ssp_probe,
.remove = jornada_ssp_remove,
.driver = {
.name = "jornada_ssp",
},
};
static int __init jornada_ssp_init(void)
{
return platform_driver_register(&jornadassp_driver);
}
module_init(jornada_ssp_init);

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arch/arm/mach-sa1100/lart.c Normal file
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/*
* linux/arch/arm/mach-sa1100/lart.c
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/tty.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <video/sa1100fb.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/irqs.h>
#include "generic.h"
static struct mcp_plat_data lart_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
};
#ifdef LART_GREY_LCD
static struct sa1100fb_mach_info lart_grey_info = {
.pixclock = 150000, .bpp = 4,
.xres = 320, .yres = 240,
.hsync_len = 1, .vsync_len = 1,
.left_margin = 4, .upper_margin = 0,
.right_margin = 2, .lower_margin = 0,
.cmap_greyscale = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
.lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
};
#endif
#ifdef LART_COLOR_LCD
static struct sa1100fb_mach_info lart_color_info = {
.pixclock = 150000, .bpp = 16,
.xres = 320, .yres = 240,
.hsync_len = 2, .vsync_len = 3,
.left_margin = 69, .upper_margin = 14,
.right_margin = 8, .lower_margin = 4,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
};
#endif
#ifdef LART_VIDEO_OUT
static struct sa1100fb_mach_info lart_video_info = {
.pixclock = 39721, .bpp = 16,
.xres = 640, .yres = 480,
.hsync_len = 95, .vsync_len = 2,
.left_margin = 40, .upper_margin = 32,
.right_margin = 24, .lower_margin = 11,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
};
#endif
#ifdef LART_KIT01_LCD
static struct sa1100fb_mach_info lart_kit01_info = {
.pixclock = 63291, .bpp = 16,
.xres = 640, .yres = 480,
.hsync_len = 64, .vsync_len = 3,
.left_margin = 122, .upper_margin = 45,
.right_margin = 10, .lower_margin = 10,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
};
#endif
static void __init lart_init(void)
{
struct sa1100fb_mach_info *inf = NULL;
#ifdef LART_GREY_LCD
inf = &lart_grey_info;
#endif
#ifdef LART_COLOR_LCD
inf = &lart_color_info;
#endif
#ifdef LART_VIDEO_OUT
inf = &lart_video_info;
#endif
#ifdef LART_KIT01_LCD
inf = &lart_kit01_info;
#endif
if (inf)
sa11x0_register_lcd(inf);
sa11x0_ppc_configure_mcp();
sa11x0_register_mcp(&lart_mcp_data);
}
static struct map_desc lart_io_desc[] __initdata = {
{ /* main flash memory */
.virtual = 0xe8000000,
.pfn = __phys_to_pfn(0x00000000),
.length = 0x00400000,
.type = MT_DEVICE
}, { /* main flash, alternative location */
.virtual = 0xec000000,
.pfn = __phys_to_pfn(0x08000000),
.length = 0x00400000,
.type = MT_DEVICE
}
};
/* LEDs */
struct gpio_led lart_gpio_leds[] = {
{
.name = "lart:red",
.default_trigger = "cpu0",
.gpio = 23,
},
};
static struct gpio_led_platform_data lart_gpio_led_info = {
.leds = lart_gpio_leds,
.num_leds = ARRAY_SIZE(lart_gpio_leds),
};
static struct platform_device lart_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &lart_gpio_led_info,
}
};
static void __init lart_map_io(void)
{
sa1100_map_io();
iotable_init(lart_io_desc, ARRAY_SIZE(lart_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
platform_device_register(&lart_leds);
}
MACHINE_START(LART, "LART")
.atag_offset = 0x100,
.map_io = lart_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_machine = lart_init,
.init_late = sa11x0_init_late,
.init_time = sa1100_timer_init,
.restart = sa11x0_restart,
MACHINE_END

117
arch/arm/mach-sa1100/nanoengine.c Normal file
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/*
* linux/arch/arm/mach-sa1100/nanoengine.c
*
* Bright Star Engineering's nanoEngine board init code.
*
* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/root_dev.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/nanoengine.h>
#include <mach/irqs.h>
#include "generic.h"
/* Flash bank 0 */
static struct mtd_partition nanoengine_partitions[] = {
{
.name = "nanoEngine boot firmware and parameter table",
.size = 0x00010000, /* 32K */
.offset = 0,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "kernel/initrd reserved",
.size = 0x002f0000,
.offset = 0x00010000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "experimental filesystem allocation",
.size = 0x00100000,
.offset = 0x00300000,
.mask_flags = MTD_WRITEABLE,
}
};
static struct flash_platform_data nanoengine_flash_data = {
.map_name = "jedec_probe",
.parts = nanoengine_partitions,
.nr_parts = ARRAY_SIZE(nanoengine_partitions),
};
static struct resource nanoengine_flash_resources[] = {
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
};
static struct map_desc nanoengine_io_desc[] __initdata = {
{
/* System Registers */
.virtual = 0xf0000000,
.pfn = __phys_to_pfn(0x10000000),
.length = 0x00100000,
.type = MT_DEVICE
}, {
/* Internal PCI Memory Read/Write */
.virtual = NANO_PCI_MEM_RW_VIRT,
.pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
.length = NANO_PCI_MEM_RW_SIZE,
.type = MT_DEVICE
}, {
/* Internal PCI Config Space */
.virtual = NANO_PCI_CONFIG_SPACE_VIRT,
.pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
.length = NANO_PCI_CONFIG_SPACE_SIZE,
.type = MT_DEVICE
}
};
static void __init nanoengine_map_io(void)
{
sa1100_map_io();
iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 3);
Ser1SDCR0 |= SDCR0_UART;
/* disable IRDA -- UART2 is used as a normal serial port */
Ser2UTCR4 = 0;
Ser2HSCR0 = 0;
}
static void __init nanoengine_init(void)
{
sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
ARRAY_SIZE(nanoengine_flash_resources));
}
MACHINE_START(NANOENGINE, "BSE nanoEngine")
.atag_offset = 0x100,
.map_io = nanoengine_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = nanoengine_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

436
arch/arm/mach-sa1100/neponset.c Normal file
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/*
* linux/arch/arm/mach-sa1100/neponset.c
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/hardware/sa1111.h>
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <mach/assabet.h>
#include <mach/neponset.h>
#include <mach/irqs.h>
#define NEP_IRQ_SMC91X 0
#define NEP_IRQ_USAR 1
#define NEP_IRQ_SA1111 2
#define NEP_IRQ_NR 3
#define WHOAMI 0x00
#define LEDS 0x10
#define SWPK 0x20
#define IRR 0x24
#define KP_Y_IN 0x80
#define KP_X_OUT 0x90
#define NCR_0 0xa0
#define MDM_CTL_0 0xb0
#define MDM_CTL_1 0xb4
#define AUD_CTL 0xc0
#define IRR_ETHERNET (1 << 0)
#define IRR_USAR (1 << 1)
#define IRR_SA1111 (1 << 2)
#define MDM_CTL0_RTS1 (1 << 0)
#define MDM_CTL0_DTR1 (1 << 1)
#define MDM_CTL0_RTS2 (1 << 2)
#define MDM_CTL0_DTR2 (1 << 3)
#define MDM_CTL1_CTS1 (1 << 0)
#define MDM_CTL1_DSR1 (1 << 1)
#define MDM_CTL1_DCD1 (1 << 2)
#define MDM_CTL1_CTS2 (1 << 3)
#define MDM_CTL1_DSR2 (1 << 4)
#define MDM_CTL1_DCD2 (1 << 5)
#define AUD_SEL_1341 (1 << 0)
#define AUD_MUTE_1341 (1 << 1)
extern void sa1110_mb_disable(void);
struct neponset_drvdata {
void __iomem *base;
struct platform_device *sa1111;
struct platform_device *smc91x;
unsigned irq_base;
#ifdef CONFIG_PM_SLEEP
u32 ncr0;
u32 mdm_ctl_0;
#endif
};
static void __iomem *nep_base;
void neponset_ncr_frob(unsigned int mask, unsigned int val)
{
void __iomem *base = nep_base;
if (base) {
unsigned long flags;
unsigned v;
local_irq_save(flags);
v = readb_relaxed(base + NCR_0);
writeb_relaxed((v & ~mask) | val, base + NCR_0);
local_irq_restore(flags);
} else {
WARN(1, "nep_base unset\n");
}
}
EXPORT_SYMBOL(neponset_ncr_frob);
static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
{
void __iomem *base = nep_base;
u_int mdm_ctl0;
if (!base)
return;
mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
if (port->mapbase == _Ser1UTCR0) {
if (mctrl & TIOCM_RTS)
mdm_ctl0 &= ~MDM_CTL0_RTS2;
else
mdm_ctl0 |= MDM_CTL0_RTS2;
if (mctrl & TIOCM_DTR)
mdm_ctl0 &= ~MDM_CTL0_DTR2;
else
mdm_ctl0 |= MDM_CTL0_DTR2;
} else if (port->mapbase == _Ser3UTCR0) {
if (mctrl & TIOCM_RTS)
mdm_ctl0 &= ~MDM_CTL0_RTS1;
else
mdm_ctl0 |= MDM_CTL0_RTS1;
if (mctrl & TIOCM_DTR)
mdm_ctl0 &= ~MDM_CTL0_DTR1;
else
mdm_ctl0 |= MDM_CTL0_DTR1;
}
writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
}
static u_int neponset_get_mctrl(struct uart_port *port)
{
void __iomem *base = nep_base;
u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
u_int mdm_ctl1;
if (!base)
return ret;
mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
if (port->mapbase == _Ser1UTCR0) {
if (mdm_ctl1 & MDM_CTL1_DCD2)
ret &= ~TIOCM_CD;
if (mdm_ctl1 & MDM_CTL1_CTS2)
ret &= ~TIOCM_CTS;
if (mdm_ctl1 & MDM_CTL1_DSR2)
ret &= ~TIOCM_DSR;
} else if (port->mapbase == _Ser3UTCR0) {
if (mdm_ctl1 & MDM_CTL1_DCD1)
ret &= ~TIOCM_CD;
if (mdm_ctl1 & MDM_CTL1_CTS1)
ret &= ~TIOCM_CTS;
if (mdm_ctl1 & MDM_CTL1_DSR1)
ret &= ~TIOCM_DSR;
}
return ret;
}
static struct sa1100_port_fns neponset_port_fns = {
.set_mctrl = neponset_set_mctrl,
.get_mctrl = neponset_get_mctrl,
};
/*
* Install handler for Neponset IRQ. Note that we have to loop here
* since the ETHERNET and USAR IRQs are level based, and we need to
* ensure that the IRQ signal is deasserted before returning. This
* is rather unfortunate.
*/
static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
unsigned int irr;
while (1) {
/*
* Acknowledge the parent IRQ.
*/
desc->irq_data.chip->irq_ack(&desc->irq_data);
/*
* Read the interrupt reason register. Let's have all
* active IRQ bits high. Note: there is a typo in the
* Neponset user's guide for the SA1111 IRR level.
*/
irr = readb_relaxed(d->base + IRR);
irr ^= IRR_ETHERNET | IRR_USAR;
if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
break;
/*
* Since there is no individual mask, we have to
* mask the parent IRQ. This is safe, since we'll
* recheck the register for any pending IRQs.
*/
if (irr & (IRR_ETHERNET | IRR_USAR)) {
desc->irq_data.chip->irq_mask(&desc->irq_data);
/*
* Ack the interrupt now to prevent re-entering
* this neponset handler. Again, this is safe
* since we'll check the IRR register prior to
* leaving.
*/
desc->irq_data.chip->irq_ack(&desc->irq_data);
if (irr & IRR_ETHERNET)
generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
if (irr & IRR_USAR)
generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
if (irr & IRR_SA1111)
generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
}
}
/* Yes, we really do not have any kind of masking or unmasking */
static void nochip_noop(struct irq_data *irq)
{
}
static struct irq_chip nochip = {
.name = "neponset",
.irq_ack = nochip_noop,
.irq_mask = nochip_noop,
.irq_unmask = nochip_noop,
};
static struct sa1111_platform_data sa1111_info = {
.disable_devs = SA1111_DEVID_PS2_MSE,
};
static int neponset_probe(struct platform_device *dev)
{
struct neponset_drvdata *d;
struct resource *nep_res, *sa1111_res, *smc91x_res;
struct resource sa1111_resources[] = {
DEFINE_RES_MEM(0x40000000, SZ_8K),
{ .flags = IORESOURCE_IRQ },
};
struct platform_device_info sa1111_devinfo = {
.parent = &dev->dev,
.name = "sa1111",
.id = 0,
.res = sa1111_resources,
.num_res = ARRAY_SIZE(sa1111_resources),
.data = &sa1111_info,
.size_data = sizeof(sa1111_info),
.dma_mask = 0xffffffffUL,
};
struct resource smc91x_resources[] = {
DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
0x02000000, "smc91x-regs"),
DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
0x02000000, "smc91x-attrib"),
{ .flags = IORESOURCE_IRQ },
};
struct platform_device_info smc91x_devinfo = {
.parent = &dev->dev,
.name = "smc91x",
.id = 0,
.res = smc91x_resources,
.num_res = ARRAY_SIZE(smc91x_resources),
};
int ret, irq;
if (nep_base)
return -EBUSY;
irq = ret = platform_get_irq(dev, 0);
if (ret < 0)
goto err_alloc;
nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
if (!nep_res || !smc91x_res || !sa1111_res) {
ret = -ENXIO;
goto err_alloc;
}
d = kzalloc(sizeof(*d), GFP_KERNEL);
if (!d) {
ret = -ENOMEM;
goto err_alloc;
}
d->base = ioremap(nep_res->start, SZ_4K);
if (!d->base) {
ret = -ENOMEM;
goto err_ioremap;
}
if (readb_relaxed(d->base + WHOAMI) != 0x11) {
dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
readb_relaxed(d->base + WHOAMI));
ret = -ENODEV;
goto err_id;
}
ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
if (ret <= 0) {
dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
NEP_IRQ_NR, ret);
if (ret == 0)
ret = -ENOMEM;
goto err_irq_alloc;
}
d->irq_base = ret;
irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
handle_simple_irq);
set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
handle_simple_irq);
set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
irq_set_handler_data(irq, d);
irq_set_chained_handler(irq, neponset_irq_handler);
/*
* We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
* something on the Neponset activates this IRQ on sleep (eth?)
*/
#if 0
enable_irq_wake(irq);
#endif
dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
nep_base = d->base;
sa1100_register_uart_fns(&neponset_port_fns);
/* Ensure that the memory bus request/grant signals are setup */
sa1110_mb_disable();
/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
sa1111_resources[0].parent = sa1111_res;
sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
d->sa1111 = platform_device_register_full(&sa1111_devinfo);
smc91x_resources[0].parent = smc91x_res;
smc91x_resources[1].parent = smc91x_res;
smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
d->smc91x = platform_device_register_full(&smc91x_devinfo);
platform_set_drvdata(dev, d);
return 0;
err_irq_alloc:
err_id:
iounmap(d->base);
err_ioremap:
kfree(d);
err_alloc:
return ret;
}
static int neponset_remove(struct platform_device *dev)
{
struct neponset_drvdata *d = platform_get_drvdata(dev);
int irq = platform_get_irq(dev, 0);
if (!IS_ERR(d->sa1111))
platform_device_unregister(d->sa1111);
if (!IS_ERR(d->smc91x))
platform_device_unregister(d->smc91x);
irq_set_chained_handler(irq, NULL);
irq_free_descs(d->irq_base, NEP_IRQ_NR);
nep_base = NULL;
iounmap(d->base);
kfree(d);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int neponset_suspend(struct device *dev)
{
struct neponset_drvdata *d = dev_get_drvdata(dev);
d->ncr0 = readb_relaxed(d->base + NCR_0);
d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
return 0;
}
static int neponset_resume(struct device *dev)
{
struct neponset_drvdata *d = dev_get_drvdata(dev);
writeb_relaxed(d->ncr0, d->base + NCR_0);
writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
return 0;
}
static const struct dev_pm_ops neponset_pm_ops = {
.suspend_noirq = neponset_suspend,
.resume_noirq = neponset_resume,
.freeze_noirq = neponset_suspend,
.restore_noirq = neponset_resume,
};
#define PM_OPS &neponset_pm_ops
#else
#define PM_OPS NULL
#endif
static struct platform_driver neponset_device_driver = {
.probe = neponset_probe,
.remove = neponset_remove,
.driver = {
.name = "neponset",
.owner = THIS_MODULE,
.pm = PM_OPS,
},
};
static int __init neponset_init(void)
{
return platform_driver_register(&neponset_device_driver);
}
subsys_initcall(neponset_init);

282
arch/arm/mach-sa1100/pci-nanoengine.c Normal file
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/*
* linux/arch/arm/mach-sa1100/pci-nanoengine.c
*
* PCI functions for BSE nanoEngine PCI
*
* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <mach/nanoengine.h>
#include <mach/hardware.h>
static DEFINE_SPINLOCK(nano_lock);
static int nanoengine_get_pci_address(struct pci_bus *bus,
unsigned int devfn, int where, unsigned long *address)
{
int ret = PCIBIOS_DEVICE_NOT_FOUND;
unsigned int busnr = bus->number;
*address = NANO_PCI_CONFIG_SPACE_VIRT +
((bus->number << 16) | (devfn << 8) | (where & ~3));
ret = (busnr > 255 || devfn > 255 || where > 255) ?
PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
return ret;
}
static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
int ret;
unsigned long address;
unsigned long flags;
u32 v;
/* nanoEngine PCI bridge does not return -1 for a non-existing
* device. We must fake the answer. We know that the only valid
* device is device zero at bus 0, which is the network chip. */
if (bus->number != 0 || (devfn >> 3) != 0) {
v = -1;
nanoengine_get_pci_address(bus, devfn, where, &address);
goto exit_function;
}
spin_lock_irqsave(&nano_lock, flags);
ret = nanoengine_get_pci_address(bus, devfn, where, &address);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
v = __raw_readl(address);
spin_unlock_irqrestore(&nano_lock, flags);
v >>= ((where & 3) * 8);
v &= (unsigned long)(-1) >> ((4 - size) * 8);
exit_function:
*val = v;
return PCIBIOS_SUCCESSFUL;
}
static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
int ret;
unsigned long address;
unsigned long flags;
unsigned shift;
u32 v;
shift = (where & 3) * 8;
spin_lock_irqsave(&nano_lock, flags);
ret = nanoengine_get_pci_address(bus, devfn, where, &address);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
v = __raw_readl(address);
switch (size) {
case 1:
v &= ~(0xFF << shift);
v |= val << shift;
break;
case 2:
v &= ~(0xFFFF << shift);
v |= val << shift;
break;
case 4:
v = val;
break;
}
__raw_writel(v, address);
spin_unlock_irqrestore(&nano_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_nano_ops = {
.read = nanoengine_read_config,
.write = nanoengine_write_config,
};
static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
return NANOENGINE_IRQ_GPIO_PCI;
}
static struct resource pci_io_ports =
DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
static struct resource pci_non_prefetchable_memory = {
.name = "PCI non-prefetchable",
.start = NANO_PCI_MEM_RW_PHYS,
/* nanoEngine documentation says there is a 1 Megabyte window here,
* but PCI reports just 128 + 8 kbytes. */
.end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
/* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
.flags = IORESOURCE_MEM,
};
/*
* nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
* overlaps with previously defined memory.
*
* Here is what happens:
*
# dmesg
...
pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:00.0: PME# disabled
PCI: bus0: Fast back to back transfers enabled
pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
*
* On the other hand, if we do not request the prefetchable memory resource,
* linux will alloc it first and the two non-prefetchable memory areas that
* are our real interest will not be mapped. So we choose to map it to an
* unused area. It gets recognized as expansion ROM, but becomes disabled.
*
* Here is what happens then:
*
# dmesg
...
pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
pci 0000:00:00.0: PME# disabled
PCI: bus0: Fast back to back transfers enabled
pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
# lspci -vv -s 0000:00:00.0
00:00.0 Class 0200: Device 8086:1209 (rev 09)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 0
Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at 0400 [size=64]
Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
[virtual] Expansion ROM at 78000000 [disabled] [size=1M]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
Kernel driver in use: e100
Kernel modules: e100
*
*/
static struct resource pci_prefetchable_memory = {
.name = "PCI prefetchable",
.start = 0x78000000,
.end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
};
static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
{
if (request_resource(&ioport_resource, &pci_io_ports)) {
printk(KERN_ERR "PCI: unable to allocate io port region\n");
return -EBUSY;
}
if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
release_resource(&pci_io_ports);
printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
return -EBUSY;
}
if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
release_resource(&pci_io_ports);
release_resource(&pci_non_prefetchable_memory);
printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
return -EBUSY;
}
pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
pci_add_resource_offset(&sys->resources,
&pci_non_prefetchable_memory, sys->mem_offset);
pci_add_resource_offset(&sys->resources,
&pci_prefetchable_memory, sys->mem_offset);
return 1;
}
int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
pcibios_min_io = 0;
pcibios_min_mem = 0;
if (nr == 0) {
sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
sys->io_offset = 0x400;
ret = pci_nanoengine_setup_resources(sys);
/* Enable alternate memory bus master mode, see
* "Intel StrongARM SA1110 Developer's Manual",
* section 10.8, "Alternate Memory Bus Master Mode". */
GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
GAFR |= GPIO_MBGNT | GPIO_MBREQ;
TUCR |= TUCR_MBGPIO;
}
return ret;
}
static struct hw_pci nanoengine_pci __initdata = {
.map_irq = pci_nanoengine_map_irq,
.nr_controllers = 1,
.ops = &pci_nano_ops,
.setup = pci_nanoengine_setup,
};
static int __init nanoengine_pci_init(void)
{
if (machine_is_nanoengine())
pci_common_init(&nanoengine_pci);
return 0;
}
subsys_initcall(nanoengine_pci_init);

140
arch/arm/mach-sa1100/pleb.c Normal file
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/*
* linux/arch/arm/mach-sa1100/pleb.c
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/mtd/partitions.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/irqs.h>
#include "generic.h"
/*
* Ethernet IRQ mappings
*/
#define PLEB_ETH0_P (0x20000300) /* Ethernet 0 in PCMCIA0 IO */
#define PLEB_ETH0_V (0xf6000300)
#define GPIO_ETH0_IRQ GPIO_GPIO(21)
#define GPIO_ETH0_EN GPIO_GPIO(26)
#define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21
static struct resource smc91x_resources[] = {
[0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000),
#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
[1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ),
#endif
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&smc91x_device,
};
/*
* Pleb's memory map
* has flash memory (typically 4 or 8 meg) selected by
* the two SA1100 lowest chip select outputs.
*/
static struct resource pleb_flash_resources[] = {
[0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M),
[1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M),
};
static struct mtd_partition pleb_partitions[] = {
{
.name = "blob",
.offset = 0,
.size = 0x00020000,
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0x000e0000,
}, {
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = 0x00300000,
}
};
static struct flash_platform_data pleb_flash_data = {
.map_name = "cfi_probe",
.parts = pleb_partitions,
.nr_parts = ARRAY_SIZE(pleb_partitions),
};
static void __init pleb_init(void)
{
sa11x0_register_mtd(&pleb_flash_data, pleb_flash_resources,
ARRAY_SIZE(pleb_flash_resources));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init pleb_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Fix expansion memory timing for network card
*/
MECR = ((2<<10) | (2<<5) | (2<<0));
/*
* Enable the SMC ethernet controller
*/
GPDR |= GPIO_ETH0_EN; /* set to output */
GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */
GPDR &= ~GPIO_ETH0_IRQ;
irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
}
MACHINE_START(PLEB, "PLEB")
.map_io = pleb_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = pleb_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

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arch/arm/mach-sa1100/pm.c Normal file
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/*
* SA1100 Power Management Routines
*
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*
* History:
*
* 2001-02-06: Cliff Brake Initial code
*
* 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
* Chester Kuo <chester@linux.org.tw>
* Save more value for the resume function! Support
* Bitsy/Assabet/Freebird board
*
* 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
* Cleaned up, pushed platform dependent stuff
* in the platform specific files.
*
* 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
* Storage is local on the stack now.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <mach/hardware.h>
#include <asm/memory.h>
#include <asm/suspend.h>
#include <asm/mach/time.h>
extern int sa1100_finish_suspend(unsigned long);
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
/*
* List of global SA11x0 peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
* on the stack and then the stack pointer is stored last in sleep.S.
*/
enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
SLEEP_SAVE_Ser1SDCR0,
SLEEP_SAVE_COUNT
};
static int sa11x0_pm_enter(suspend_state_t state)
{
unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
gpio = GPLR;
/* save vital registers */
SAVE(GPDR);
SAVE(GAFR);
SAVE(PPDR);
SAVE(PPSR);
SAVE(PPAR);
SAVE(PSDR);
SAVE(Ser1SDCR0);
/* Clear previous reset status */
RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
/* set resume return address */
PSPR = virt_to_phys(cpu_resume);
/* go zzz */
cpu_suspend(0, sa1100_finish_suspend);
/*
* Ensure not to come back here if it wasn't intended
*/
PSPR = 0;
/*
* Ensure interrupt sources are disabled; we will re-init
* the interrupt subsystem via the device manager.
*/
ICLR = 0;
ICCR = 1;
ICMR = 0;
/* restore registers */
RESTORE(GPDR);
RESTORE(GAFR);
RESTORE(PPDR);
RESTORE(PPSR);
RESTORE(PPAR);
RESTORE(PSDR);
RESTORE(Ser1SDCR0);
GPSR = gpio;
GPCR = ~gpio;
/*
* Clear the peripheral sleep-hold bit.
*/
PSSR = PSSR_PH;
return 0;
}
static const struct platform_suspend_ops sa11x0_pm_ops = {
.enter = sa11x0_pm_enter,
.valid = suspend_valid_only_mem,
};
int __init sa11x0_pm_init(void)
{
suspend_set_ops(&sa11x0_pm_ops);
return 0;
}

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arch/arm/mach-sa1100/shannon.c Normal file
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/*
* linux/arch/arm/mach-sa1100/shannon.c
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/tty.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <video/sa1100fb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/shannon.h>
#include <mach/irqs.h>
#include "generic.h"
static struct mtd_partition shannon_partitions[] = {
{
.name = "BLOB boot loader",
.offset = 0,
.size = 0x20000
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0xe0000
},
{
.name = "initrd",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL
}
};
static struct flash_platform_data shannon_flash_data = {
.map_name = "cfi_probe",
.parts = shannon_partitions,
.nr_parts = ARRAY_SIZE(shannon_partitions),
};
static struct resource shannon_flash_resource =
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M);
static struct mcp_plat_data shannon_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
};
static struct sa1100fb_mach_info shannon_lcd_info = {
.pixclock = 152500, .bpp = 8,
.xres = 640, .yres = 480,
.hsync_len = 4, .vsync_len = 3,
.left_margin = 2, .upper_margin = 0,
.right_margin = 1, .lower_margin = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
.lccr3 = LCCR3_ACBsDiv(512),
};
static void __init shannon_init(void)
{
sa11x0_ppc_configure_mcp();
sa11x0_register_lcd(&shannon_lcd_info);
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
sa11x0_register_mcp(&shannon_mcp_data);
}
static void __init shannon_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
Ser1SDCR0 |= SDCR0_SUS;
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD | SHANNON_GPIO_CODEC_RESET;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/* reset the codec */
GPCR = SHANNON_GPIO_CODEC_RESET;
GPSR = SHANNON_GPIO_CODEC_RESET;
}
MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
.atag_offset = 0x100,
.map_io = shannon_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_time = sa1100_timer_init,
.init_machine = shannon_init,
.init_late = sa11x0_init_late,
.restart = sa11x0_restart,
MACHINE_END

401
arch/arm/mach-sa1100/simpad.c Normal file
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/*
* linux/arch/arm/mach-sa1100/simpad.c
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/pm.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/mfd/ucb1x00.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#include <mach/simpad.h>
#include <mach/irqs.h>
#include <linux/serial_core.h>
#include <linux/ioport.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <linux/i2c-gpio.h>
#include "generic.h"
/*
* CS3 support
*/
static long cs3_shadow;
static spinlock_t cs3_lock;
static struct gpio_chip cs3_gpio;
long simpad_get_cs3_ro(void)
{
return readl(CS3_BASE);
}
EXPORT_SYMBOL(simpad_get_cs3_ro);
long simpad_get_cs3_shadow(void)
{
return cs3_shadow;
}
EXPORT_SYMBOL(simpad_get_cs3_shadow);
static void __simpad_write_cs3(void)
{
writel(cs3_shadow, CS3_BASE);
}
void simpad_set_cs3_bit(int value)
{
unsigned long flags;
spin_lock_irqsave(&cs3_lock, flags);
cs3_shadow |= value;
__simpad_write_cs3();
spin_unlock_irqrestore(&cs3_lock, flags);
}
EXPORT_SYMBOL(simpad_set_cs3_bit);
void simpad_clear_cs3_bit(int value)
{
unsigned long flags;
spin_lock_irqsave(&cs3_lock, flags);
cs3_shadow &= ~value;
__simpad_write_cs3();
spin_unlock_irqrestore(&cs3_lock, flags);
}
EXPORT_SYMBOL(simpad_clear_cs3_bit);
static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
if (offset > 15)
return;
if (value)
simpad_set_cs3_bit(1 << offset);
else
simpad_clear_cs3_bit(1 << offset);
};
static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset)
{
if (offset > 15)
return simpad_get_cs3_ro() & (1 << (offset - 16));
return simpad_get_cs3_shadow() & (1 << offset);
};
static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
if (offset > 15)
return 0;
return -EINVAL;
};
static int cs3_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
if (offset > 15)
return -EINVAL;
cs3_gpio_set(chip, offset, value);
return 0;
};
static struct map_desc simpad_io_desc[] __initdata = {
{ /* MQ200 */
.virtual = 0xf2800000,
.pfn = __phys_to_pfn(0x4b800000),
.length = 0x00800000,
.type = MT_DEVICE
}, { /* Simpad CS3 */
.virtual = (unsigned long)CS3_BASE,
.pfn = __phys_to_pfn(SA1100_CS3_PHYS),
.length = 0x00100000,
.type = MT_DEVICE
},
};
static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
if (port->mapbase == (u_int)&Ser1UTCR0) {
if (state)
{
simpad_clear_cs3_bit(RS232_ON);
simpad_clear_cs3_bit(DECT_POWER_ON);
}else
{
simpad_set_cs3_bit(RS232_ON);
simpad_set_cs3_bit(DECT_POWER_ON);
}
}
}
static struct sa1100_port_fns simpad_port_fns __initdata = {
.pm = simpad_uart_pm,
};
static struct mtd_partition simpad_partitions[] = {
{
.name = "SIMpad boot firmware",
.size = 0x00080000,
.offset = 0,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "SIMpad kernel",
.size = 0x0010000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "SIMpad root jffs2",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct flash_platform_data simpad_flash_data = {
.map_name = "cfi_probe",
.parts = simpad_partitions,
.nr_parts = ARRAY_SIZE(simpad_partitions),
};
static struct resource simpad_flash_resources [] = {
DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M),
DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M),
};
static struct ucb1x00_plat_data simpad_ucb1x00_data = {
.gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
};
static struct mcp_plat_data simpad_mcp_data = {
.mccr0 = MCCR0_ADM,
.sclk_rate = 11981000,
.codec_pdata = &simpad_ucb1x00_data,
};
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
/* Initialize CS3 */
cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON |
RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
__simpad_write_cs3(); /* Spinlocks not yet initialized */
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3); /* serial interface */
sa1100_register_uart(1, 1); /* DECT */
// Reassign UART 1 pins
GAFR |= GPIO_UART_TXD | GPIO_UART_RXD;
GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0| PWER_RTC;
PGSR = 0x818;
PCFR = 0;
PSDR = 0;
}
static void simpad_power_off(void)
{
local_irq_disable();
cs3_shadow = SD_MEDIAQ;
__simpad_write_cs3(); /* Bypass spinlock here */
/* disable internal oscillator, float CS lines */
PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
/* enable wake-up on GPIO0 */
PWER = GFER = GRER = PWER_GPIO0;
/*
* set scratchpad to zero, just in case it is used as a
* restart address by the bootloader.
*/
PSPR = 0;
PGSR = 0;
/* enter sleep mode */
PMCR = PMCR_SF;
while(1);
local_irq_enable(); /* we won't ever call it */
}
/*
* gpio_keys
*/
static struct gpio_keys_button simpad_button_table[] = {
{ KEY_POWER, IRQ_GPIO_POWER_BUTTON, 1, "power button" },
};
static struct gpio_keys_platform_data simpad_keys_data = {
.buttons = simpad_button_table,
.nbuttons = ARRAY_SIZE(simpad_button_table),
};
static struct platform_device simpad_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &simpad_keys_data,
},
};
static struct gpio_keys_button simpad_polled_button_table[] = {
{ KEY_PROG1, SIMPAD_UCB1X00_GPIO_PROG1, 1, "prog1 button" },
{ KEY_PROG2, SIMPAD_UCB1X00_GPIO_PROG2, 1, "prog2 button" },
{ KEY_UP, SIMPAD_UCB1X00_GPIO_UP, 1, "up button" },
{ KEY_DOWN, SIMPAD_UCB1X00_GPIO_DOWN, 1, "down button" },
{ KEY_LEFT, SIMPAD_UCB1X00_GPIO_LEFT, 1, "left button" },
{ KEY_RIGHT, SIMPAD_UCB1X00_GPIO_RIGHT, 1, "right button" },
};
static struct gpio_keys_platform_data simpad_polled_keys_data = {
.buttons = simpad_polled_button_table,
.nbuttons = ARRAY_SIZE(simpad_polled_button_table),
.poll_interval = 50,
};
static struct platform_device simpad_polled_keys = {
.name = "gpio-keys-polled",
.dev = {
.platform_data = &simpad_polled_keys_data,
},
};
/*
* GPIO LEDs
*/
static struct gpio_led simpad_leds[] = {
{
.name = "simpad:power",
.gpio = SIMPAD_CS3_LED2_ON,
.active_low = 0,
.default_trigger = "default-on",
},
};
static struct gpio_led_platform_data simpad_led_data = {
.num_leds = ARRAY_SIZE(simpad_leds),
.leds = simpad_leds,
};
static struct platform_device simpad_gpio_leds = {
.name = "leds-gpio",
.id = 0,
.dev = {
.platform_data = &simpad_led_data,
},
};
/*
* i2c
*/
static struct i2c_gpio_platform_data simpad_i2c_data = {
.sda_pin = GPIO_GPIO21,
.scl_pin = GPIO_GPIO25,
.udelay = 10,
.timeout = HZ,
};
static struct platform_device simpad_i2c = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = &simpad_i2c_data,
},
};
/*
* MediaQ Video Device
*/
static struct platform_device simpad_mq200fb = {
.name = "simpad-mq200",
.id = 0,
};
static struct platform_device *devices[] __initdata = {
&simpad_keys,
&simpad_polled_keys,
&simpad_mq200fb,
&simpad_gpio_leds,
&simpad_i2c,
};
static int __init simpad_init(void)
{
int ret;
spin_lock_init(&cs3_lock);
cs3_gpio.label = "simpad_cs3";
cs3_gpio.base = SIMPAD_CS3_GPIO_BASE;
cs3_gpio.ngpio = 24;
cs3_gpio.set = cs3_gpio_set;
cs3_gpio.get = cs3_gpio_get;
cs3_gpio.direction_input = cs3_gpio_direction_input;
cs3_gpio.direction_output = cs3_gpio_direction_output;
ret = gpiochip_add(&cs3_gpio);
if (ret)
printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device");
pm_power_off = simpad_power_off;
sa11x0_ppc_configure_mcp();
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
ARRAY_SIZE(simpad_flash_resources));
sa11x0_register_mcp(&simpad_mcp_data);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if(ret)
printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
return 0;
}
arch_initcall(simpad_init);
MACHINE_START(SIMPAD, "Simpad")
/* Maintainer: Holger Freyther */
.atag_offset = 0x100,
.map_io = simpad_map_io,
.nr_irqs = SA1100_NR_IRQS,
.init_irq = sa1100_init_irq,
.init_late = sa11x0_init_late,
.init_time = sa1100_timer_init,
.restart = sa11x0_restart,
MACHINE_END

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arch/arm/mach-sa1100/sleep.S Normal file
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/*
* SA11x0 Assembler Sleep/WakeUp Management Routines
*
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*
* History:
*
* 2001-02-06: Cliff Brake Initial code
*
* 2001-08-29: Nicolas Pitre Simplified.
*
* 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
* Storage is on the stack now.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>
.text
/*
* sa1100_finish_suspend()
*
* Causes sa11x0 to enter sleep state
*
* Must be aligned to a cacheline.
*/
.balign 32
ENTRY(sa1100_finish_suspend)
@ disable clock switching
mcr p15, 0, r1, c15, c2, 2
ldr r6, =MDREFR
ldr r4, [r6]
orr r4, r4, #MDREFR_K1DB2
ldr r5, =PPCR
@ Pre-load __loop_udelay into the I-cache
mov r0, #1
bl __loop_udelay
mov r0, r0
@ The following must all exist in a single cache line to
@ avoid accessing memory until this sequence is complete,
@ otherwise we occasionally hang.
@ Adjust memory timing before lowering CPU clock
str r4, [r6]
@ delay 90us and set CPU PLL to lowest speed
@ fixes resume problem on high speed SA1110
mov r0, #90
bl __loop_udelay
mov r1, #0
str r1, [r5]
mov r0, #90
bl __loop_udelay
/*
* SA1110 SDRAM controller workaround. register values:
*
* r0 = &MSC0
* r1 = &MSC1
* r2 = &MSC2
* r3 = MSC0 value
* r4 = MSC1 value
* r5 = MSC2 value
* r6 = &MDREFR
* r7 = first MDREFR value
* r8 = second MDREFR value
* r9 = &MDCNFG
* r10 = MDCNFG value
* r11 = third MDREFR value
* r12 = &PMCR
* r13 = PMCR value (1)
*/
ldr r0, =MSC0
ldr r1, =MSC1
ldr r2, =MSC2
ldr r3, [r0]
bic r3, r3, #FMsk(MSC_RT)
bic r3, r3, #FMsk(MSC_RT)<<16
ldr r4, [r1]
bic r4, r4, #FMsk(MSC_RT)
bic r4, r4, #FMsk(MSC_RT)<<16
ldr r5, [r2]
bic r5, r5, #FMsk(MSC_RT)
bic r5, r5, #FMsk(MSC_RT)<<16
ldr r7, [r6]
bic r7, r7, #0x0000FF00
bic r7, r7, #0x000000F0
orr r8, r7, #MDREFR_SLFRSH
ldr r9, =MDCNFG
ldr r10, [r9]
bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
bic r11, r8, #MDREFR_SLFRSH
bic r11, r11, #MDREFR_E1PIN
ldr r12, =PMCR
mov r13, #PMCR_SF
b sa1110_sdram_controller_fix
.align 5
sa1110_sdram_controller_fix:
@ Step 1 clear RT field of all MSCx registers
str r3, [r0]
str r4, [r1]
str r5, [r2]
@ Step 2 clear DRI field in MDREFR
str r7, [r6]
@ Step 3 set SLFRSH bit in MDREFR
str r8, [r6]
@ Step 4 clear DE bis in MDCNFG
str r10, [r9]
@ Step 5 clear DRAM refresh control register
str r11, [r6]
@ Wow, now the hardware suspend request pins can be used, that makes them functional for
@ about 7 ns out of the entire time that the CPU is running!
@ Step 6 set force sleep bit in PMCR
str r13, [r12]
20: b 20b @ loop waiting for sleep

243
arch/arm/mach-sa1100/ssp.c Normal file
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/*
* linux/arch/arm/mach-sa1100/ssp.c
*
* Copyright (C) 2003 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Generic SSP driver. This provides the generic core for simple
* IO-based SSP applications.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/hardware/ssp.h>
#define TIMEOUT 100000
static irqreturn_t ssp_interrupt(int irq, void *dev_id)
{
unsigned int status = Ser4SSSR;
if (status & SSSR_ROR)
printk(KERN_WARNING "SSP: receiver overrun\n");
Ser4SSSR = SSSR_ROR;
return status ? IRQ_HANDLED : IRQ_NONE;
}
/**
* ssp_write_word - write a word to the SSP port
* @data: 16-bit, MSB justified data to write.
*
* Wait for a free entry in the SSP transmit FIFO, and write a data
* word to the SSP port. Wait for the SSP port to start sending
* the data.
*
* The caller is expected to perform the necessary locking.
*
* Returns:
* %-ETIMEDOUT timeout occurred
* 0 success
*/
int ssp_write_word(u16 data)
{
int timeout = TIMEOUT;
while (!(Ser4SSSR & SSSR_TNF)) {
if (!--timeout)
return -ETIMEDOUT;
cpu_relax();
}
Ser4SSDR = data;
timeout = TIMEOUT;
while (!(Ser4SSSR & SSSR_BSY)) {
if (!--timeout)
return -ETIMEDOUT;
cpu_relax();
}
return 0;
}
/**
* ssp_read_word - read a word from the SSP port
*
* Wait for a data word in the SSP receive FIFO, and return the
* received data. Data is LSB justified.
*
* Note: Currently, if data is not expected to be received, this
* function will wait for ever.
*
* The caller is expected to perform the necessary locking.
*
* Returns:
* %-ETIMEDOUT timeout occurred
* 16-bit data success
*/
int ssp_read_word(u16 *data)
{
int timeout = TIMEOUT;
while (!(Ser4SSSR & SSSR_RNE)) {
if (!--timeout)
return -ETIMEDOUT;
cpu_relax();
}
*data = (u16)Ser4SSDR;
return 0;
}
/**
* ssp_flush - flush the transmit and receive FIFOs
*
* Wait for the SSP to idle, and ensure that the receive FIFO
* is empty.
*
* The caller is expected to perform the necessary locking.
*
* Returns:
* %-ETIMEDOUT timeout occurred
* 0 success
*/
int ssp_flush(void)
{
int timeout = TIMEOUT * 2;
do {
while (Ser4SSSR & SSSR_RNE) {
if (!--timeout)
return -ETIMEDOUT;
(void) Ser4SSDR;
}
if (!--timeout)
return -ETIMEDOUT;
} while (Ser4SSSR & SSSR_BSY);
return 0;
}
/**
* ssp_enable - enable the SSP port
*
* Turn on the SSP port.
*/
void ssp_enable(void)
{
Ser4SSCR0 |= SSCR0_SSE;
}
/**
* ssp_disable - shut down the SSP port
*
* Turn off the SSP port, optionally powering it down.
*/
void ssp_disable(void)
{
Ser4SSCR0 &= ~SSCR0_SSE;
}
/**
* ssp_save_state - save the SSP configuration
* @ssp: pointer to structure to save SSP configuration
*
* Save the configured SSP state for suspend.
*/
void ssp_save_state(struct ssp_state *ssp)
{
ssp->cr0 = Ser4SSCR0;
ssp->cr1 = Ser4SSCR1;
Ser4SSCR0 &= ~SSCR0_SSE;
}
/**
* ssp_restore_state - restore a previously saved SSP configuration
* @ssp: pointer to configuration saved by ssp_save_state
*
* Restore the SSP configuration saved previously by ssp_save_state.
*/
void ssp_restore_state(struct ssp_state *ssp)
{
Ser4SSSR = SSSR_ROR;
Ser4SSCR0 = ssp->cr0 & ~SSCR0_SSE;
Ser4SSCR1 = ssp->cr1;
Ser4SSCR0 = ssp->cr0;
}
/**
* ssp_init - setup the SSP port
*
* initialise and claim resources for the SSP port.
*
* Returns:
* %-ENODEV if the SSP port is unavailable
* %-EBUSY if the resources are already in use
* %0 on success
*/
int ssp_init(void)
{
int ret;
if (!(PPAR & PPAR_SPR) && (Ser4MCCR0 & MCCR0_MCE))
return -ENODEV;
if (!request_mem_region(__PREG(Ser4SSCR0), 0x18, "SSP")) {
return -EBUSY;
}
Ser4SSSR = SSSR_ROR;
ret = request_irq(IRQ_Ser4SSP, ssp_interrupt, 0, "SSP", NULL);
if (ret)
goto out_region;
return 0;
out_region:
release_mem_region(__PREG(Ser4SSCR0), 0x18);
return ret;
}
/**
* ssp_exit - undo the effects of ssp_init
*
* release and free resources for the SSP port.
*/
void ssp_exit(void)
{
Ser4SSCR0 &= ~SSCR0_SSE;
free_irq(IRQ_Ser4SSP, NULL);
release_mem_region(__PREG(Ser4SSCR0), 0x18);
}
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("SA11x0 SSP PIO driver");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(ssp_write_word);
EXPORT_SYMBOL(ssp_read_word);
EXPORT_SYMBOL(ssp_flush);
EXPORT_SYMBOL(ssp_enable);
EXPORT_SYMBOL(ssp_disable);
EXPORT_SYMBOL(ssp_save_state);
EXPORT_SYMBOL(ssp_restore_state);
EXPORT_SYMBOL(ssp_init);
EXPORT_SYMBOL(ssp_exit);

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arch/arm/mach-sa1100/time.c Normal file
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/*
* linux/arch/arm/mach-sa1100/time.c
*
* Copyright (C) 1998 Deborah Wallach.
* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
*
* 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
* Rewritten: big cleanup, much simpler, better HZ accuracy.
*
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/timex.h>
#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
static u32 notrace sa1100_read_sched_clock(void)
{
return readl_relaxed(OSCR);
}
#define MIN_OSCR_DELTA 2
static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
/* Disarm the compare/match, signal the event. */
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
c->event_handler(c);
return IRQ_HANDLED;
}
static int
sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
{
unsigned long next, oscr;
writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
next = readl_relaxed(OSCR) + delta;
writel_relaxed(next, OSMR0);
oscr = readl_relaxed(OSCR);
return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
}
static void
sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
{
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
writel_relaxed(OSSR_M0, OSSR);
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
break;
}
}
#ifdef CONFIG_PM
unsigned long osmr[4], oier;
static void sa1100_timer_suspend(struct clock_event_device *cedev)
{
osmr[0] = readl_relaxed(OSMR0);
osmr[1] = readl_relaxed(OSMR1);
osmr[2] = readl_relaxed(OSMR2);
osmr[3] = readl_relaxed(OSMR3);
oier = readl_relaxed(OIER);
}
static void sa1100_timer_resume(struct clock_event_device *cedev)
{
writel_relaxed(0x0f, OSSR);
writel_relaxed(osmr[0], OSMR0);
writel_relaxed(osmr[1], OSMR1);
writel_relaxed(osmr[2], OSMR2);
writel_relaxed(osmr[3], OSMR3);
writel_relaxed(oier, OIER);
/*
* OSMR0 is the system timer: make sure OSCR is sufficiently behind
*/
writel_relaxed(OSMR0 - LATCH, OSCR);
}
#else
#define sa1100_timer_suspend NULL
#define sa1100_timer_resume NULL
#endif
static struct clock_event_device ckevt_sa1100_osmr0 = {
.name = "osmr0",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = sa1100_osmr0_set_next_event,
.set_mode = sa1100_osmr0_set_mode,
.suspend = sa1100_timer_suspend,
.resume = sa1100_timer_resume,
};
static struct irqaction sa1100_timer_irq = {
.name = "ost0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = sa1100_ost0_interrupt,
.dev_id = &ckevt_sa1100_osmr0,
};
void __init sa1100_timer_init(void)
{
writel_relaxed(0, OIER);
writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
setup_irq(IRQ_OST0, &sa1100_timer_irq);
clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
clocksource_mmio_readl_up);
clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
MIN_OSCR_DELTA * 2, 0x7fffffff);
}