nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
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43
arch/arm/mach-msm/include/mach/board.h Normal file
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/* arch/arm/mach-msm/include/mach/board.h
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_BOARD_H
#define __ASM_ARCH_MSM_BOARD_H
#include <linux/types.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
/* platform device data structures */
struct clk_lookup;
/* common init routines for use by arch/arm/mach-msm/board-*.c */
void __init msm_add_devices(void);
void __init msm_init_irq(void);
void __init msm_init_gpio(void);
void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
int smd_debugfs_init(void);
#else
static inline int smd_debugfs_init(void) { return 0; }
#endif
#endif

40
arch/arm/mach-msm/include/mach/clk.h Normal file
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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_CLK_H
#define __MACH_CLK_H
/* Magic rate value for use with PM QOS to request the board's maximum
* supported AXI rate. PM QOS will only pass positive s32 rate values
* through to the clock driver, so INT_MAX is used.
*/
#define MSM_AXI_MAX_FREQ LONG_MAX
enum clk_reset_action {
CLK_RESET_DEASSERT = 0,
CLK_RESET_ASSERT = 1
};
struct clk;
/* Rate is minimum clock rate in Hz */
int clk_set_min_rate(struct clk *clk, unsigned long rate);
/* Rate is maximum clock rate in Hz */
int clk_set_max_rate(struct clk *clk, unsigned long rate);
/* Assert/Deassert reset to a hardware block associated with a clock */
int clk_reset(struct clk *clk, enum clk_reset_action action);
/* Set clock-specific configuration parameters */
int clk_set_flags(struct clk *clk, unsigned long flags);
#endif

65
arch/arm/mach-msm/include/mach/debug-macro.S Normal file
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/*
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
.macro addruart, rp, rv, tmp
#ifdef MSM_DEBUG_UART_PHYS
ldr \rp, =MSM_DEBUG_UART_PHYS
ldr \rv, =MSM_DEBUG_UART_BASE
#endif
.endm
.macro senduart, rd, rx
#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
@ Write the 1 character to UARTDM_TF
str \rd, [\rx, #0x70]
#else
str \rd, [\rx, #0x0C]
#endif
.endm
.macro waituart, rd, rx
#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
@ check for TX_EMT in UARTDM_SR
ldr \rd, [\rx, #0x08]
tst \rd, #0x08
bne 1002f
@ wait for TXREADY in UARTDM_ISR
1001: ldr \rd, [\rx, #0x14]
tst \rd, #0x80
beq 1001b
1002:
@ Clear TX_READY by writing to the UARTDM_CR register
mov \rd, #0x300
str \rd, [\rx, #0x10]
@ Write 0x1 to NCF register
mov \rd, #0x1
str \rd, [\rx, #0x40]
@ UARTDM reg. Read to induce delay
ldr \rd, [\rx, #0x08]
#else
@ wait for TX_READY
1001: ldr \rd, [\rx, #0x08]
tst \rd, #0x04
beq 1001b
#endif
.endm
.macro busyuart, rd, rx
.endm

151
arch/arm/mach-msm/include/mach/dma.h Normal file
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/* linux/include/asm-arm/arch-msm/dma.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_DMA_H
#include <linux/list.h>
struct msm_dmov_errdata {
uint32_t flush[6];
};
struct msm_dmov_cmd {
struct list_head list;
unsigned int cmdptr;
void (*complete_func)(struct msm_dmov_cmd *cmd,
unsigned int result,
struct msm_dmov_errdata *err);
void (*execute_func)(struct msm_dmov_cmd *cmd);
void *data;
};
#ifndef CONFIG_ARCH_MSM8X60
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
#else
static inline
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
static inline
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
static inline
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
#endif
#define DMOV_CMD_LIST (0 << 29) /* does not work */
#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
#define DMOV_RSLT_ERROR (1 << 3)
#define DMOV_RSLT_FLUSH (1 << 2)
#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
#define DMOV_STATUS_RSLT_VALID (1 << 1)
#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
#define DMOV_CONFIG_IRQ_EN (1 << 0)
/* channel assignments */
#define DMOV_NAND_CHAN 7
#define DMOV_NAND_CRCI_CMD 5
#define DMOV_NAND_CRCI_DATA 4
#define DMOV_SDC1_CHAN 8
#define DMOV_SDC1_CRCI 6
#define DMOV_SDC2_CHAN 8
#define DMOV_SDC2_CRCI 7
#define DMOV_TSIF_CHAN 10
#define DMOV_TSIF_CRCI 10
#define DMOV_USB_CHAN 11
/* no client rate control ifc (eg, ram) */
#define DMOV_NONE_CRCI 0
/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
* is going to walk a list of 32bit pointers as described below. Each
* pointer points to a *array* of dmov_s, etc structs. The last pointer
* in the list is marked with CMD_PTR_LP. The last struct in each array
* is marked with CMD_LC (see below).
*/
#define CMD_PTR_ADDR(addr) ((addr) >> 3)
#define CMD_PTR_LP (1 << 31) /* last pointer */
#define CMD_PTR_PT (3 << 29) /* ? */
/* Single Item Mode */
typedef struct {
unsigned cmd;
unsigned src;
unsigned dst;
unsigned len;
} dmov_s;
/* Scatter/Gather Mode */
typedef struct {
unsigned cmd;
unsigned src_dscr;
unsigned dst_dscr;
unsigned _reserved;
} dmov_sg;
/* Box mode */
typedef struct {
uint32_t cmd;
uint32_t src_row_addr;
uint32_t dst_row_addr;
uint32_t src_dst_len;
uint32_t num_rows;
uint32_t row_offset;
} dmov_box;
/* bits for the cmd field of the above structures */
#define CMD_LC (1 << 31) /* last command */
#define CMD_FR (1 << 22) /* force result -- does not work? */
#define CMD_OCU (1 << 21) /* other channel unblock */
#define CMD_OCB (1 << 20) /* other channel block */
#define CMD_TCB (1 << 19) /* ? */
#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
#define CMD_MODE_SG (1 << 0) /* untested */
#define CMD_MODE_IND_SG (2 << 0) /* untested */
#define CMD_MODE_BOX (3 << 0) /* untested */
#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
#define CMD_DST_CRCI(n) (((n) & 15) << 7)
#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
#endif

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arch/arm/mach-msm/include/mach/entry-macro.S Normal file
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#if !defined(CONFIG_ARM_GIC)
#include <mach/msm_iomap.h>
.macro get_irqnr_preamble, base, tmp
@ enable imprecise aborts
cpsie a
mov \base, #MSM_VIC_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ 0xD0 has irq# or old irq# if the irq has been handled
@ 0xD4 has irq# or -1 if none pending *but* if you just
@ read 0xD4 you never get the first irq for some reason
ldr \irqnr, [\base, #0xD0]
ldr \irqnr, [\base, #0xD4]
cmp \irqnr, #0xffffffff
.endm
#endif

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arch/arm/mach-msm/include/mach/hardware.h Normal file
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/* arch/arm/mach-msm/include/mach/hardware.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_HARDWARE_H
#endif

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arch/arm/mach-msm/include/mach/iommu.h Normal file
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef MSM_IOMMU_H
#define MSM_IOMMU_H
#include <linux/interrupt.h>
#include <linux/clk.h>
/* Sharability attributes of MSM IOMMU mappings */
#define MSM_IOMMU_ATTR_NON_SH 0x0
#define MSM_IOMMU_ATTR_SH 0x4
/* Cacheability attributes of MSM IOMMU mappings */
#define MSM_IOMMU_ATTR_NONCACHED 0x0
#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
#define MSM_IOMMU_ATTR_CACHED_WT 0x3
/* Mask for the cache policy attribute */
#define MSM_IOMMU_CP_MASK 0x03
/* Maximum number of Machine IDs that we are allowing to be mapped to the same
* context bank. The number of MIDs mapped to the same CB does not affect
* performance, but there is a practical limit on how many distinct MIDs may
* be present. These mappings are typically determined at design time and are
* not expected to change at run time.
*/
#define MAX_NUM_MIDS 32
/**
* struct msm_iommu_dev - a single IOMMU hardware instance
* name Human-readable name given to this IOMMU HW instance
* ncb Number of context banks present on this IOMMU HW instance
*/
struct msm_iommu_dev {
const char *name;
int ncb;
};
/**
* struct msm_iommu_ctx_dev - an IOMMU context bank instance
* name Human-readable name given to this context bank
* num Index of this context bank within the hardware
* mids List of Machine IDs that are to be mapped into this context
* bank, terminated by -1. The MID is a set of signals on the
* AXI bus that identifies the function associated with a specific
* memory request. (See ARM spec).
*/
struct msm_iommu_ctx_dev {
const char *name;
int num;
int mids[MAX_NUM_MIDS];
};
/**
* struct msm_iommu_drvdata - A single IOMMU hardware instance
* @base: IOMMU config port base address (VA)
* @ncb The number of contexts on this IOMMU
* @irq: Interrupt number
* @clk: The bus clock for this IOMMU hardware instance
* @pclk: The clock for the IOMMU bus interconnect
*
* A msm_iommu_drvdata holds the global driver data about a single piece
* of an IOMMU hardware instance.
*/
struct msm_iommu_drvdata {
void __iomem *base;
int irq;
int ncb;
struct clk *clk;
struct clk *pclk;
};
/**
* struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
* @num: Hardware context number of this context
* @pdev: Platform device associated wit this HW instance
* @attached_elm: List element for domains to track which devices are
* attached to them
*
* A msm_iommu_ctx_drvdata holds the driver data for a single context bank
* within each IOMMU hardware instance
*/
struct msm_iommu_ctx_drvdata {
int num;
struct platform_device *pdev;
struct list_head attached_elm;
};
/*
* Look up an IOMMU context device by its context name. NULL if none found.
* Useful for testing and drivers that do not yet fully have IOMMU stuff in
* their platform devices.
*/
struct device *msm_iommu_get_ctx(const char *ctx_name);
/*
* Interrupt handler for the IOMMU context fault interrupt. Hooking the
* interrupt is not supported in the API yet, but this will print an error
* message and dump useful IOMMU registers.
*/
irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
#endif

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arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h Normal file
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75
arch/arm/mach-msm/include/mach/irqs-7x00.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*/
#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
#define __ASM_ARCH_MSM_IRQS_7X00_H
/* MSM ARM11 Interrupt Numbers */
/* See 80-VE113-1 A, pp219-221 */
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_UART1 9
#define INT_UART2 10
#define INT_UART3 11
#define INT_UART1_RX 12
#define INT_UART2_RX 13
#define INT_UART3_RX 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_GPIO_GROUP1 (32 + 0)
#define INT_GPIO_GROUP2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_SOFTRESET (32 + 3)
#define INT_NAND_WR_ER_DONE (32 + 4)
#define INT_NAND_OP_DONE (32 + 5)
#define INT_PBUS_ARM11 (32 + 6)
#define INT_AXI_MPU_SMI (32 + 7)
#define INT_AXI_MPU_EBI1 (32 + 8)
#define INT_AD_HSSD (32 + 9)
#define INT_ARM11_PMU (32 + 10)
#define INT_ARM11_DMA (32 + 11)
#define INT_TSIF_IRQ (32 + 12)
#define INT_UART1DM_IRQ (32 + 13)
#define INT_UART1DM_RX (32 + 14)
#define INT_USB_HS (32 + 15)
#define INT_SDC3_0 (32 + 16)
#define INT_SDC3_1 (32 + 17)
#define INT_SDC4_0 (32 + 18)
#define INT_SDC4_1 (32 + 19)
#define INT_UART2DM_RX (32 + 20)
#define INT_UART2DM_IRQ (32 + 21)
/* 22-31 are reserved */
#define NR_MSM_IRQS 64
#define NR_GPIO_IRQS 122
#define NR_BOARD_IRQS 64
#endif

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arch/arm/mach-msm/include/mach/irqs-7x30.h Normal file
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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
#define __ASM_ARCH_MSM_IRQS_7X30_H
/* MSM ACPU Interrupt Numbers */
#define INT_DEBUG_TIMER_EXP 0
#define INT_GPT0_TIMER_EXP 1
#define INT_GPT1_TIMER_EXP 2
#define INT_WDT0_ACCSCSSBARK 3
#define INT_WDT1_ACCSCSSBARK 4
#define INT_AVS_SVIC 5
#define INT_AVS_SVIC_SW_DONE 6
#define INT_SC_DBG_RX_FULL 7
#define INT_SC_DBG_TX_EMPTY 8
#define INT_ARM11_PM 9
#define INT_AVS_REQ_DOWN 10
#define INT_AVS_REQ_UP 11
#define INT_SC_ACG 12
/* SCSS_VICFIQSTS0[13:15] are RESERVED */
#define INT_L2_SVICCPUIRPTREQ 16
#define INT_L2_SVICDMANSIRPTREQ 17
#define INT_L2_SVICDMASIRPTREQ 18
#define INT_L2_SVICSLVIRPTREQ 19
#define INT_AD5A_MPROC_APPS_0 20
#define INT_AD5A_MPROC_APPS_1 21
#define INT_A9_M2A_0 22
#define INT_A9_M2A_1 23
#define INT_A9_M2A_2 24
#define INT_A9_M2A_3 25
#define INT_A9_M2A_4 26
#define INT_A9_M2A_5 27
#define INT_A9_M2A_6 28
#define INT_A9_M2A_7 29
#define INT_A9_M2A_8 30
#define INT_A9_M2A_9 31
#define INT_AXI_EBI1_SC (32 + 0)
#define INT_IMEM_ERR (32 + 1)
#define INT_AXI_EBI0_SC (32 + 2)
#define INT_PBUS_SC_IRQC (32 + 3)
#define INT_PERPH_BUS_BPM (32 + 4)
#define INT_CC_TEMP_SENSE (32 + 5)
#define INT_UXMC_EBI0 (32 + 6)
#define INT_UXMC_EBI1 (32 + 7)
#define INT_EBI2_OP_DONE (32 + 8)
#define INT_EBI2_WR_ER_DONE (32 + 9)
#define INT_TCSR_SPSS_CE (32 + 10)
#define INT_EMDH (32 + 11)
#define INT_PMDH (32 + 12)
#define INT_MDC (32 + 13)
#define INT_MIDI_TO_SUPSS (32 + 14)
#define INT_LPA_2 (32 + 15)
#define INT_GPIO_GROUP1_SECURE (32 + 16)
#define INT_GPIO_GROUP2_SECURE (32 + 17)
#define INT_GPIO_GROUP1 (32 + 18)
#define INT_GPIO_GROUP2 (32 + 19)
#define INT_MPRPH_SOFTRESET (32 + 20)
#define INT_PWB_I2C (32 + 21)
#define INT_PWB_I2C_2 (32 + 22)
#define INT_TSSC_SAMPLE (32 + 23)
#define INT_TSSC_PENUP (32 + 24)
#define INT_TCHSCRN_SSBI (32 + 25)
#define INT_FM_RDS (32 + 26)
#define INT_KEYSENSE (32 + 27)
#define INT_USB_OTG_HS (32 + 28)
#define INT_USB_OTG_HS2 (32 + 29)
#define INT_USB_OTG_HS3 (32 + 30)
#define INT_CSI (32 + 31)
#define INT_SPI_OUTPUT (64 + 0)
#define INT_SPI_INPUT (64 + 1)
#define INT_SPI_ERROR (64 + 2)
#define INT_UART1 (64 + 3)
#define INT_UART1_RX (64 + 4)
#define INT_UART2 (64 + 5)
#define INT_UART2_RX (64 + 6)
#define INT_UART3 (64 + 7)
#define INT_UART3_RX (64 + 8)
#define INT_UART1DM_IRQ (64 + 9)
#define INT_UART1DM_RX (64 + 10)
#define INT_UART2DM_IRQ (64 + 11)
#define INT_UART2DM_RX (64 + 12)
#define INT_TSIF (64 + 13)
#define INT_ADM_SC1 (64 + 14)
#define INT_ADM_SC2 (64 + 15)
#define INT_MDP (64 + 16)
#define INT_VPE (64 + 17)
#define INT_GRP_2D (64 + 18)
#define INT_GRP_3D (64 + 19)
#define INT_ROTATOR (64 + 20)
#define INT_MFC720 (64 + 21)
#define INT_JPEG (64 + 22)
#define INT_VFE (64 + 23)
#define INT_TV_ENC (64 + 24)
#define INT_PMIC_SSBI (64 + 25)
#define INT_MPM_1 (64 + 26)
#define INT_TCSR_SPSS_SAMPLE (64 + 27)
#define INT_TCSR_SPSS_PENUP (64 + 28)
#define INT_MPM_2 (64 + 29)
#define INT_SDC1_0 (64 + 30)
#define INT_SDC1_1 (64 + 31)
#define INT_SDC3_0 (96 + 0)
#define INT_SDC3_1 (96 + 1)
#define INT_SDC2_0 (96 + 2)
#define INT_SDC2_1 (96 + 3)
#define INT_SDC4_0 (96 + 4)
#define INT_SDC4_1 (96 + 5)
#define INT_PWB_QUP_IN (96 + 6)
#define INT_PWB_QUP_OUT (96 + 7)
#define INT_PWB_QUP_ERR (96 + 8)
#define INT_SCSS_WDT0_BITE (96 + 9)
/* SCSS_VICFIQSTS3[10:31] are RESERVED */
/* Retrofit universal macro names */
#define INT_ADM_AARM INT_ADM_SC2
#define INT_USB_HS INT_USB_OTG_HS
#define INT_USB_OTG INT_USB_OTG_HS
#define INT_TCHSCRN1 INT_TSSC_SAMPLE
#define INT_TCHSCRN2 INT_TSSC_PENUP
#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0
#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1
#define INT_MDDI_EXT INT_EMDH
#define INT_MDDI_PRI INT_PMDH
#define INT_MDDI_CLIENT INT_MDC
#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE
#define INT_NAND_OP_DONE INT_EBI2_OP_DONE
#define NR_MSM_IRQS 128
#define NR_GPIO_IRQS 182
#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
#define NR_PMIC8058_GPIO_IRQS 40
#define NR_PMIC8058_MPP_IRQS 12
#define NR_PMIC8058_MISC_IRQS 8
#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\
NR_PMIC8058_MPP_IRQS +\
NR_PMIC8058_MISC_IRQS)
#define NR_BOARD_IRQS NR_PMIC8058_IRQS
#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */

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/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_IRQS_8960_H
#define __ASM_ARCH_MSM_IRQS_8960_H
/* MSM ACPU Interrupt Numbers */
/* 0-15: STI/SGI (software triggered/generated interrupts)
16-31: PPI (private peripheral interrupts)
32+: SPI (shared peripheral interrupts) */
#define GIC_PPI_START 16
#define GIC_SPI_START 32
#define INT_VGIC (GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
#define AVS_SVICINT (GIC_PPI_START + 6)
#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
#define SC_AVSCPUXUP (GIC_PPI_START + 12)
#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
/* PPI 15 is unused */
#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
#define VPE_IRQ (GIC_SPI_START + 47)
#define VFE_IRQ (GIC_SPI_START + 48)
#define VCODEC_IRQ (GIC_SPI_START + 49)
#define TV_ENC_IRQ (GIC_SPI_START + 50)
#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
#define ROT_IRQ (GIC_SPI_START + 73)
#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
#define MDP_IRQ (GIC_SPI_START + 75)
#define JPEGD_IRQ (GIC_SPI_START + 76)
#define JPEG_IRQ (GIC_SPI_START + 77)
#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
#define HDMI_IRQ (GIC_SPI_START + 79)
#define GFX3D_IRQ (GIC_SPI_START + 80)
#define GFX2D0_IRQ (GIC_SPI_START + 81)
#define DSI1_IRQ (GIC_SPI_START + 82)
#define CSI_1_IRQ (GIC_SPI_START + 83)
#define CSI_0_IRQ (GIC_SPI_START + 84)
#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
#define USB1_HS_IRQ (GIC_SPI_START + 100)
#define SDC4_IRQ_0 (GIC_SPI_START + 101)
#define SDC3_IRQ_0 (GIC_SPI_START + 102)
#define SDC2_IRQ_0 (GIC_SPI_START + 103)
#define SDC1_IRQ_0 (GIC_SPI_START + 104)
#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
#define SPS_MTI_0 (GIC_SPI_START + 107)
#define SPS_MTI_1 (GIC_SPI_START + 108)
#define SPS_MTI_2 (GIC_SPI_START + 109)
#define SPS_MTI_3 (GIC_SPI_START + 110)
#define SPS_MTI_4 (GIC_SPI_START + 111)
#define SPS_MTI_5 (GIC_SPI_START + 112)
#define SPS_MTI_6 (GIC_SPI_START + 113)
#define SPS_MTI_7 (GIC_SPI_START + 114)
#define SPS_MTI_8 (GIC_SPI_START + 115)
#define SPS_MTI_9 (GIC_SPI_START + 116)
#define SPS_MTI_10 (GIC_SPI_START + 117)
#define SPS_MTI_11 (GIC_SPI_START + 118)
#define SPS_MTI_12 (GIC_SPI_START + 119)
#define SPS_MTI_13 (GIC_SPI_START + 120)
#define SPS_MTI_14 (GIC_SPI_START + 121)
#define SPS_MTI_15 (GIC_SPI_START + 122)
#define SPS_MTI_16 (GIC_SPI_START + 123)
#define SPS_MTI_17 (GIC_SPI_START + 124)
#define SPS_MTI_18 (GIC_SPI_START + 125)
#define SPS_MTI_19 (GIC_SPI_START + 126)
#define SPS_MTI_20 (GIC_SPI_START + 127)
#define SPS_MTI_21 (GIC_SPI_START + 128)
#define SPS_MTI_22 (GIC_SPI_START + 129)
#define SPS_MTI_23 (GIC_SPI_START + 130)
#define SPS_MTI_24 (GIC_SPI_START + 131)
#define SPS_MTI_25 (GIC_SPI_START + 132)
#define SPS_MTI_26 (GIC_SPI_START + 133)
#define SPS_MTI_27 (GIC_SPI_START + 134)
#define SPS_MTI_28 (GIC_SPI_START + 135)
#define SPS_MTI_29 (GIC_SPI_START + 136)
#define SPS_MTI_30 (GIC_SPI_START + 137)
#define SPS_MTI_31 (GIC_SPI_START + 138)
#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
#define USB2_IRQ (GIC_SPI_START + 141)
#define USB1_IRQ (GIC_SPI_START + 142)
#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
#define TSIF2_IRQ (GIC_SPI_START + 164)
#define TSIF1_IRQ (GIC_SPI_START + 165)
#define DSI2_IRQ (GIC_SPI_START + 166)
#define ISPIF_IRQ (GIC_SPI_START + 167)
#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
#define SDC5_IRQ_0 (GIC_SPI_START + 188)
#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
#define A2_BAM_IRQ (GIC_SPI_START + 209)
#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
#define GFX2D1_IRQ (GIC_SPI_START + 212)
#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
/* For now, use the maximum number of interrupts until a pending GIC issue
* is sorted out */
#define NR_MSM_IRQS 1020
#define NR_BOARD_IRQS 0
#define NR_GPIO_IRQS 0
#endif

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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
#define __ASM_ARCH_MSM_IRQS_8XXX_H
/* MSM ACPU Interrupt Numbers */
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_SIRC_0 9
#define INT_SDC3_0 10
#define INT_SDC3_1 11
#define INT_SDC4_0 12
#define INT_SDC4_1 13
#define INT_AD6_EXT_VFR 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_TCSR_MPRPH_SC1 (32 + 0)
#define INT_USB_FS2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_SOFTRESET (32 + 3)
#define INT_NAND_WR_ER_DONE (32 + 4)
#define INT_NAND_OP_DONE (32 + 5)
#define INT_TCSR_MPRPH_SC2 (32 + 6)
#define INT_OP_PEN (32 + 7)
#define INT_AD_HSSD (32 + 8)
#define INT_ARM11_PM (32 + 9)
#define INT_SDMA_NON_SECURE (32 + 10)
#define INT_TSIF_IRQ (32 + 11)
#define INT_UART1DM_IRQ (32 + 12)
#define INT_UART1DM_RX (32 + 13)
#define INT_SDMA_SECURE (32 + 14)
#define INT_SI2S_SLAVE (32 + 15)
#define INT_SC_I2CPU (32 + 16)
#define INT_SC_DBG_RDTRFULL (32 + 17)
#define INT_SC_DBG_WDTRFULL (32 + 18)
#define INT_SCPLL_CTL_DONE (32 + 19)
#define INT_UART2DM_IRQ (32 + 20)
#define INT_UART2DM_RX (32 + 21)
#define INT_VDC_MEC (32 + 22)
#define INT_VDC_DB (32 + 23)
#define INT_VDC_AXI (32 + 24)
#define INT_VFE (32 + 25)
#define INT_USB_HS (32 + 26)
#define INT_AUDIO_OUT0 (32 + 27)
#define INT_AUDIO_OUT1 (32 + 28)
#define INT_CRYPTO (32 + 29)
#define INT_AD6M_IDLE (32 + 30)
#define INT_SIRC_1 (32 + 31)
#define NR_GPIO_IRQS 165
#define NR_MSM_IRQS 64
#define NR_BOARD_IRQS 64
#endif

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/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
#define __ASM_ARCH_MSM_IRQS_8X60_H
/* MSM ACPU Interrupt Numbers */
/* 0-15: STI/SGI (software triggered/generated interrupts)
* 16-31: PPI (private peripheral interrupts)
* 32+: SPI (shared peripheral interrupts)
*/
#define GIC_PPI_START 16
#define GIC_SPI_START 32
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2)
#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3)
#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
#define AVS_SVICINT (GIC_PPI_START + 5)
#define AVS_SVICINTSWDONE (GIC_PPI_START + 6)
#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7)
#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8)
#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9)
#define SC_AVSCPUXDOWN (GIC_PPI_START + 10)
#define SC_AVSCPUXUP (GIC_PPI_START + 11)
#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12)
/* PPI 13 to 15 are unused */
#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2)
#define NC (GIC_SPI_START + 3)
#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
#define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
#define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
#define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
#define PM8058_SEC_IRQ_N (GIC_SPI_START + 14)
#define PM8901_SEC_IRQ_N (GIC_SPI_START + 15)
#define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16)
#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
#define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
#define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
#define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
#define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
#define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
#define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
#define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27)
#define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28)
#define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29)
#define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30)
#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
#define MARM_FIQ (GIC_SPI_START + 33)
#define MARM_IRQ (GIC_SPI_START + 34)
#define MARM_L2CC_IRQ (GIC_SPI_START + 35)
#define MARM_WDOG_EXPIRED (GIC_SPI_START + 36)
#define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37)
#define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38)
#define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39)
#define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40)
#define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41)
#define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42)
#define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43)
#define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44)
#define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45)
#define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46)
#define VPE_IRQ (GIC_SPI_START + 47)
#define VFE_IRQ (GIC_SPI_START + 48)
#define VCODEC_IRQ (GIC_SPI_START + 49)
#define TV_ENC_IRQ (GIC_SPI_START + 50)
#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
#define ROT_IRQ (GIC_SPI_START + 73)
#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
#define MDP_IRQ (GIC_SPI_START + 75)
#define JPEGD_IRQ (GIC_SPI_START + 76)
#define JPEG_IRQ (GIC_SPI_START + 77)
#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
#define HDMI_IRQ (GIC_SPI_START + 79)
#define GFX3D_IRQ (GIC_SPI_START + 80)
#define GFX2D0_IRQ (GIC_SPI_START + 81)
#define DSI_IRQ (GIC_SPI_START + 82)
#define CSI_1_IRQ (GIC_SPI_START + 83)
#define CSI_0_IRQ (GIC_SPI_START + 84)
#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
#define USB1_HS_IRQ (GIC_SPI_START + 100)
#define SDC4_IRQ_0 (GIC_SPI_START + 101)
#define SDC3_IRQ_0 (GIC_SPI_START + 102)
#define SDC2_IRQ_0 (GIC_SPI_START + 103)
#define SDC1_IRQ_0 (GIC_SPI_START + 104)
#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
#define SPS_MTI_0 (GIC_SPI_START + 107)
#define SPS_MTI_1 (GIC_SPI_START + 108)
#define SPS_MTI_2 (GIC_SPI_START + 109)
#define SPS_MTI_3 (GIC_SPI_START + 110)
#define SPS_MTI_4 (GIC_SPI_START + 111)
#define SPS_MTI_5 (GIC_SPI_START + 112)
#define SPS_MTI_6 (GIC_SPI_START + 113)
#define SPS_MTI_7 (GIC_SPI_START + 114)
#define SPS_MTI_8 (GIC_SPI_START + 115)
#define SPS_MTI_9 (GIC_SPI_START + 116)
#define SPS_MTI_10 (GIC_SPI_START + 117)
#define SPS_MTI_11 (GIC_SPI_START + 118)
#define SPS_MTI_12 (GIC_SPI_START + 119)
#define SPS_MTI_13 (GIC_SPI_START + 120)
#define SPS_MTI_14 (GIC_SPI_START + 121)
#define SPS_MTI_15 (GIC_SPI_START + 122)
#define SPS_MTI_16 (GIC_SPI_START + 123)
#define SPS_MTI_17 (GIC_SPI_START + 124)
#define SPS_MTI_18 (GIC_SPI_START + 125)
#define SPS_MTI_19 (GIC_SPI_START + 126)
#define SPS_MTI_20 (GIC_SPI_START + 127)
#define SPS_MTI_21 (GIC_SPI_START + 128)
#define SPS_MTI_22 (GIC_SPI_START + 129)
#define SPS_MTI_23 (GIC_SPI_START + 130)
#define SPS_MTI_24 (GIC_SPI_START + 131)
#define SPS_MTI_25 (GIC_SPI_START + 132)
#define SPS_MTI_26 (GIC_SPI_START + 133)
#define SPS_MTI_27 (GIC_SPI_START + 134)
#define SPS_MTI_28 (GIC_SPI_START + 135)
#define SPS_MTI_29 (GIC_SPI_START + 136)
#define SPS_MTI_30 (GIC_SPI_START + 137)
#define SPS_MTI_31 (GIC_SPI_START + 138)
#define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139)
#define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140)
#define USB2_IRQ (GIC_SPI_START + 141)
#define USB1_IRQ (GIC_SPI_START + 142)
#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
#define INT_UART1DM_IRQ (GIC_SPI_START + 146)
#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
#define INT_UART2DM_IRQ (GIC_SPI_START + 148)
#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
#define INT_UART3DM_IRQ (GIC_SPI_START + 150)
#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
#define INT_UART4DM_IRQ (GIC_SPI_START + 152)
#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
#define INT_UART5DM_IRQ (GIC_SPI_START + 154)
#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
#define INT_UART6DM_IRQ (GIC_SPI_START + 156)
#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
#define INT_UART7DM_IRQ (GIC_SPI_START + 158)
#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
#define INT_UART8DM_IRQ (GIC_SPI_START + 160)
#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
#define TSIF2_IRQ (GIC_SPI_START + 164)
#define TSIF1_IRQ (GIC_SPI_START + 165)
#define INT_ADM1_MASTER (GIC_SPI_START + 166)
#define INT_ADM1_AARM (GIC_SPI_START + 167)
#define INT_ADM1_SD2 (GIC_SPI_START + 168)
#define INT_ADM1_SD3 (GIC_SPI_START + 169)
#define INT_ADM0_MASTER (GIC_SPI_START + 170)
#define INT_ADM0_AARM (GIC_SPI_START + 171)
#define INT_ADM0_SD2 (GIC_SPI_START + 172)
#define INT_ADM0_SD3 (GIC_SPI_START + 173)
#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
#define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185)
#define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186)
#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
#define SDC5_IRQ_0 (GIC_SPI_START + 188)
#define INT_UART9DM_IRQ (GIC_SPI_START + 189)
#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
#define INT_UART10DM_IRQ (GIC_SPI_START + 191)
#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
#define INT_UART11DM_IRQ (GIC_SPI_START + 193)
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
/*SPI 197 to 209 arent used in 8x60*/
#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
/*SPI 212 to 216 arent used in 8x60*/
#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
#define SMPSS_SPARE_4 (GIC_SPI_START + 220)
#define SMPSS_SPARE_5 (GIC_SPI_START + 221)
#define SMPSS_SPARE_6 (GIC_SPI_START + 222)
#define SMPSS_SPARE_7 (GIC_SPI_START + 223)
#define NR_GPIO_IRQS 173
#define NR_MSM_IRQS 256
#define NR_BOARD_IRQS 0
#endif

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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_IRQS_H
#define __ASM_ARCH_MSM_IRQS_H
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#if defined(CONFIG_ARCH_MSM7X30)
#include "irqs-7x30.h"
#elif defined(CONFIG_ARCH_QSD8X50)
#include "irqs-8x50.h"
#include "sirc.h"
#elif defined(CONFIG_ARCH_MSM8X60)
#include "irqs-8x60.h"
#elif defined(CONFIG_ARCH_MSM8960)
/* TODO: Make these not generic. */
#include "irqs-8960.h"
#elif defined(CONFIG_ARCH_MSM_ARM11)
#include "irqs-7x00.h"
#else
#error "Unknown architecture specification"
#endif
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
#endif

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/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _LINUX_MSM_GPIOMUX_H
#define _LINUX_MSM_GPIOMUX_H
#ifdef CONFIG_MSM_GPIOMUX
/* Increment a gpio's reference count, possibly activating the line. */
int __must_check msm_gpiomux_get(unsigned gpio);
/* Decrement a gpio's reference count, possibly suspending the line. */
int msm_gpiomux_put(unsigned gpio);
#else
static inline int __must_check msm_gpiomux_get(unsigned gpio)
{
return -ENOSYS;
}
static inline int msm_gpiomux_put(unsigned gpio)
{
return -ENOSYS;
}
#endif
#endif /* _LINUX_MSM_GPIOMUX_H */

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/* arch/arm/mach-msm/include/mach/msm_iomap.h
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
#define __ASM_ARCH_MSM_IOMAP_7X00_H
#include <asm/sizes.h>
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xC0000000
#define MSM_VIC_SIZE SZ_4K
#define MSM7X00_CSR_PHYS 0xC0100000
#define MSM7X00_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000
#define MSM_DMOV_SIZE SZ_4K
#define MSM7X00_GPIO1_PHYS 0xA9200000
#define MSM7X00_GPIO1_SIZE SZ_4K
#define MSM7X00_GPIO2_PHYS 0xA9300000
#define MSM7X00_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xA8600000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS 0x01F00000
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xA9A00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xA9B00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_SDC1_PHYS 0xA0400000
#define MSM_SDC1_SIZE SZ_4K
#define MSM_SDC2_PHYS 0xA0500000
#define MSM_SDC2_SIZE SZ_4K
#define MSM_SDC3_PHYS 0xA0600000
#define MSM_SDC3_SIZE SZ_4K
#define MSM_SDC4_PHYS 0xA0700000
#define MSM_SDC4_SIZE SZ_4K
#define MSM_I2C_PHYS 0xA9900000
#define MSM_I2C_SIZE SZ_4K
#define MSM_HSUSB_PHYS 0xA0800000
#define MSM_HSUSB_SIZE SZ_4K
#define MSM_PMDH_PHYS 0xAA600000
#define MSM_PMDH_SIZE SZ_4K
#define MSM_EMDH_PHYS 0xAA700000
#define MSM_EMDH_SIZE SZ_4K
#define MSM_MDP_PHYS 0xAA200000
#define MSM_MDP_SIZE 0x000F0000
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_PHYS 0xAC000000
#define MSM_AD5_SIZE (SZ_1M*13)
#endif

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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
#define __ASM_ARCH_MSM_IOMAP_7X30_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xC0080000
#define MSM_VIC_SIZE SZ_4K
#define MSM7X30_CSR_PHYS 0xC0100000
#define MSM7X30_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xAC400000
#define MSM_DMOV_SIZE SZ_4K
#define MSM7X30_GPIO1_PHYS 0xAC001000
#define MSM7X30_GPIO1_SIZE SZ_4K
#define MSM7X30_GPIO2_PHYS 0xAC101000
#define MSM7X30_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xAB800000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
#define MSM_CLK_CTL_SH2_SIZE SZ_4K
#define MSM_ACC_BASE IOMEM(0xE0007000)
#define MSM_ACC_PHYS 0xC0101000
#define MSM_ACC_SIZE SZ_4K
#define MSM_SAW_BASE IOMEM(0xE0008000)
#define MSM_SAW_PHYS 0xC0102000
#define MSM_SAW_SIZE SZ_4K
#define MSM_GCC_BASE IOMEM(0xE0009000)
#define MSM_GCC_PHYS 0xC0182000
#define MSM_GCC_SIZE SZ_4K
#define MSM_TCSR_BASE IOMEM(0xE000A000)
#define MSM_TCSR_PHYS 0xAB600000
#define MSM_TCSR_SIZE SZ_4K
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS 0x00100000
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xACA00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xACB00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xACC00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_BASE IOMEM(0xE0300000)
#define MSM_AD5_PHYS 0xA7000000
#define MSM_AD5_SIZE (SZ_1M*13)
#define MSM_HSUSB_PHYS 0xA3600000
#define MSM_HSUSB_SIZE SZ_1K
#endif

53
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
#define __ASM_ARCH_MSM_IOMAP_8960_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM8960_QGIC_DIST_PHYS 0x02000000
#define MSM8960_QGIC_DIST_SIZE SZ_4K
#define MSM8960_QGIC_CPU_PHYS 0x02002000
#define MSM8960_QGIC_CPU_SIZE SZ_4K
#define MSM8960_TMR_PHYS 0x0200A000
#define MSM8960_TMR_SIZE SZ_4K
#define MSM8960_TMR0_PHYS 0x0208A000
#define MSM8960_TMR0_SIZE SZ_4K
#ifdef CONFIG_DEBUG_MSM8960_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x16440000
#endif
#endif

125
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
#define __ASM_ARCH_MSM_IOMAP_8X50_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xAC000000
#define MSM_VIC_SIZE SZ_4K
#define QSD8X50_CSR_PHYS 0xAC100000
#define QSD8X50_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000
#define MSM_DMOV_SIZE SZ_4K
#define QSD8X50_GPIO1_PHYS 0xA9000000
#define QSD8X50_GPIO1_SIZE SZ_4K
#define QSD8X50_GPIO2_PHYS 0xA9100000
#define QSD8X50_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xA8600000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_SIRC_BASE IOMEM(0xE1006000)
#define MSM_SIRC_PHYS 0xAC200000
#define MSM_SIRC_SIZE SZ_4K
#define MSM_SCPLL_BASE IOMEM(0xE1007000)
#define MSM_SCPLL_PHYS 0xA8800000
#define MSM_SCPLL_SIZE SZ_4K
#ifdef CONFIG_MSM_SOC_REV_A
#define MSM_SMI_BASE 0xE0000000
#else
#define MSM_SMI_BASE 0x00000000
#endif
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xA9A00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xA9B00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_BASE IOMEM(0xE0300000)
#define MSM_AD5_PHYS 0xAC000000
#define MSM_AD5_SIZE (SZ_1M*13)
#define MSM_I2C_SIZE SZ_4K
#define MSM_I2C_PHYS 0xA9900000
#define MSM_HSUSB_PHYS 0xA0800000
#define MSM_HSUSB_SIZE SZ_1K
#define MSM_NAND_PHYS 0xA0A00000
#define MSM_TSIF_PHYS (0xa0100000)
#define MSM_TSIF_SIZE (0x200)
#define MSM_TSSC_PHYS 0xAA300000
#define MSM_UART1DM_PHYS 0xA0200000
#define MSM_UART2DM_PHYS 0xA0900000
#define MSM_SDC1_PHYS 0xA0300000
#define MSM_SDC1_SIZE SZ_4K
#define MSM_SDC2_PHYS 0xA0400000
#define MSM_SDC2_SIZE SZ_4K
#define MSM_SDC3_PHYS 0xA0500000
#define MSM_SDC3_SIZE SZ_4K
#define MSM_SDC4_PHYS 0xA0600000
#define MSM_SDC4_SIZE SZ_4K
#endif

59
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
#define __ASM_ARCH_MSM_IOMAP_8X60_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM8X60_QGIC_DIST_PHYS 0x02080000
#define MSM8X60_QGIC_DIST_SIZE SZ_4K
#define MSM8X60_QGIC_CPU_PHYS 0x02081000
#define MSM8X60_QGIC_CPU_SIZE SZ_4K
#define MSM_TLMM_BASE IOMEM(0xF0004000)
#define MSM_TLMM_PHYS 0x00800000
#define MSM_TLMM_SIZE SZ_16K
#define MSM8X60_TMR_PHYS 0x02000000
#define MSM8X60_TMR_SIZE SZ_4K
#define MSM8X60_TMR0_PHYS 0x02040000
#define MSM8X60_TMR0_SIZE SZ_4K
#ifdef CONFIG_DEBUG_MSM8660_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x19C40000
#endif
#endif

72
arch/arm/mach-msm/include/mach/msm_iomap.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_H
#define __ASM_ARCH_MSM_IOMAP_H
#include <asm/sizes.h>
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#if defined(CONFIG_ARCH_MSM7X30)
#include "msm_iomap-7x30.h"
#elif defined(CONFIG_ARCH_QSD8X50)
#include "msm_iomap-8x50.h"
#else
#include "msm_iomap-7x00.h"
#endif
#include "msm_iomap-8x60.h"
#include "msm_iomap-8960.h"
#define MSM_DEBUG_UART_SIZE SZ_4K
#if defined(CONFIG_DEBUG_MSM_UART1)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART2)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART3)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
#endif
/* Virtual addresses shared across all MSM targets. */
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
#define MSM_TMR_BASE IOMEM(0xF0200000)
#define MSM_TMR0_BASE IOMEM(0xF0201000)
#define MSM_GPIO1_BASE IOMEM(0xE0003000)
#define MSM_GPIO2_BASE IOMEM(0xE0004000)
#endif

109
arch/arm/mach-msm/include/mach/msm_smd.h Normal file
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/* linux/include/asm-arm/arch-msm/msm_smd.h
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_SMD_H
#define __ASM_ARCH_MSM_SMD_H
typedef struct smd_channel smd_channel_t;
extern int (*msm_check_for_modem_crash)(void);
/* warning: notify() may be called before open returns */
int smd_open(const char *name, smd_channel_t **ch, void *priv,
void (*notify)(void *priv, unsigned event));
#define SMD_EVENT_DATA 1
#define SMD_EVENT_OPEN 2
#define SMD_EVENT_CLOSE 3
int smd_close(smd_channel_t *ch);
/* passing a null pointer for data reads and discards */
int smd_read(smd_channel_t *ch, void *data, int len);
/* Write to stream channels may do a partial write and return
** the length actually written.
** Write to packet channels will never do a partial write --
** it will return the requested length written or an error.
*/
int smd_write(smd_channel_t *ch, const void *data, int len);
int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
int smd_write_avail(smd_channel_t *ch);
int smd_read_avail(smd_channel_t *ch);
/* Returns the total size of the current packet being read.
** Returns 0 if no packets available or a stream channel.
*/
int smd_cur_packet_size(smd_channel_t *ch);
/* used for tty unthrottling and the like -- causes the notify()
** callback to be called from the same lock context as is used
** when it is called from channel updates
*/
void smd_kick(smd_channel_t *ch);
#if 0
/* these are interruptable waits which will block you until the specified
** number of bytes are readable or writable.
*/
int smd_wait_until_readable(smd_channel_t *ch, int bytes);
int smd_wait_until_writable(smd_channel_t *ch, int bytes);
#endif
typedef enum {
SMD_PORT_DS = 0,
SMD_PORT_DIAG,
SMD_PORT_RPC_CALL,
SMD_PORT_RPC_REPLY,
SMD_PORT_BT,
SMD_PORT_CONTROL,
SMD_PORT_MEMCPY_SPARE1,
SMD_PORT_DATA1,
SMD_PORT_DATA2,
SMD_PORT_DATA3,
SMD_PORT_DATA4,
SMD_PORT_DATA5,
SMD_PORT_DATA6,
SMD_PORT_DATA7,
SMD_PORT_DATA8,
SMD_PORT_DATA9,
SMD_PORT_DATA10,
SMD_PORT_DATA11,
SMD_PORT_DATA12,
SMD_PORT_DATA13,
SMD_PORT_DATA14,
SMD_PORT_DATA15,
SMD_PORT_DATA16,
SMD_PORT_DATA17,
SMD_PORT_DATA18,
SMD_PORT_DATA19,
SMD_PORT_DATA20,
SMD_PORT_GPS_NMEA,
SMD_PORT_BRIDGE_1,
SMD_PORT_BRIDGE_2,
SMD_PORT_BRIDGE_3,
SMD_PORT_BRIDGE_4,
SMD_PORT_BRIDGE_5,
SMD_PORT_LOOPBACK,
SMD_PORT_CS_APPS_MODEM,
SMD_PORT_CS_APPS_DSP,
SMD_PORT_CS_MODEM_DSP,
SMD_NUM_PORTS,
} smd_port_id_type;
#endif

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arch/arm/mach-msm/include/mach/sirc.h Normal file
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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_SIRC_H
#define __ASM_ARCH_MSM_SIRC_H
struct sirc_regs_t {
void *int_enable;
void *int_enable_clear;
void *int_enable_set;
void *int_type;
void *int_polarity;
void *int_clear;
};
struct sirc_cascade_regs {
void *int_status;
unsigned int cascade_irq;
};
void msm_init_sirc(void);
void msm_sirc_enter_sleep(void);
void msm_sirc_exit_sleep(void);
#if defined(CONFIG_ARCH_MSM_SCORPION)
#include <mach/msm_iomap.h>
/*
* Secondary interrupt controller interrupts
*/
#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
#define INT_UART1 (FIRST_SIRC_IRQ + 0)
#define INT_UART2 (FIRST_SIRC_IRQ + 1)
#define INT_UART3 (FIRST_SIRC_IRQ + 2)
#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
#if defined(CONFIG_MSM_SOC_REV_A)
#define NR_SIRC_IRQS 28
#define SIRC_MASK 0x0FFFFFFF
#else
#define NR_SIRC_IRQS 23
#define SIRC_MASK 0x007FFFFF
#endif
#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
#endif
#endif

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arch/arm/mach-msm/include/mach/timex.h Normal file
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/* arch/arm/mach-msm/include/mach/timex.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_TIMEX_H
#define __ASM_ARCH_MSM_TIMEX_H
#define CLOCK_TICK_RATE 1000000
#endif

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arch/arm/mach-msm/include/mach/uncompress.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
#define __ASM_ARCH_MSM_UNCOMPRESS_H
#include <asm/barrier.h>
#include <asm/processor.h>
#include <mach/msm_iomap.h>
#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
static void putc(int c)
{
#if defined(MSM_DEBUG_UART_PHYS)
#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
/*
* Wait for TX_READY to be set; but skip it if we have a
* TX underrun.
*/
if (!(UART_DM_SR & 0x08))
while (!(UART_DM_ISR & 0x80))
cpu_relax();
UART_DM_CR = 0x300;
UART_DM_NCHAR = 0x1;
UART_DM_TF = c;
#else
while (!(UART_CSR & 0x04))
cpu_relax();
UART_TF = c;
#endif
#endif
}
static inline void flush(void)
{
}
static inline void arch_decomp_setup(void)
{
}
#endif

29
arch/arm/mach-msm/include/mach/vreg.h Normal file
View File

@@ -0,0 +1,29 @@
/* linux/include/asm-arm/arch-msm/vreg.h
*
* Copyright (C) 2008 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_VREG_H
#define __ARCH_ARM_MACH_MSM_VREG_H
struct vreg;
struct vreg *vreg_get(struct device *dev, const char *id);
void vreg_put(struct vreg *vreg);
int vreg_enable(struct vreg *vreg);
int vreg_disable(struct vreg *vreg);
int vreg_set_level(struct vreg *vreg, unsigned mv);
#endif