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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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26
arch/arm/mach-exynos/include/mach/dma.h Normal file
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common DMA API driver for PL330 */
#include <plat/dma-pl330.h>
#endif /* __MACH_DMA_H */

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arch/arm/mach-exynos/include/mach/gpio.h Normal file
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/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
/* Macro for EXYNOS GPIO numbering */
#define EXYNOS_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
/* EXYNOS4 GPIO bank sizes */
#define EXYNOS4_GPIO_A0_NR (8)
#define EXYNOS4_GPIO_A1_NR (6)
#define EXYNOS4_GPIO_B_NR (8)
#define EXYNOS4_GPIO_C0_NR (5)
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
#define EXYNOS4_GPIO_E0_NR (5)
#define EXYNOS4_GPIO_E1_NR (8)
#define EXYNOS4_GPIO_E2_NR (6)
#define EXYNOS4_GPIO_E3_NR (8)
#define EXYNOS4_GPIO_E4_NR (8)
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
#define EXYNOS4_GPIO_F3_NR (6)
#define EXYNOS4_GPIO_J0_NR (8)
#define EXYNOS4_GPIO_J1_NR (5)
#define EXYNOS4_GPIO_K0_NR (7)
#define EXYNOS4_GPIO_K1_NR (7)
#define EXYNOS4_GPIO_K2_NR (7)
#define EXYNOS4_GPIO_K3_NR (7)
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
#define EXYNOS4_GPIO_X3_NR (8)
#define EXYNOS4_GPIO_Y0_NR (6)
#define EXYNOS4_GPIO_Y1_NR (4)
#define EXYNOS4_GPIO_Y2_NR (6)
#define EXYNOS4_GPIO_Y3_NR (8)
#define EXYNOS4_GPIO_Y4_NR (8)
#define EXYNOS4_GPIO_Y5_NR (8)
#define EXYNOS4_GPIO_Y6_NR (8)
#define EXYNOS4_GPIO_Z_NR (7)
/* EXYNOS4 GPIO bank numbers */
enum exynos4_gpio_number {
EXYNOS4_GPIO_A0_START = 0,
EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
};
/* EXYNOS4 GPIO number definitions */
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
/* the end of the EXYNOS4 specific gpios */
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
/* EXYNOS5 GPIO bank sizes */
#define EXYNOS5_GPIO_A0_NR (8)
#define EXYNOS5_GPIO_A1_NR (6)
#define EXYNOS5_GPIO_A2_NR (8)
#define EXYNOS5_GPIO_B0_NR (5)
#define EXYNOS5_GPIO_B1_NR (5)
#define EXYNOS5_GPIO_B2_NR (4)
#define EXYNOS5_GPIO_B3_NR (4)
#define EXYNOS5_GPIO_C0_NR (7)
#define EXYNOS5_GPIO_C1_NR (4)
#define EXYNOS5_GPIO_C2_NR (7)
#define EXYNOS5_GPIO_C3_NR (7)
#define EXYNOS5_GPIO_C4_NR (7)
#define EXYNOS5_GPIO_D0_NR (4)
#define EXYNOS5_GPIO_D1_NR (8)
#define EXYNOS5_GPIO_Y0_NR (6)
#define EXYNOS5_GPIO_Y1_NR (4)
#define EXYNOS5_GPIO_Y2_NR (6)
#define EXYNOS5_GPIO_Y3_NR (8)
#define EXYNOS5_GPIO_Y4_NR (8)
#define EXYNOS5_GPIO_Y5_NR (8)
#define EXYNOS5_GPIO_Y6_NR (8)
#define EXYNOS5_GPIO_X0_NR (8)
#define EXYNOS5_GPIO_X1_NR (8)
#define EXYNOS5_GPIO_X2_NR (8)
#define EXYNOS5_GPIO_X3_NR (8)
#define EXYNOS5_GPIO_E0_NR (8)
#define EXYNOS5_GPIO_E1_NR (2)
#define EXYNOS5_GPIO_F0_NR (4)
#define EXYNOS5_GPIO_F1_NR (4)
#define EXYNOS5_GPIO_G0_NR (8)
#define EXYNOS5_GPIO_G1_NR (8)
#define EXYNOS5_GPIO_G2_NR (2)
#define EXYNOS5_GPIO_H0_NR (4)
#define EXYNOS5_GPIO_H1_NR (8)
#define EXYNOS5_GPIO_V0_NR (8)
#define EXYNOS5_GPIO_V1_NR (8)
#define EXYNOS5_GPIO_V2_NR (8)
#define EXYNOS5_GPIO_V3_NR (8)
#define EXYNOS5_GPIO_V4_NR (2)
#define EXYNOS5_GPIO_Z_NR (7)
/* EXYNOS5 GPIO bank numbers */
enum exynos5_gpio_number {
EXYNOS5_GPIO_A0_START = 0,
EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
};
/* EXYNOS5 GPIO number definitions */
#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
/* the end of the EXYNOS5 specific gpios */
#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
#define S3C_GPIO_END (EXYNOS5_GPIO_END)
/* define the number of gpios */
#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
#endif /* __ASM_ARCH_GPIO_H */

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arch/arm/mach-exynos/include/mach/hardware.h Normal file
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/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/mach-exynos/include/mach/irqs.h Normal file
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/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
/* PPI: Private Peripheral Interrupt */
#define IRQ_PPI(x) (x + 16)
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) (x + 32)
/* COMBINER */
#define MAX_IRQ_IN_COMBINER 8
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
/* For EXYNOS4 and EXYNOS5 */
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
/* For EXYNOS4 SoCs */
#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
#define EXYNOS4_IRQ_2D IRQ_SPI(89)
#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
#define EXYNOS4210_MAX_COMBINER_NR 16
#define EXYNOS4212_MAX_COMBINER_NR 18
#define EXYNOS4412_MAX_COMBINER_NR 20
#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
/*
* For Compatibility:
* the default is for EXYNOS4, and
* for exynos5, should be re-mapped at function
*/
#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
#define IRQ_WDT EXYNOS4_IRQ_WDT
#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
#define IRQ_IIC EXYNOS4_IRQ_IIC
#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
#define IRQ_JPEG EXYNOS4_IRQ_JPEG
#define IRQ_2D EXYNOS4_IRQ_2D
#define IRQ_MIXER EXYNOS4_IRQ_MIXER
#define IRQ_HDMI EXYNOS4_IRQ_HDMI
#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
#define IRQ_MFC EXYNOS4_IRQ_MFC
#define IRQ_SDO EXYNOS4_IRQ_SDO
#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
#define IRQ_ADC EXYNOS4_IRQ_ADC0
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
/* For EXYNOS5 SoCs */
#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
#define EXYNOS5_IRQ_2D IRQ_SPI(91)
#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
/* EXYNOS5440 */
#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
#define EXYNOS5_MAX_COMBINER_NR 32
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
/* Set the default NR_IRQS */
#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
#ifndef CONFIG_SPARSE_IRQ
#define NR_IRQS EXYNOS_NR_IRQS
#endif
#endif /* __ASM_ARCH_IRQS_H */

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/* linux/arch/arm/mach-exynos/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/*
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
* So need to define it, and here is to avoid redefinition warning.
*/
#define S3C_UART_OFFSET (0x10000)
#include <plat/map-s5p.h>
#define EXYNOS4_PA_SYSRAM0 0x02025000
#define EXYNOS4_PA_SYSRAM1 0x02020000
#define EXYNOS5_PA_SYSRAM 0x02020000
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
#define EXYNOS4_PA_FIMC0 0x11800000
#define EXYNOS4_PA_FIMC1 0x11810000
#define EXYNOS4_PA_FIMC2 0x11820000
#define EXYNOS4_PA_FIMC3 0x11830000
#define EXYNOS4_PA_JPEG 0x11840000
/* x = 0...1 */
#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
#define EXYNOS4_PA_G2D 0x12800000
#define EXYNOS4_PA_I2S0 0x03830000
#define EXYNOS4_PA_I2S1 0xE3100000
#define EXYNOS4_PA_I2S2 0xE2A00000
#define EXYNOS4_PA_PCM0 0x03840000
#define EXYNOS4_PA_PCM1 0x13980000
#define EXYNOS4_PA_PCM2 0x13990000
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
#define EXYNOS4_PA_ONENAND 0x0C000000
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
#define EXYNOS_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
#define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS5_PA_PMU 0x10040000
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000
#define EXYNOS4_PA_SYSTIMER 0x10050000
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS5_PA_WATCHDOG 0x101D0000
#define EXYNOS4_PA_RTC 0x10070000
#define EXYNOS4_PA_KEYPAD 0x100A0000
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_DMC1 0x10410000
#define EXYNOS4_PA_COMBINER 0x10440000
#define EXYNOS5_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10482000
#define EXYNOS5_PA_GIC_DIST 0x10481000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_TMU 0x100C0000
#define EXYNOS4_PA_MDMA0 0x10810000
#define EXYNOS4_PA_MDMA1 0x12850000
#define EXYNOS4_PA_S_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
#define EXYNOS5_PA_MDMA0 0x10800000
#define EXYNOS5_PA_MDMA1 0x11C10000
#define EXYNOS5_PA_PDMA0 0x121A0000
#define EXYNOS5_PA_PDMA1 0x121B0000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
#define EXYNOS5_PA_GSC0 0x13E00000
#define EXYNOS5_PA_GSC1 0x13E10000
#define EXYNOS5_PA_GSC2 0x13E20000
#define EXYNOS5_PA_GSC3 0x13E30000
#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
#define EXYNOS5_PA_SYSMMU_TV 0x14650000
#define EXYNOS4_PA_SPI0 0x13920000
#define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000
#define EXYNOS5_PA_SPI0 0x12D20000
#define EXYNOS5_PA_SPI1 0x12D30000
#define EXYNOS5_PA_SPI2 0x12D40000
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
#define EXYNOS4_PA_GPIO3 0x03860000
#define EXYNOS5_PA_GPIO1 0x11400000
#define EXYNOS5_PA_GPIO2 0x13400000
#define EXYNOS5_PA_GPIO3 0x10D10000
#define EXYNOS5_PA_GPIO4 0x03860000
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
#define EXYNOS5_PA_DWMCI0 0x12200000
#define EXYNOS5_PA_DWMCI1 0x12210000
#define EXYNOS5_PA_DWMCI2 0x12220000
#define EXYNOS5_PA_DWMCI3 0x12230000
#define EXYNOS4_PA_HSOTG 0x12480000
#define EXYNOS4_PA_USB_HSPHY 0x125B0000
#define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
#define EXYNOS4_PA_SROMC 0x12570000
#define EXYNOS5_PA_SROMC 0x12250000
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_OHCI 0x12590000
#define EXYNOS4_PA_HSPHY 0x125B0000
#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
#define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000
#define EXYNOS4_PA_SDO 0x12C20000
#define EXYNOS4_PA_HDMI 0x12D00000
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
#define EXYNOS4_PA_TIMER 0x139D0000
#define EXYNOS5_PA_TIMER 0x12DD0000
#define EXYNOS4_PA_SDRAM 0x40000000
#define EXYNOS5_PA_SDRAM 0x40000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_JPEG EXYNOS4_PA_JPEG
#define S5P_PA_G2D EXYNOS4_PA_G2D
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDO EXYNOS4_PA_SDO
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_VP EXYNOS4_PA_VP
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
/* Compatibility UART */
#define EXYNOS4_PA_UART0 0x13800000
#define EXYNOS4_PA_UART1 0x13810000
#define EXYNOS4_PA_UART2 0x13820000
#define EXYNOS4_PA_UART3 0x13830000
#define EXYNOS4_SZ_UART SZ_256
#define EXYNOS5_PA_UART0 0x12C00000
#define EXYNOS5_PA_UART1 0x12C10000
#define EXYNOS5_PA_UART2 0x12C20000
#define EXYNOS5_PA_UART3 0x12C30000
#define EXYNOS5440_PA_UART0 0x000B0000
#define EXYNOS5440_PA_UART1 0x000C0000
#define EXYNOS5440_SZ_UART SZ_256
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */

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/* linux/arch/arm/mach-exynos4/include/mach/memory.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H __FILE__
#define PLAT_PHYS_OFFSET UL(0x40000000)
/* Maximum of 256MiB in one bank */
#define MAX_PHYSMEM_BITS 32
#define SECTION_SIZE_BITS 28
#endif /* __ASM_ARCH_MEMORY_H */

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/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PM_CORE_H
#define __ASM_ARCH_PM_CORE_H __FILE__
#include <linux/of.h>
#include <mach/regs-pmu.h>
#ifdef CONFIG_PINCTRL_EXYNOS
extern u32 exynos_get_eint_wake_mask(void);
#else
static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
#endif
static inline void s3c_pm_debug_init_uart(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
u32 eintmask = s3c_irqwake_eintmask;
if (of_have_populated_dt())
eintmask = exynos_get_eint_wake_mask();
__raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
__raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_show_resume_irqs(void)
{
/* nothing here yet */
}
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
/* nothing here yet */
}
static inline void s3c_pm_restored_gpios(void)
{
/* nothing here yet */
}
static inline void samsung_pm_saved_gpios(void)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_PM_CORE_H */

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/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <plat/cpu.h>
#include <mach/map.h>
#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x0C930) : \
EXYNOS_CLKREG(0x04930))
#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x0C960) : \
EXYNOS_CLKREG(0x08960))
#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x14004) : \
EXYNOS_CLKREG(0x10008))
#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x14108) : \
EXYNOS_CLKREG(0x10108))
#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x1410C) : \
EXYNOS_CLKREG(0x1010C))
#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
/* Only for EXYNOS4210 */
#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
/* Only for EXYNOS4212 */
#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
/* For EXYNOS5250 */
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
#endif /* __ASM_ARCH_REGS_CLOCK_H */

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/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - GPIO (including EINT) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
#include <mach/irqs.h>
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
/* compatibility for plat-s5p/irq-pm.c */
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
#endif /* __ASM_ARCH_REGS_GPIO_H */

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/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <linux/irqchip/arm-gic.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_REGS_IRQ_H */

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/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - Power management unit definition
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_PMU_H
#define __ASM_ARCH_REGS_PMU_H __FILE__
#include <mach/map.h>
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFI1 (1 << 17)
#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define S5P_USE_STANDBY_WFE1 (1 << 25)
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
#define S5P_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
#define S5P_HDMI_PHY_ENABLE (1 << 0)
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
#define S5P_DAC_PHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
#define S5P_INFORM0 S5P_PMUREG(0x0800)
#define S5P_INFORM1 S5P_PMUREG(0x0804)
#define S5P_INFORM2 S5P_PMUREG(0x0808)
#define S5P_INFORM3 S5P_PMUREG(0x080C)
#define S5P_INFORM4 S5P_PMUREG(0x0810)
#define S5P_INFORM5 S5P_PMUREG(0x0814)
#define S5P_INFORM6 S5P_PMUREG(0x0818)
#define S5P_INFORM7 S5P_PMUREG(0x081C)
#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD
/* Only for EXYNOS4210 */
#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704)
#define S5P_USBDEVICE_PHY_ENABLE (1 << 0)
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
/* Only for EXYNOS4x12 */
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
/* Only for EXYNOS4412 */
#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
/* For EXYNOS5 */
#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
#define EXYNOS5_SYS_WDTRESET (1 << 20)
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
#endif /* __ASM_ARCH_REGS_PMU_H */

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arch/arm/mach-exynos/include/mach/regs-usb-phy.h Normal file
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/*
* Copyright (C) 2011 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PLAT_S5P_REGS_USB_PHY_H
#define __PLAT_S5P_REGS_USB_PHY_H
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
#define PHY1_HSIC1_SLEEP (1 << 12)
#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
#define PHY1_HSIC0_SLEEP (1 << 10)
#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
#define PHY1_STD_NORMAL_MASK (0x7 << 6)
#define PHY1_STD_SLEEP (1 << 8)
#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
#define PHY1_STD_FORCE_SUSPEND (1 << 6)
#define PHY0_NORMAL_MASK (0x39 << 0)
#define PHY0_SLEEP (1 << 5)
#define PHY0_OTG_DISABLE (1 << 4)
#define PHY0_ANALOG_POWERDOWN (1 << 3)
#define PHY0_FORCE_SUSPEND (1 << 0)
#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
#define PHY1_COMMON_ON_N (1 << 7)
#define PHY0_COMMON_ON_N (1 << 4)
#define PHY0_ID_PULLUP (1 << 2)
#define EXYNOS4_CLKSEL_SHIFT (0)
#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
#define HOST_LINK_PORT2_SWRST (1 << 9)
#define HOST_LINK_PORT1_SWRST (1 << 8)
#define HOST_LINK_PORT0_SWRST (1 << 7)
#define HOST_LINK_ALL_SWRST (1 << 6)
#define PHY1_SWRST_MASK (0x7 << 3)
#define PHY1_HSIC_SWRST (1 << 5)
#define PHY1_STD_SWRST (1 << 4)
#define PHY1_ALL_SWRST (1 << 3)
#define PHY0_SWRST_MASK (0x7 << 0)
#define PHY0_PHYLINK_SWRST (1 << 2)
#define PHY0_HLINK_SWRST (1 << 1)
#define PHY0_SWRST (1 << 0)
#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
#define FPENABLEN (1 << 0)
#endif /* __PLAT_S5P_REGS_USB_PHY_H */

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arch/arm/mach-exynos/include/mach/timex.h Normal file
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/* linux/arch/arm/mach-exynos4/include/mach/timex.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2003-2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Based on arch/arm/mach-s5p6442/include/mach/timex.h
*
* EXYNOS4 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H __FILE__
/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
* a variable is useless. It seems as long as we make our timers an
* exact multiple of HZ, any value that makes a 1->1 correspondence
* for the time conversion functions to/from jiffies is acceptable.
*/
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */

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arch/arm/mach-exynos/include/mach/uncompress.h Normal file
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/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H __FILE__
#include <asm/mach-types.h>
#include <mach/map.h>
volatile u8 *uart_base;
#include <plat/uncompress.h>
static unsigned int __raw_readl(unsigned int ptr)
{
return *((volatile unsigned int *)ptr);
}
static void arch_detect_cpu(void)
{
u32 chip_id = __raw_readl(EXYNOS_PA_CHIPID);
/*
* product_id is bits 31:12
* bits 23:20 describe the exynosX family
*
*/
chip_id >>= 20;
chip_id &= 0xf;
if (chip_id == 0x5)
uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
else
uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
/*
* For preventing FIFO overrun or infinite loop of UART console,
* fifo_max should be the minimum fifo size of all of the UART channels
*/
fifo_mask = S5PV210_UFSTAT_TXMASK;
fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */