nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit; kernel source import

Browse Source
This commit is contained in:
Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
45093 changed files with 18199410 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
arch/arm/mach-clps711x/include/mach/autcpu12.h Normal file
View File

@@ -0,0 +1,59 @@
/*
* AUTCPU12 specific defines
*
* (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_AUTCPU12_H
#define __ASM_ARCH_AUTCPU12_H
/*
* The flash bank is wired to chip select 0
*/
#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */
/* offset for device specific information structure */
#define AUTCPU12_LCDINFO_OFFS (0x00010000)
/* Videomemory in the internal SRAM (CS 6) */
#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
/*
* All special IO's are tied to CS1
*/
#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */
#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */
#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */
#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
/*
* defines for lcd contrast
*/
#define AUTCPU12_DPOT_PORT_OFFSET PEDR
#define AUTCPU12_DPOT_CS (1<<0)
#define AUTCPU12_DPOT_CLK (1<<1)
#define AUTCPU12_DPOT_UD (1<<2)
#endif

304
arch/arm/mach-clps711x/include/mach/clps711x.h Normal file
View File

@@ -0,0 +1,304 @@
/*
* This file contains the hardware definitions of the Cirrus Logic
* ARM7 CLPS711X internal registers.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_CLPS711X_H
#define __MACH_CLPS711X_H
#define CLPS711X_PHYS_BASE (0x80000000)
#define PADR (0x0000)
#define PBDR (0x0001)
#define PCDR (0x0002)
#define PDDR (0x0003)
#define PADDR (0x0040)
#define PBDDR (0x0041)
#define PCDDR (0x0042)
#define PDDDR (0x0043)
#define PEDR (0x0083)
#define PEDDR (0x00c3)
#define SYSCON1 (0x0100)
#define SYSFLG1 (0x0140)
#define MEMCFG1 (0x0180)
#define MEMCFG2 (0x01c0)
#define DRFPR (0x0200)
#define INTSR1 (0x0240)
#define INTMR1 (0x0280)
#define LCDCON (0x02c0)
#define TC1D (0x0300)
#define TC2D (0x0340)
#define RTCDR (0x0380)
#define RTCMR (0x03c0)
#define PMPCON (0x0400)
#define CODR (0x0440)
#define UARTDR1 (0x0480)
#define UBRLCR1 (0x04c0)
#define SYNCIO (0x0500)
#define PALLSW (0x0540)
#define PALMSW (0x0580)
#define STFCLR (0x05c0)
#define BLEOI (0x0600)
#define MCEOI (0x0640)
#define TEOI (0x0680)
#define TC1EOI (0x06c0)
#define TC2EOI (0x0700)
#define RTCEOI (0x0740)
#define UMSEOI (0x0780)
#define COEOI (0x07c0)
#define HALT (0x0800)
#define STDBY (0x0840)
#define FBADDR (0x1000)
#define SYSCON2 (0x1100)
#define SYSFLG2 (0x1140)
#define INTSR2 (0x1240)
#define INTMR2 (0x1280)
#define UARTDR2 (0x1480)
#define UBRLCR2 (0x14c0)
#define SS2DR (0x1500)
#define SRXEOF (0x1600)
#define SS2POP (0x16c0)
#define KBDEOI (0x1700)
#define DAIR (0x2000)
#define DAIDR0 (0x2040)
#define DAIDR1 (0x2080)
#define DAIDR2 (0x20c0)
#define DAISR (0x2100)
#define SYSCON3 (0x2200)
#define INTSR3 (0x2240)
#define INTMR3 (0x2280)
#define LEDFLSH (0x22c0)
#define SDCONF (0x2300)
#define SDRFPR (0x2340)
#define UNIQID (0x2440)
#define DAI64FS (0x2600)
#define PLLW (0x2610)
#define PLLR (0xa5a8)
#define RANDID0 (0x2700)
#define RANDID1 (0x2704)
#define RANDID2 (0x2708)
#define RANDID3 (0x270c)
/* common bits: SYSCON1 / SYSCON2 */
#define SYSCON_UARTEN (1 << 8)
#define SYSCON1_KBDSCAN(x) ((x) & 15)
#define SYSCON1_KBDSCANMASK (15)
#define SYSCON1_TC1M (1 << 4)
#define SYSCON1_TC1S (1 << 5)
#define SYSCON1_TC2M (1 << 6)
#define SYSCON1_TC2S (1 << 7)
#define SYSCON1_UART1EN SYSCON_UARTEN
#define SYSCON1_BZTOG (1 << 9)
#define SYSCON1_BZMOD (1 << 10)
#define SYSCON1_DBGEN (1 << 11)
#define SYSCON1_LCDEN (1 << 12)
#define SYSCON1_CDENTX (1 << 13)
#define SYSCON1_CDENRX (1 << 14)
#define SYSCON1_SIREN (1 << 15)
#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
#define SYSCON1_ADCKSEL_MASK (3 << 16)
#define SYSCON1_EXCKEN (1 << 18)
#define SYSCON1_WAKEDIS (1 << 19)
#define SYSCON1_IRTXM (1 << 20)
/* common bits: SYSFLG1 / SYSFLG2 */
#define SYSFLG_UBUSY (1 << 11)
#define SYSFLG_URXFE (1 << 22)
#define SYSFLG_UTXFF (1 << 23)
#define SYSFLG1_MCDR (1 << 0)
#define SYSFLG1_DCDET (1 << 1)
#define SYSFLG1_WUDR (1 << 2)
#define SYSFLG1_WUON (1 << 3)
#define SYSFLG1_CTS (1 << 8)
#define SYSFLG1_DSR (1 << 9)
#define SYSFLG1_DCD (1 << 10)
#define SYSFLG1_UBUSY SYSFLG_UBUSY
#define SYSFLG1_NBFLG (1 << 12)
#define SYSFLG1_RSTFLG (1 << 13)
#define SYSFLG1_PFFLG (1 << 14)
#define SYSFLG1_CLDFLG (1 << 15)
#define SYSFLG1_URXFE SYSFLG_URXFE
#define SYSFLG1_UTXFF SYSFLG_UTXFF
#define SYSFLG1_CRXFE (1 << 24)
#define SYSFLG1_CTXFF (1 << 25)
#define SYSFLG1_SSIBUSY (1 << 26)
#define SYSFLG1_ID (1 << 29)
#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
#define SYSFLG1_VERID_MASK (3 << 30)
#define SYSFLG2_SSRXOF (1 << 0)
#define SYSFLG2_RESVAL (1 << 1)
#define SYSFLG2_RESFRM (1 << 2)
#define SYSFLG2_SS2RXFE (1 << 3)
#define SYSFLG2_SS2TXFF (1 << 4)
#define SYSFLG2_SS2TXUF (1 << 5)
#define SYSFLG2_CKMODE (1 << 6)
#define SYSFLG2_UBUSY SYSFLG_UBUSY
#define SYSFLG2_URXFE SYSFLG_URXFE
#define SYSFLG2_UTXFF SYSFLG_UTXFF
#define LCDCON_GSEN (1 << 30)
#define LCDCON_GSMD (1 << 31)
#define SYSCON2_SERSEL (1 << 0)
#define SYSCON2_KBD6 (1 << 1)
#define SYSCON2_DRAMZ (1 << 2)
#define SYSCON2_KBWEN (1 << 3)
#define SYSCON2_SS2TXEN (1 << 4)
#define SYSCON2_PCCARD1 (1 << 5)
#define SYSCON2_PCCARD2 (1 << 6)
#define SYSCON2_SS2RXEN (1 << 7)
#define SYSCON2_UART2EN SYSCON_UARTEN
#define SYSCON2_SS2MAEN (1 << 9)
#define SYSCON2_OSTB (1 << 12)
#define SYSCON2_CLKENSL (1 << 13)
#define SYSCON2_BUZFREQ (1 << 14)
/* common bits: UARTDR1 / UARTDR2 */
#define UARTDR_FRMERR (1 << 8)
#define UARTDR_PARERR (1 << 9)
#define UARTDR_OVERR (1 << 10)
/* common bits: UBRLCR1 / UBRLCR2 */
#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
#define UBRLCR_BREAK (1 << 12)
#define UBRLCR_PRTEN (1 << 13)
#define UBRLCR_EVENPRT (1 << 14)
#define UBRLCR_XSTOP (1 << 15)
#define UBRLCR_FIFOEN (1 << 16)
#define UBRLCR_WRDLEN5 (0 << 17)
#define UBRLCR_WRDLEN6 (1 << 17)
#define UBRLCR_WRDLEN7 (2 << 17)
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)
#define DAIR_RESERVED (0x0404)
#define DAIR_DAIEN (1 << 16)
#define DAIR_ECS (1 << 17)
#define DAIR_LCTM (1 << 19)
#define DAIR_LCRM (1 << 20)
#define DAIR_RCTM (1 << 21)
#define DAIR_RCRM (1 << 22)
#define DAIR_LBM (1 << 23)
#define DAIDR2_FIFOEN (1 << 15)
#define DAIDR2_FIFOLEFT (0x0d << 16)
#define DAIDR2_FIFORIGHT (0x11 << 16)
#define DAISR_RCTS (1 << 0)
#define DAISR_RCRS (1 << 1)
#define DAISR_LCTS (1 << 2)
#define DAISR_LCRS (1 << 3)
#define DAISR_RCTU (1 << 4)
#define DAISR_RCRO (1 << 5)
#define DAISR_LCTU (1 << 6)
#define DAISR_LCRO (1 << 7)
#define DAISR_RCNF (1 << 8)
#define DAISR_RCNE (1 << 9)
#define DAISR_LCNF (1 << 10)
#define DAISR_LCNE (1 << 11)
#define DAISR_FIFO (1 << 12)
#define DAI64FS_I2SF64 (1 << 0)
#define DAI64FS_AUDIOCLKEN (1 << 1)
#define DAI64FS_AUDIOCLKSRC (1 << 2)
#define DAI64FS_MCLK256EN (1 << 3)
#define DAI64FS_LOOPBACK (1 << 5)
#define SYSCON3_ADCCON (1 << 0)
#define SYSCON3_CLKCTL0 (1 << 1)
#define SYSCON3_CLKCTL1 (1 << 2)
#define SYSCON3_DAISEL (1 << 3)
#define SYSCON3_ADCCKNSEN (1 << 4)
#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
#define SYSCON3_VERSN_MASK (7 << 5)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
#define SYSCON3_128FS SYSCON3_DAIEN
#define SYSCON3_ENPD67 (1 << 10)
#define SDCONF_ACTIVE (1 << 10)
#define SDCONF_CLKCTL (1 << 9)
#define SDCONF_WIDTH_4 (0 << 7)
#define SDCONF_WIDTH_8 (1 << 7)
#define SDCONF_WIDTH_16 (2 << 7)
#define SDCONF_WIDTH_32 (3 << 7)
#define SDCONF_SIZE_16 (0 << 5)
#define SDCONF_SIZE_64 (1 << 5)
#define SDCONF_SIZE_128 (2 << 5)
#define SDCONF_SIZE_256 (3 << 5)
#define SDCONF_CASLAT_2 (2)
#define SDCONF_CASLAT_3 (3)
#define MEMCFG_BUS_WIDTH_32 (1)
#define MEMCFG_BUS_WIDTH_16 (0)
#define MEMCFG_BUS_WIDTH_8 (3)
#define MEMCFG_SQAEN (1 << 6)
#define MEMCFG_CLKENB (1 << 7)
#define MEMCFG_WAITSTATE_8_3 (0 << 2)
#define MEMCFG_WAITSTATE_7_3 (1 << 2)
#define MEMCFG_WAITSTATE_6_3 (2 << 2)
#define MEMCFG_WAITSTATE_5_3 (3 << 2)
#define MEMCFG_WAITSTATE_4_2 (4 << 2)
#define MEMCFG_WAITSTATE_3_2 (5 << 2)
#define MEMCFG_WAITSTATE_2_2 (6 << 2)
#define MEMCFG_WAITSTATE_1_2 (7 << 2)
#define MEMCFG_WAITSTATE_8_1 (8 << 2)
#define MEMCFG_WAITSTATE_7_1 (9 << 2)
#define MEMCFG_WAITSTATE_6_1 (10 << 2)
#define MEMCFG_WAITSTATE_5_1 (11 << 2)
#define MEMCFG_WAITSTATE_4_0 (12 << 2)
#define MEMCFG_WAITSTATE_3_0 (13 << 2)
#define MEMCFG_WAITSTATE_2_0 (14 << 2)
#define MEMCFG_WAITSTATE_1_0 (15 << 2)
/* INTSR1 Interrupts */
#define IRQ_CSINT (4)
#define IRQ_EINT1 (5)
#define IRQ_EINT2 (6)
#define IRQ_EINT3 (7)
#define IRQ_TC1OI (8)
#define IRQ_TC2OI (9)
#define IRQ_RTCMI (10)
#define IRQ_TINT (11)
#define IRQ_UTXINT1 (12)
#define IRQ_URXINT1 (13)
#define IRQ_UMSINT (14)
#define IRQ_SSEOTI (15)
/* INTSR2 Interrupts */
#define IRQ_KBDINT (16 + 0)
#define IRQ_SS2RX (16 + 1)
#define IRQ_SS2TX (16 + 2)
#define IRQ_UTXINT2 (16 + 12)
#define IRQ_URXINT2 (16 + 13)
/* INTSR3 Interrupts */
#define IRQ_DAIINT (32 + 0)
#endif /* __MACH_CLPS711X_H */

38
arch/arm/mach-clps711x/include/mach/debug-macro.S Normal file
View File

@@ -0,0 +1,38 @@
/* arch/arm/mach-clps711x/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/hardware.h>
.macro addruart, rp, rv, tmp
#ifndef CONFIG_DEBUG_CLPS711X_UART2
mov \rp, #0x0000 @ UART1
#else
mov \rp, #0x1000 @ UART2
#endif
orr \rv, \rp, #CLPS711X_VIRT_BASE
orr \rp, \rp, #CLPS711X_PHYS_BASE
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0480] @ UARTDR
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
tst \rd, #1 << 11 @ UBUSYx
bne 1001b
.endm

80
arch/arm/mach-clps711x/include/mach/hardware.h Normal file
View File

@@ -0,0 +1,80 @@
/*
* arch/arm/mach-clps711x/include/mach/hardware.h
*
* This file contains the hardware definitions of the Prospector P720T.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#include <mach/clps711x.h>
#define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \
(((x) >> 2) & 0x3c000000)))
#define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
#ifndef __ASSEMBLY__
#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off))
#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off))
#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off))
#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off))
#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off))
#endif
/*
* The physical addresses that the external chip select signals map to is
* dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
* processors. CONFIG_EP72XX_BOOT_ROM is only available if these
* processors are in use.
*/
#ifndef CONFIG_EP72XX_ROM_BOOT
#define CS0_PHYS_BASE (0x00000000)
#define CS1_PHYS_BASE (0x10000000)
#define CS2_PHYS_BASE (0x20000000)
#define CS3_PHYS_BASE (0x30000000)
#define CS4_PHYS_BASE (0x40000000)
#define CS5_PHYS_BASE (0x50000000)
#define CS6_PHYS_BASE (0x60000000)
#define CS7_PHYS_BASE (0x70000000)
#else
#define CS0_PHYS_BASE (0x70000000)
#define CS1_PHYS_BASE (0x60000000)
#define CS2_PHYS_BASE (0x50000000)
#define CS3_PHYS_BASE (0x40000000)
#define CS4_PHYS_BASE (0x30000000)
#define CS5_PHYS_BASE (0x20000000)
#define CS6_PHYS_BASE (0x10000000)
#define CS7_PHYS_BASE (0x00000000)
#endif
#define CLPS711X_SRAM_BASE CS6_PHYS_BASE
#define CLPS711X_SRAM_SIZE (48 * 1024)
#define CLPS711X_SDRAM0_BASE (0xc0000000)
#define CLPS711X_SDRAM1_BASE (0xd0000000)
#if defined (CONFIG_ARCH_EDB7211)
/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
#endif /* CONFIG_ARCH_EDB7211 */
#endif

41
arch/arm/mach-clps711x/include/mach/memory.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* arch/arm/mach-clps711x/include/mach/memory.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PLAT_PHYS_OFFSET UL(0xc0000000)
/*
* The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
* uses only one of the two banks (bank #1). However, even within
* bank #1, memory is discontiguous.
*
* The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
* them, so we use 24 for the node max shift to get 16MB node sizes.
*/
#define SECTION_SIZE_BITS 24
#define MAX_PHYSMEM_BITS 32
#endif

116
arch/arm/mach-clps711x/include/mach/syspld.h Normal file
View File

@@ -0,0 +1,116 @@
/*
* arch/arm/mach-clps711x/include/mach/syspld.h
*
* System Control PLD register definitions.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSPLD_H
#define __ASM_ARCH_SYSPLD_H
#define SYSPLD_PHYS_BASE (0x10000000)
#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
#define PLD_INT SYSPLD_REG(u32, 0x000000)
#define PLD_INT_PENIRQ (1 << 5)
#define PLD_INT_UCB_IRQ (1 << 1)
#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */
#define PLD_PWR SYSPLD_REG(u32, 0x000004)
#define PLD_PWR_EXT (1 << 5)
#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */
#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */
#define PLD_S3_ON (1 << 2) /* LCD backlight enable */
#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */
#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */
#define PLD_KBD SYSPLD_REG(u32, 0x000008)
#define PLD_KBD_WAKE (1 << 1)
#define PLD_KBD_EN (1 << 0)
#define PLD_SPI SYSPLD_REG(u32, 0x00000c)
#define PLD_SPI_EN (1 << 0)
#define PLD_IO SYSPLD_REG(u32, 0x000010)
#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */
#define PLD_IO_USER (1 << 5) /* user defined switch */
#define PLD_IO_LED3 (1 << 4)
#define PLD_IO_LED2 (1 << 3)
#define PLD_IO_LED1 (1 << 2)
#define PLD_IO_LED0 (1 << 1)
#define PLD_IO_LEDEN (1 << 0)
#define PLD_IRDA SYSPLD_REG(u32, 0x000014)
#define PLD_IRDA_EN (1 << 0)
#define PLD_COM2 SYSPLD_REG(u32, 0x000018)
#define PLD_COM2_EN (1 << 0)
#define PLD_COM1 SYSPLD_REG(u32, 0x00001c)
#define PLD_COM1_EN (1 << 0)
#define PLD_AUD SYSPLD_REG(u32, 0x000020)
#define PLD_AUD_DIV1 (1 << 6)
#define PLD_AUD_DIV0 (1 << 5)
#define PLD_AUD_CLK_SEL1 (1 << 4)
#define PLD_AUD_CLK_SEL0 (1 << 3)
#define PLD_AUD_MIC_PWR (1 << 2)
#define PLD_AUD_MIC_GAIN (1 << 1)
#define PLD_AUD_CODEC_EN (1 << 0)
#define PLD_CF SYSPLD_REG(u32, 0x000024)
#define PLD_CF2_SLEEP (1 << 5)
#define PLD_CF1_SLEEP (1 << 4)
#define PLD_CF2_nPDREQ (1 << 3)
#define PLD_CF1_nPDREQ (1 << 2)
#define PLD_CF2_nIRQ (1 << 1)
#define PLD_CF1_nIRQ (1 << 0)
#define PLD_SDC SYSPLD_REG(u32, 0x000028)
#define PLD_SDC_INT_EN (1 << 2)
#define PLD_SDC_WP (1 << 1)
#define PLD_SDC_CD (1 << 0)
#define PLD_FPGA SYSPLD_REG(u32, 0x00002c)
#define PLD_CODEC SYSPLD_REG(u32, 0x400000)
#define PLD_CODEC_IRQ3 (1 << 4)
#define PLD_CODEC_IRQ2 (1 << 3)
#define PLD_CODEC_IRQ1 (1 << 2)
#define PLD_CODEC_EN (1 << 0)
#define PLD_BRITE SYSPLD_REG(u32, 0x400004)
#define PLD_BRITE_UP (1 << 1)
#define PLD_BRITE_DN (1 << 0)
#define PLD_LCDEN SYSPLD_REG(u32, 0x400008)
#define PLD_LCDEN_EN (1 << 0)
#define PLD_ID SYSPLD_REG(u32, 0x40000c)
#define PLD_TCH SYSPLD_REG(u32, 0x400010)
#define PLD_TCH_PENIRQ (1 << 1)
#define PLD_TCH_EN (1 << 0)
#define PLD_GPIO SYSPLD_REG(u32, 0x400014)
#define PLD_GPIO2 (1 << 2)
#define PLD_GPIO1 (1 << 1)
#define PLD_GPIO0 (1 << 0)
#endif

2
arch/arm/mach-clps711x/include/mach/timex.h Normal file
View File

@@ -0,0 +1,2 @@
/* Bogus value */
#define CLOCK_TICK_RATE 512000

55
arch/arm/mach-clps711x/include/mach/uncompress.h Normal file
View File

@@ -0,0 +1,55 @@
/*
* arch/arm/mach-clps711x/include/mach/uncompress.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <mach/clps711x.h>
#ifdef CONFIG_DEBUG_CLPS711X_UART2
#define SYSFLGx SYSFLG2
#define UARTDRx UARTDR2
#else
#define SYSFLGx SYSFLG1
#define UARTDRx UARTDR1
#endif
#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x)))
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
*/
static inline void putc(int c)
{
while (phys_reg(SYSFLGx) & SYSFLG_UTXFF)
barrier();
phys_reg(UARTDRx) = c;
}
static inline void flush(void)
{
while (phys_reg(SYSFLGx) & SYSFLG_UBUSY)
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()