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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
commit 25c6d769f4
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61
arch/arm/mach-at91/include/mach/at91_adc.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_adc.h
*
* Copyright (C) SAN People
*
* Analog-to-Digital Converter (ADC) registers.
* Based on AT91SAM9260 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_ADC_H
#define AT91_ADC_H
#define AT91_ADC_CR 0x00 /* Control Register */
#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
#define AT91_ADC_START (1 << 1) /* Start Conversion */
#define AT91_ADC_MR 0x04 /* Mode Register */
#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
#define AT91_ADC_TRGSEL_TC0 (0 << 1)
#define AT91_ADC_TRGSEL_TC1 (1 << 1)
#define AT91_ADC_TRGSEL_TC2 (2 << 1)
#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
#define AT91_ADC_PRESCAL_(x) ((x) << 8)
#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */
#define AT91_ADC_STARTUP_(x) ((x) << 16)
#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
#define AT91_ADC_SHTIM_(x) ((x) << 24)
#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
#define AT91_ADC_SR 0x1C /* Status Register */
#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
#define AT91_ADC_LDATA (0x3ff)
#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
#define AT91_ADC_DATA (0x3ff)
#endif

66
arch/arm/mach-at91/include/mach/at91_dbgu.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_dbgu.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (0x14) /* Status Register */
#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */
/*
* Some AT91 parts that don't have full DEBUG units still support the ID
* and extensions register.
*/
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#endif

23
arch/arm/mach-at91/include/mach/at91_matrix.h Normal file
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/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#ifndef __MACH_AT91_MATRIX_H__
#define __MACH_AT91_MATRIX_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_matrix_base;
#define at91_matrix_read(field) \
__raw_readl(at91_matrix_base + field)
#define at91_matrix_write(field, value) \
__raw_writel(value, at91_matrix_base + field)
#else
.extern at91_matrix_base
#endif
#endif /* __MACH_AT91_MATRIX_H__ */

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arch/arm/mach-at91/include/mach/at91_pio.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
#define PIO_ESR 0xc0 /* Edge Select Register */
#define PIO_LSR 0xc4 /* Level Select Register */
#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
#define ABCDSR_PERIPH_A 0x0
#define ABCDSR_PERIPH_B 0x1
#define ABCDSR_PERIPH_C 0x2
#define ABCDSR_PERIPH_D 0x3
#endif

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arch/arm/mach-at91/include/mach/at91_pmc.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#ifndef __ASSEMBLY__
extern void __iomem *at91_pmc_base;
#define at91_pmc_read(field) \
__raw_readl(at91_pmc_base + field)
#define at91_pmc_write(field, value) \
__raw_writel(value, at91_pmc_base + field)
#else
.extern at91_pmc_base
#endif
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f)
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
#define PMC_PRES_OFFSET 2
#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
#define PMC_ALT_PRES_OFFSET 4
#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
#define AT91_PMC_SR 0x68 /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */
#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
#endif

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arch/arm/mach-at91/include/mach/at91_ramc.h Normal file
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/*
* Header file for the Atmel RAM Controller
*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __AT91_RAMC_H__
#define __AT91_RAMC_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_ramc_base[];
#define at91_ramc_read(id, field) \
__raw_readl(at91_ramc_base[id] + field)
#define at91_ramc_write(id, field, value) \
__raw_writel(value, at91_ramc_base[id] + field)
#else
.extern at91_ramc_base
#endif
#define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2
#include <mach/at91rm9200_sdramc.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/at91sam9_sdramc.h>
#endif /* __AT91_RAMC_H__ */

35
arch/arm/mach-at91/include/mach/at91_rtt.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_rtt.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* Real-time Timer (RTT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RTT_H
#define AT91_RTT_H
#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
#define AT91_RTT_VR 0x08 /* Real-time Value Register */
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
#define AT91_RTT_SR 0x0c /* Real-time Status Register */
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91_st.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System Timer (ST) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_ST_H
#define AT91_ST_H
#ifndef __ASSEMBLY__
extern void __iomem *at91_st_base;
#define at91_st_read(field) \
__raw_readl(at91_st_base + field)
#define at91_st_write(field, value) \
__raw_writel(value, at91_st_base + field)
#else
.extern at91_st_base
#endif
#define AT91_ST_CR 0x00 /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR 0x10 /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91rm9200.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91RM9200_ID_US0 6 /* USART 0 */
#define AT91RM9200_ID_US1 7 /* USART 1 */
#define AT91RM9200_ID_US2 8 /* USART 2 */
#define AT91RM9200_ID_US3 9 /* USART 3 */
#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
#define AT91RM9200_ID_UDP 11 /* USB Device Port */
#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
#define AT91RM9200_ID_UHP 23 /* USB Host port */
#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
/*
* Peripheral physical base addresses.
*/
#define AT91RM9200_BASE_TCB0 0xfffa0000
#define AT91RM9200_BASE_TC0 0xfffa0000
#define AT91RM9200_BASE_TC1 0xfffa0040
#define AT91RM9200_BASE_TC2 0xfffa0080
#define AT91RM9200_BASE_TCB1 0xfffa4000
#define AT91RM9200_BASE_TC3 0xfffa4000
#define AT91RM9200_BASE_TC4 0xfffa4040
#define AT91RM9200_BASE_TC5 0xfffa4080
#define AT91RM9200_BASE_UDP 0xfffb0000
#define AT91RM9200_BASE_MCI 0xfffb4000
#define AT91RM9200_BASE_TWI 0xfffb8000
#define AT91RM9200_BASE_EMAC 0xfffbc000
#define AT91RM9200_BASE_US0 0xfffc0000
#define AT91RM9200_BASE_US1 0xfffc4000
#define AT91RM9200_BASE_US2 0xfffc8000
#define AT91RM9200_BASE_US3 0xfffcc000
#define AT91RM9200_BASE_SSC0 0xfffd0000
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
/*
* System Peripherals
*/
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
/*
* Internal Memory.
*/
#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91rm9200_mc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_MC_H
#define AT91RM9200_MC_H
/* Memory Controller */
#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* Burst Flash Controller register */
#define AT91_BFC_MR 0xc0 /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif

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arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (SDRAMC only) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_SDRAMC_H
#define AT91RM9200_SDRAMC_H
/* SDRAM Controller registers */
#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9260.h
*
* (C) 2006 Andrew Victor
*
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* Includes also definitions for AT91SAM9XE and AT91SAM9G families
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
#define AT91SAM9260_ID_US0 6 /* USART 0 */
#define AT91SAM9260_ID_US1 7 /* USART 1 */
#define AT91SAM9260_ID_US2 8 /* USART 2 */
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
#define AT91SAM9260_ID_US3 23 /* USART 3 */
#define AT91SAM9260_ID_US4 24 /* USART 4 */
#define AT91SAM9260_ID_US5 25 /* USART 5 */
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9260_BASE_TCB0 0xfffa0000
#define AT91SAM9260_BASE_TC0 0xfffa0000
#define AT91SAM9260_BASE_TC1 0xfffa0040
#define AT91SAM9260_BASE_TC2 0xfffa0080
#define AT91SAM9260_BASE_UDP 0xfffa4000
#define AT91SAM9260_BASE_MCI 0xfffa8000
#define AT91SAM9260_BASE_TWI 0xfffac000
#define AT91SAM9260_BASE_US0 0xfffb0000
#define AT91SAM9260_BASE_US1 0xfffb4000
#define AT91SAM9260_BASE_US2 0xfffb8000
#define AT91SAM9260_BASE_SSC 0xfffbc000
#define AT91SAM9260_BASE_ISI 0xfffc0000
#define AT91SAM9260_BASE_EMAC 0xfffc4000
#define AT91SAM9260_BASE_SPI0 0xfffc8000
#define AT91SAM9260_BASE_SPI1 0xfffcc000
#define AT91SAM9260_BASE_US3 0xfffd0000
#define AT91SAM9260_BASE_US4 0xfffd4000
#define AT91SAM9260_BASE_US5 0xfffd8000
#define AT91SAM9260_BASE_TCB1 0xfffdc000
#define AT91SAM9260_BASE_TC3 0xfffdc000
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
/*
* System Peripherals
*/
#define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
#define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_MATRIX 0xffffee00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800
#define AT91SAM9260_BASE_RSTC 0xfffffd00
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91SAM9260_BASE_GPBR 0xfffffd50
/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
*
* Copyright (C) 2007 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9261.h
*
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9261_ID_US0 6 /* USART 0 */
#define AT91SAM9261_ID_US1 7 /* USART 1 */
#define AT91SAM9261_ID_US2 8 /* USART 2 */
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9261_BASE_TCB0 0xfffa0000
#define AT91SAM9261_BASE_TC0 0xfffa0000
#define AT91SAM9261_BASE_TC1 0xfffa0040
#define AT91SAM9261_BASE_TC2 0xfffa0080
#define AT91SAM9261_BASE_UDP 0xfffa4000
#define AT91SAM9261_BASE_MCI 0xfffa8000
#define AT91SAM9261_BASE_TWI 0xfffac000
#define AT91SAM9261_BASE_US0 0xfffb0000
#define AT91SAM9261_BASE_US1 0xfffb4000
#define AT91SAM9261_BASE_US2 0xfffb8000
#define AT91SAM9261_BASE_SSC0 0xfffbc000
#define AT91SAM9261_BASE_SSC1 0xfffc0000
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
/*
* System Peripherals
*/
#define AT91SAM9261_BASE_SMC 0xffffec00
#define AT91SAM9261_BASE_MATRIX 0xffffee00
#define AT91SAM9261_BASE_SDRAMC 0xffffea00
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800
#define AT91SAM9261_BASE_RSTC 0xfffffd00
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
#define AT91SAM9261_BASE_WDT 0xfffffd40
#define AT91SAM9261_BASE_GPBR 0xfffffd50
/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
*
* Copyright (C) 2007 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_ITCM_64 (7 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
/*
* System Peripherals
*/
#define AT91SAM9263_BASE_ECC0 0xffffe000
#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
#define AT91SAM9263_BASE_SMC0 0xffffe400
#define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
#define AT91SAM9263_BASE_SMC1 0xffffea00
#define AT91SAM9263_BASE_MATRIX 0xffffec00
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400
#define AT91SAM9263_BASE_PIOC 0xfffff600
#define AT91SAM9263_BASE_PIOD 0xfffff800
#define AT91SAM9263_BASE_PIOE 0xfffffa00
#define AT91SAM9263_BASE_RSTC 0xfffffd00
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
#define AT91SAM9263_BASE_WDT 0xfffffd40
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91SAM9263_BASE_GPBR 0xfffffd60
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
*
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
#endif

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/*
* Header file for the Atmel DDR/SDR SDRAM Controller
*
* Copyright (C) 2010 Atmel Corporation
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_DDRSDR_H
#define AT91SAM9_DDRSDR_H
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
#define AT91_DDRSDRC_MODE_NORMAL 0
#define AT91_DDRSDRC_MODE_NOP 1
#define AT91_DDRSDRC_MODE_PRECHARGE 2
#define AT91_DDRSDRC_MODE_LMR 3
#define AT91_DDRSDRC_MODE_REFRESH 4
#define AT91_DDRSDRC_MODE_EXT_LMR 5
#define AT91_DDRSDRC_MODE_DEEP 6
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
#define AT91_DDRSDRC_NR_11 (0 << 2)
#define AT91_DDRSDRC_NR_12 (1 << 2)
#define AT91_DDRSDRC_NR_13 (2 << 2)
#define AT91_DDRSDRC_NR_14 (3 << 2)
#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
#define AT91_DDRSDRC_CAS_2 (2 << 4)
#define AT91_DDRSDRC_CAS_3 (3 << 4)
#define AT91_DDRSDRC_CAS_25 (6 << 4)
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_DDRSDRC_LPCB_DISABLE 0
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* SDRAM Controllers (SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_SDRAMC_H
#define AT91SAM9_SDRAMC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
#define AT91_SDRAMC_MODE_PRECHARGE 2
#define AT91_SDRAMC_MODE_LMR 3
#define AT91_SDRAMC_MODE_REFRESH 4
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_1 (1 << 5)
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_CAS_3 (3 << 5)
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9_smc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* Static Memory Controllers (SMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
#include <mach/cpu.h>
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
u8 ncs_read_setup;
u8 nrd_setup;
u8 ncs_write_setup;
u8 nwe_setup;
/* Pulse register */
u8 ncs_read_pulse;
u8 nrd_pulse;
u8 ncs_write_pulse;
u8 nwe_pulse;
/* Cycle register */
u16 read_cycle;
u16 write_cycle;
/* Mode register */
u32 mode;
u8 tdf_cycles:4;
};
extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
#endif
#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#endif

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/*
* Chip-specific header file for the AT91SAM9G45 family
*
* Copyright (C) 2008-2009 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9G45 preliminary datasheet.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9G45_H
#define AT91SAM9G45_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
#define AT91SAM9G45_ID_US0 7 /* USART 0 */
#define AT91SAM9G45_ID_US1 8 /* USART 1 */
#define AT91SAM9G45_ID_US2 9 /* USART 2 */
#define AT91SAM9G45_ID_US3 10 /* USART 3 */
#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9G45_BASE_UDPHS 0xfff78000
#define AT91SAM9G45_BASE_TCB0 0xfff7c000
#define AT91SAM9G45_BASE_TC0 0xfff7c000
#define AT91SAM9G45_BASE_TC1 0xfff7c040
#define AT91SAM9G45_BASE_TC2 0xfff7c080
#define AT91SAM9G45_BASE_MCI0 0xfff80000
#define AT91SAM9G45_BASE_TWI0 0xfff84000
#define AT91SAM9G45_BASE_TWI1 0xfff88000
#define AT91SAM9G45_BASE_US0 0xfff8c000
#define AT91SAM9G45_BASE_US1 0xfff90000
#define AT91SAM9G45_BASE_US2 0xfff94000
#define AT91SAM9G45_BASE_US3 0xfff98000
#define AT91SAM9G45_BASE_SSC0 0xfff9c000
#define AT91SAM9G45_BASE_SSC1 0xfffa0000
#define AT91SAM9G45_BASE_SPI0 0xfffa4000
#define AT91SAM9G45_BASE_SPI1 0xfffa8000
#define AT91SAM9G45_BASE_AC97C 0xfffac000
#define AT91SAM9G45_BASE_TSC 0xfffb0000
#define AT91SAM9G45_BASE_ISI 0xfffb4000
#define AT91SAM9G45_BASE_PWMC 0xfffb8000
#define AT91SAM9G45_BASE_EMAC 0xfffbc000
#define AT91SAM9G45_BASE_AES 0xfffc0000
#define AT91SAM9G45_BASE_TDES 0xfffc4000
#define AT91SAM9G45_BASE_SHA 0xfffc8000
#define AT91SAM9G45_BASE_TRNG 0xfffcc000
#define AT91SAM9G45_BASE_MCI1 0xfffd0000
#define AT91SAM9G45_BASE_TCB1 0xfffd4000
#define AT91SAM9G45_BASE_TC3 0xfffd4000
#define AT91SAM9G45_BASE_TC4 0xfffd4040
#define AT91SAM9G45_BASE_TC5 0xfffd4080
/*
* System Peripherals
*/
#define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
#define AT91SAM9G45_BASE_DMA 0xffffec00
#define AT91SAM9G45_BASE_SMC 0xffffe800
#define AT91SAM9G45_BASE_MATRIX 0xffffea00
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9G45_BASE_PIOA 0xfffff200
#define AT91SAM9G45_BASE_PIOB 0xfffff400
#define AT91SAM9G45_BASE_PIOC 0xfffff600
#define AT91SAM9G45_BASE_PIOD 0xfffff800
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
#define AT91SAM9G45_BASE_RSTC 0xfffffd00
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
#define AT91SAM9G45_BASE_WDT 0xfffffd40
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
/*
* Internal Memory.
*/
#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
/*
* DMA peripheral identifiers
* for hardware handshaking interface
*/
#define AT_DMA_ID_MCI0 0
#define AT_DMA_ID_SPI0_TX 1
#define AT_DMA_ID_SPI0_RX 2
#define AT_DMA_ID_SPI1_TX 3
#define AT_DMA_ID_SPI1_RX 4
#define AT_DMA_ID_SSC0_TX 5
#define AT_DMA_ID_SSC0_RX 6
#define AT_DMA_ID_SSC1_TX 7
#define AT_DMA_ID_SSC1_RX 8
#define AT_DMA_ID_AC97_TX 9
#define AT_DMA_ID_AC97_RX 10
#define AT_DMA_ID_AES_TX 11
#define AT_DMA_ID_AES_RX 12
#define AT_DMA_ID_MCI1 13
#endif

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/*
* Matrix-centric header file for the AT91SAM9G45 family
*
* Copyright (C) 2008-2009 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9G45 preliminary datasheet.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0)
#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0)
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif

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arch/arm/mach-at91/include/mach/at91sam9n12.h Normal file
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/*
* SoC specific header file for the AT91SAM9N12
*
* Copyright (C) 2012 Atmel Corporation
*
* Common definitions, based on AT91SAM9N12 SoC datasheet
*
* Licensed under GPLv2 or later
*/
#ifndef _AT91SAM9N12_H_
#define _AT91SAM9N12_H_
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9N12_BASE_USART0 0xf801c000
#define AT91SAM9N12_BASE_USART1 0xf8020000
#define AT91SAM9N12_BASE_USART2 0xf8024000
#define AT91SAM9N12_BASE_USART3 0xf8028000
/*
* Internal Memory.
*/
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#endif

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arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h Normal file
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/*
* Matrix-centric header file for the AT91SAM9N12
*
* Copyright (C) 2012 Atmel Corporation.
*
* Only EBI related registers.
* Write Protect register definitions may be useful.
*
* Licensed under GPLv2 or later.
*/
#ifndef _AT91SAM9N12_MATRIX_H_
#define _AT91SAM9N12_MATRIX_H_
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
#define AT91_MATRIX_MP_OFF (0 << 25)
#define AT91_MATRIX_MP_ON (1 << 25)
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0)
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif

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arch/arm/mach-at91/include/mach/at91sam9rl.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91sam9260.h
*
* Copyright (C) 2007 Atmel Corporation
*
* Common definitions.
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91SAM9RL_ID_US0 6 /* USART 0 */
#define AT91SAM9RL_ID_US1 7 /* USART 1 */
#define AT91SAM9RL_ID_US2 8 /* USART 2 */
#define AT91SAM9RL_ID_US3 9 /* USART 3 */
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9RL_BASE_TCB0 0xfffa0000
#define AT91SAM9RL_BASE_TC0 0xfffa0000
#define AT91SAM9RL_BASE_TC1 0xfffa0040
#define AT91SAM9RL_BASE_TC2 0xfffa0080
#define AT91SAM9RL_BASE_MCI 0xfffa4000
#define AT91SAM9RL_BASE_TWI0 0xfffa8000
#define AT91SAM9RL_BASE_TWI1 0xfffac000
#define AT91SAM9RL_BASE_US0 0xfffb0000
#define AT91SAM9RL_BASE_US1 0xfffb4000
#define AT91SAM9RL_BASE_US2 0xfffb8000
#define AT91SAM9RL_BASE_US3 0xfffbc000
#define AT91SAM9RL_BASE_SSC0 0xfffc0000
#define AT91SAM9RL_BASE_SSC1 0xfffc4000
#define AT91SAM9RL_BASE_PWMC 0xfffc8000
#define AT91SAM9RL_BASE_SPI 0xfffcc000
#define AT91SAM9RL_BASE_TSC 0xfffd0000
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9RL_BASE_DMA 0xffffe600
#define AT91SAM9RL_BASE_ECC 0xffffe800
#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
#define AT91SAM9RL_BASE_SMC 0xffffec00
#define AT91SAM9RL_BASE_MATRIX 0xffffee00
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9RL_BASE_PIOA 0xfffff400
#define AT91SAM9RL_BASE_PIOB 0xfffff600
#define AT91SAM9RL_BASE_PIOC 0xfffff800
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
#define AT91SAM9RL_BASE_RSTC 0xfffffd00
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
#define AT91SAM9RL_BASE_RTT 0xfffffd20
#define AT91SAM9RL_BASE_PIT 0xfffffd30
#define AT91SAM9RL_BASE_WDT 0xfffffd40
#define AT91SAM9RL_BASE_GPBR 0xfffffd60
#define AT91SAM9RL_BASE_RTC 0xfffffe00
/*
* Internal Memory.
*/
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
*
* Copyright (C) 2007 Atmel Corporation
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef AT91SAM9RL_MATRIX_H
#define AT91SAM9RL_MATRIX_H
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif

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/*
* Chip-specific header file for the AT91SAM9x5 family
*
* Copyright (C) 2009-2012 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9x5 datasheet.
*
* Licensed under GPLv2 or later.
*/
#ifndef AT91SAM9X5_H
#define AT91SAM9X5_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9X5_BASE_USART0 0xf801c000
#define AT91SAM9X5_BASE_USART1 0xf8020000
#define AT91SAM9X5_BASE_USART2 0xf8024000
/*
* Internal Memory.
*/
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
#endif

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/*
* Matrix-centric header file for the AT91SAM9x5 family
*
* Copyright (C) 2009-2012 Atmel Corporation.
*
* Only EBI related registers.
* Write Protect register definitions may be useful.
*
* Licensed under GPLv2 or later.
*/
#ifndef AT91SAM9X5_MATRIX_H
#define AT91SAM9X5_MATRIX_H
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
#define AT91_MATRIX_MP_OFF (0 << 25)
#define AT91_MATRIX_MP_ON (1 << 25)
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0)
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif

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arch/arm/mach-at91/include/mach/at91x40.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91x40.h
*
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91X40_H
#define AT91X40_H
/*
* IRQ list.
*/
#define AT91X40_ID_USART0 2 /* USART port 0 */
#define AT91X40_ID_USART1 3 /* USART port 1 */
#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
#define AT91X40_ID_WD 7 /* Watchdog? */
#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
/*
* System Peripherals
*/
#define AT91_BASE_SYS 0xffc00000
#define AT91_EBI 0xffe00000 /* External Bus Interface */
#define AT91_SF 0xfff00000 /* Special Function */
#define AT91_USART1 0xfffcc000 /* USART 1 */
#define AT91_USART0 0xfffd0000 /* USART 0 */
#define AT91_TC 0xfffe0000 /* Timer Counter */
#define AT91_PIOA 0xffff0000 /* PIO Controller A */
#define AT91_PS 0xffff4000 /* Power Save */
#define AT91_WD 0xffff8000 /* Watchdog Timer */
/*
* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
* But it does have a chip identify register and extension ID, so define at
* least these here.
*/
#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
/*
* Support defines for the simple Power Controller module.
*/
#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
#endif /* AT91X40_H */

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#ifndef __MACH_ATMEL_MCI_H
#define __MACH_ATMEL_MCI_H
#include <linux/platform_data/dma-atmel.h>
/**
* struct mci_dma_data - DMA data for MCI interface
*/
struct mci_dma_data {
struct at_dma_slave sdata;
};
/* accessor macros */
#define slave_data_ptr(s) (&(s)->sdata)
#define find_slave_dev(s) ((s)->sdata.dma_dev)
#endif /* __MACH_ATMEL_MCI_H */

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/*
* arch/arm/mach-at91/include/mach/cpu.h
*
* Copyright (C) 2006 SAN People
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __MACH_CPU_H__
#define __MACH_CPU_H__
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
#define ARCH_ID_AT91SAM9G10 0x019903a0
#define ARCH_ID_AT91SAM9G20 0x019905a0
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
#define ARCH_ID_AT91SAM9G45 0x819b05a0
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
#define ARCH_ID_AT91SAM9N12 0x819a07a0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
#define ARCH_ID_AT91M40800 0x14080044
#define ARCH_ID_AT91R40807 0x44080746
#define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840
#define ARCH_ID_SAMA5D3 0x8A5C07C0
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
#define ARCH_EXID_AT91SAM9G46 0x00000003
#define ARCH_EXID_AT91SAM9G45 0x00000004
#define ARCH_EXID_AT91SAM9G15 0x00000000
#define ARCH_EXID_AT91SAM9G35 0x00000001
#define ARCH_EXID_AT91SAM9X35 0x00000002
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
#define ARCH_EXID_SAMA5D31 0x00444300
#define ARCH_EXID_SAMA5D33 0x00414300
#define ARCH_EXID_SAMA5D34 0x00414301
#define ARCH_EXID_SAMA5D35 0x00584300
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
/* RM9200 type */
#define ARCH_REVISON_9200_BGA (0 << 0)
#define ARCH_REVISON_9200_PQFP (1 << 0)
#ifndef __ASSEMBLY__
enum at91_soc_type {
/* 920T */
AT91_SOC_RM9200,
/* SAM92xx */
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
/* SAM9Gxx */
AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
/* SAM9RL */
AT91_SOC_SAM9RL,
/* SAM9X5 */
AT91_SOC_SAM9X5,
/* SAM9N12 */
AT91_SOC_SAM9N12,
/* SAMA5D3 */
AT91_SOC_SAMA5D3,
/* Unknown type */
AT91_SOC_UNKNOWN,
};
enum at91_soc_subtype {
/* RM9200 */
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
/* SAM9260 */
AT91_SOC_SAM9XE,
/* SAM9G45 */
AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
/* SAM9X5 */
AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
/* SAMA5D3 */
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
AT91_SOC_SAMA5D35,
/* No subtype for this SoC */
AT91_SOC_SUBTYPE_NONE,
/* Unknown subtype */
AT91_SOC_SUBTYPE_UNKNOWN,
};
struct at91_socinfo {
unsigned int type, subtype;
unsigned int cidr, exid;
};
extern struct at91_socinfo at91_soc_initdata;
const char *at91_get_soc_type(struct at91_socinfo *c);
const char *at91_get_soc_subtype(struct at91_socinfo *c);
static inline int at91_soc_is_detected(void)
{
return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
}
#ifdef CONFIG_SOC_AT91RM9200
#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
#else
#define cpu_is_at91rm9200() (0)
#define cpu_is_at91rm9200_bga() (0)
#define cpu_is_at91rm9200_pqfp() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9260
#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#define cpu_is_at91sam9g20() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9261
#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
#else
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9g10() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9263
#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9RL
#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
#else
#define cpu_is_at91sam9rl() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9G45
#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#define cpu_is_at91sam9m10() (0)
#define cpu_is_at91sam9g46() (0)
#define cpu_is_at91sam9m11() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9X5
#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
#else
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
#define cpu_is_at91sam9g35() (0)
#define cpu_is_at91sam9x35() (0)
#define cpu_is_at91sam9g25() (0)
#define cpu_is_at91sam9x25() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9N12
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
#else
#define cpu_is_at91sam9n12() (0)
#endif
#ifdef CONFIG_SOC_SAMA5D3
#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
#else
#define cpu_is_sama5d3() (0)
#endif
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these
* definitions may reduce clutter in common drivers.
*/
#define cpu_is_at32ap7000() (0)
#endif /* __ASSEMBLY__ */
#endif /* __MACH_CPU_H__ */

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arch/arm/mach-at91/include/mach/debug-macro.S Normal file
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/*
* arch/arm/mach-at91/include/mach/debug-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Debugging macro include header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/hardware.h>
#include <mach/at91_dbgu.h>
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
#define AT91_DBGU AT91_BASE_DBGU0
#else
#define AT91_DBGU AT91_BASE_DBGU1
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =AT91_DBGU @ System peripherals (phys address)
ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
beq 1001b
.endm

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arch/arm/mach-at91/include/mach/gpio.h Normal file
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/*
* arch/arm/mach-at91/include/mach/gpio.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
#define __ASM_ARCH_AT91RM9200_GPIO_H
#include <linux/kernel.h>
#include <asm/irq.h>
#define MAX_GPIO_BANKS 5
#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32)
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91_PIN_PA0 (0x00 + 0)
#define AT91_PIN_PA1 (0x00 + 1)
#define AT91_PIN_PA2 (0x00 + 2)
#define AT91_PIN_PA3 (0x00 + 3)
#define AT91_PIN_PA4 (0x00 + 4)
#define AT91_PIN_PA5 (0x00 + 5)
#define AT91_PIN_PA6 (0x00 + 6)
#define AT91_PIN_PA7 (0x00 + 7)
#define AT91_PIN_PA8 (0x00 + 8)
#define AT91_PIN_PA9 (0x00 + 9)
#define AT91_PIN_PA10 (0x00 + 10)
#define AT91_PIN_PA11 (0x00 + 11)
#define AT91_PIN_PA12 (0x00 + 12)
#define AT91_PIN_PA13 (0x00 + 13)
#define AT91_PIN_PA14 (0x00 + 14)
#define AT91_PIN_PA15 (0x00 + 15)
#define AT91_PIN_PA16 (0x00 + 16)
#define AT91_PIN_PA17 (0x00 + 17)
#define AT91_PIN_PA18 (0x00 + 18)
#define AT91_PIN_PA19 (0x00 + 19)
#define AT91_PIN_PA20 (0x00 + 20)
#define AT91_PIN_PA21 (0x00 + 21)
#define AT91_PIN_PA22 (0x00 + 22)
#define AT91_PIN_PA23 (0x00 + 23)
#define AT91_PIN_PA24 (0x00 + 24)
#define AT91_PIN_PA25 (0x00 + 25)
#define AT91_PIN_PA26 (0x00 + 26)
#define AT91_PIN_PA27 (0x00 + 27)
#define AT91_PIN_PA28 (0x00 + 28)
#define AT91_PIN_PA29 (0x00 + 29)
#define AT91_PIN_PA30 (0x00 + 30)
#define AT91_PIN_PA31 (0x00 + 31)
#define AT91_PIN_PB0 (0x20 + 0)
#define AT91_PIN_PB1 (0x20 + 1)
#define AT91_PIN_PB2 (0x20 + 2)
#define AT91_PIN_PB3 (0x20 + 3)
#define AT91_PIN_PB4 (0x20 + 4)
#define AT91_PIN_PB5 (0x20 + 5)
#define AT91_PIN_PB6 (0x20 + 6)
#define AT91_PIN_PB7 (0x20 + 7)
#define AT91_PIN_PB8 (0x20 + 8)
#define AT91_PIN_PB9 (0x20 + 9)
#define AT91_PIN_PB10 (0x20 + 10)
#define AT91_PIN_PB11 (0x20 + 11)
#define AT91_PIN_PB12 (0x20 + 12)
#define AT91_PIN_PB13 (0x20 + 13)
#define AT91_PIN_PB14 (0x20 + 14)
#define AT91_PIN_PB15 (0x20 + 15)
#define AT91_PIN_PB16 (0x20 + 16)
#define AT91_PIN_PB17 (0x20 + 17)
#define AT91_PIN_PB18 (0x20 + 18)
#define AT91_PIN_PB19 (0x20 + 19)
#define AT91_PIN_PB20 (0x20 + 20)
#define AT91_PIN_PB21 (0x20 + 21)
#define AT91_PIN_PB22 (0x20 + 22)
#define AT91_PIN_PB23 (0x20 + 23)
#define AT91_PIN_PB24 (0x20 + 24)
#define AT91_PIN_PB25 (0x20 + 25)
#define AT91_PIN_PB26 (0x20 + 26)
#define AT91_PIN_PB27 (0x20 + 27)
#define AT91_PIN_PB28 (0x20 + 28)
#define AT91_PIN_PB29 (0x20 + 29)
#define AT91_PIN_PB30 (0x20 + 30)
#define AT91_PIN_PB31 (0x20 + 31)
#define AT91_PIN_PC0 (0x40 + 0)
#define AT91_PIN_PC1 (0x40 + 1)
#define AT91_PIN_PC2 (0x40 + 2)
#define AT91_PIN_PC3 (0x40 + 3)
#define AT91_PIN_PC4 (0x40 + 4)
#define AT91_PIN_PC5 (0x40 + 5)
#define AT91_PIN_PC6 (0x40 + 6)
#define AT91_PIN_PC7 (0x40 + 7)
#define AT91_PIN_PC8 (0x40 + 8)
#define AT91_PIN_PC9 (0x40 + 9)
#define AT91_PIN_PC10 (0x40 + 10)
#define AT91_PIN_PC11 (0x40 + 11)
#define AT91_PIN_PC12 (0x40 + 12)
#define AT91_PIN_PC13 (0x40 + 13)
#define AT91_PIN_PC14 (0x40 + 14)
#define AT91_PIN_PC15 (0x40 + 15)
#define AT91_PIN_PC16 (0x40 + 16)
#define AT91_PIN_PC17 (0x40 + 17)
#define AT91_PIN_PC18 (0x40 + 18)
#define AT91_PIN_PC19 (0x40 + 19)
#define AT91_PIN_PC20 (0x40 + 20)
#define AT91_PIN_PC21 (0x40 + 21)
#define AT91_PIN_PC22 (0x40 + 22)
#define AT91_PIN_PC23 (0x40 + 23)
#define AT91_PIN_PC24 (0x40 + 24)
#define AT91_PIN_PC25 (0x40 + 25)
#define AT91_PIN_PC26 (0x40 + 26)
#define AT91_PIN_PC27 (0x40 + 27)
#define AT91_PIN_PC28 (0x40 + 28)
#define AT91_PIN_PC29 (0x40 + 29)
#define AT91_PIN_PC30 (0x40 + 30)
#define AT91_PIN_PC31 (0x40 + 31)
#define AT91_PIN_PD0 (0x60 + 0)
#define AT91_PIN_PD1 (0x60 + 1)
#define AT91_PIN_PD2 (0x60 + 2)
#define AT91_PIN_PD3 (0x60 + 3)
#define AT91_PIN_PD4 (0x60 + 4)
#define AT91_PIN_PD5 (0x60 + 5)
#define AT91_PIN_PD6 (0x60 + 6)
#define AT91_PIN_PD7 (0x60 + 7)
#define AT91_PIN_PD8 (0x60 + 8)
#define AT91_PIN_PD9 (0x60 + 9)
#define AT91_PIN_PD10 (0x60 + 10)
#define AT91_PIN_PD11 (0x60 + 11)
#define AT91_PIN_PD12 (0x60 + 12)
#define AT91_PIN_PD13 (0x60 + 13)
#define AT91_PIN_PD14 (0x60 + 14)
#define AT91_PIN_PD15 (0x60 + 15)
#define AT91_PIN_PD16 (0x60 + 16)
#define AT91_PIN_PD17 (0x60 + 17)
#define AT91_PIN_PD18 (0x60 + 18)
#define AT91_PIN_PD19 (0x60 + 19)
#define AT91_PIN_PD20 (0x60 + 20)
#define AT91_PIN_PD21 (0x60 + 21)
#define AT91_PIN_PD22 (0x60 + 22)
#define AT91_PIN_PD23 (0x60 + 23)
#define AT91_PIN_PD24 (0x60 + 24)
#define AT91_PIN_PD25 (0x60 + 25)
#define AT91_PIN_PD26 (0x60 + 26)
#define AT91_PIN_PD27 (0x60 + 27)
#define AT91_PIN_PD28 (0x60 + 28)
#define AT91_PIN_PD29 (0x60 + 29)
#define AT91_PIN_PD30 (0x60 + 30)
#define AT91_PIN_PD31 (0x60 + 31)
#define AT91_PIN_PE0 (0x80 + 0)
#define AT91_PIN_PE1 (0x80 + 1)
#define AT91_PIN_PE2 (0x80 + 2)
#define AT91_PIN_PE3 (0x80 + 3)
#define AT91_PIN_PE4 (0x80 + 4)
#define AT91_PIN_PE5 (0x80 + 5)
#define AT91_PIN_PE6 (0x80 + 6)
#define AT91_PIN_PE7 (0x80 + 7)
#define AT91_PIN_PE8 (0x80 + 8)
#define AT91_PIN_PE9 (0x80 + 9)
#define AT91_PIN_PE10 (0x80 + 10)
#define AT91_PIN_PE11 (0x80 + 11)
#define AT91_PIN_PE12 (0x80 + 12)
#define AT91_PIN_PE13 (0x80 + 13)
#define AT91_PIN_PE14 (0x80 + 14)
#define AT91_PIN_PE15 (0x80 + 15)
#define AT91_PIN_PE16 (0x80 + 16)
#define AT91_PIN_PE17 (0x80 + 17)
#define AT91_PIN_PE18 (0x80 + 18)
#define AT91_PIN_PE19 (0x80 + 19)
#define AT91_PIN_PE20 (0x80 + 20)
#define AT91_PIN_PE21 (0x80 + 21)
#define AT91_PIN_PE22 (0x80 + 22)
#define AT91_PIN_PE23 (0x80 + 23)
#define AT91_PIN_PE24 (0x80 + 24)
#define AT91_PIN_PE25 (0x80 + 25)
#define AT91_PIN_PE26 (0x80 + 26)
#define AT91_PIN_PE27 (0x80 + 27)
#define AT91_PIN_PE28 (0x80 + 28)
#define AT91_PIN_PE29 (0x80 + 29)
#define AT91_PIN_PE30 (0x80 + 30)
#define AT91_PIN_PE31 (0x80 + 31)
#ifndef __ASSEMBLY__
/* setup setup routines, called from board init or driver probe() */
extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
/* callable at any time */
extern int at91_set_gpio_value(unsigned pin, int value);
extern int at91_get_gpio_value(unsigned pin);
/* callable only from core power-management code */
extern void at91_gpio_suspend(void);
extern void at91_gpio_resume(void);
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#else
static inline void at91_pinctrl_gpio_suspend(void) {}
static inline void at91_pinctrl_gpio_resume(void) {}
#endif
#endif /* __ASSEMBLY__ */
#endif

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arch/arm/mach-at91/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-at91/include/mach/hardware.h
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
/* DBGU base */
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
#define AT91_BASE_DBGU0 0xfffff200
/* 9263, 9g45 */
#define AT91_BASE_DBGU1 0xffffee00
#if defined(CONFIG_ARCH_AT91X40)
#include <mach/at91x40.h>
#else
#include <mach/at91rm9200.h>
#include <mach/at91sam9260.h>
#include <mach/at91sam9261.h>
#include <mach/at91sam9263.h>
#include <mach/at91sam9rl.h>
#include <mach/at91sam9g45.h>
#include <mach/at91sam9x5.h>
#include <mach/at91sam9n12.h>
/*
* On all at91 except rm9200 and x40 have the System Controller starts
* at address 0xffffc000 and has a size of 16KiB.
*
* On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
* at 0xfffff000
*
* Removes the individual definitions of AT91_BASE_SYS and
* replaces them with a common version at base 0xfffffc000 and size 16KiB
* and map the same memory space
*/
#define AT91_BASE_SYS 0xffffc000
#endif
/*
* On all at91 have the Advanced Interrupt Controller starts at address
* 0xfffff000 and the Power Management Controller starts at 0xfffffc00
*/
#define AT91_AIC 0xfffff000
#define AT91_PMC 0xfffffc00
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#ifdef CONFIG_MMU
/*
* Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
* to 0xFEF78000 .. 0xFF000000. (544Kb)
*/
#define AT91_IO_PHYS_BASE 0xFFF78000
#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
#else
/*
* Identity mapping for the non MMU case.
*/
#define AT91_IO_PHYS_BASE AT91_BASE_SYS
#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
#endif
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
/* Convert a physical IO address to virtual IO address */
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
/*
* Virtual to Physical Address mapping for IO devices.
*/
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
/* Internal SRAM is mapped below the IO devices */
#define AT91_SRAM_MAX SZ_1M
#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
/* External Memory Map */
#define AT91_CHIPSELECT_0 0x10000000
#define AT91_CHIPSELECT_1 0x20000000
#define AT91_CHIPSELECT_2 0x30000000
#define AT91_CHIPSELECT_3 0x40000000
#define AT91_CHIPSELECT_4 0x50000000
#define AT91_CHIPSELECT_5 0x60000000
#define AT91_CHIPSELECT_6 0x70000000
#define AT91_CHIPSELECT_7 0x80000000
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#endif

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arch/arm/mach-at91/include/mach/io.h Normal file
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/*
* arch/arm/mach-at91/include/mach/io.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) __typesafe_io(a)
#endif

26
arch/arm/mach-at91/include/mach/memory.h Normal file
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/*
* arch/arm/mach-at91/include/mach/memory.h
*
* Copyright (C) 2004 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <mach/hardware.h>
#endif

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arch/arm/mach-at91/include/mach/sama5d3.h Normal file
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/*
* Chip-specific header file for the SAMA5D3 family
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Common definitions.
* Based on SAMA5D3 datasheet.
*
* Licensed under GPLv2 or later.
*/
#ifndef SAMA5D3_H
#define SAMA5D3_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
#define AT91_ID_PIT 3 /* PIT */
#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */
#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */
#define SAMA5D3_ID_PIOA 6 /* PIOA */
#define SAMA5D3_ID_PIOB 7 /* PIOB */
#define SAMA5D3_ID_PIOC 8 /* PIOC */
#define SAMA5D3_ID_PIOD 9 /* PIOD */
#define SAMA5D3_ID_PIOE 10 /* PIOE */
#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */
#define SAMA5D3_ID_USART0 12 /* USART0 */
#define SAMA5D3_ID_USART1 13 /* USART1 */
#define SAMA5D3_ID_USART2 14 /* USART2 */
#define SAMA5D3_ID_USART3 15 /* USART3 */
#define SAMA5D3_ID_UART0 16 /* UART 0 */
#define SAMA5D3_ID_UART1 17 /* UART 1 */
#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */
#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */
#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */
#define SAMA5D3_ID_HSMCI0 21 /* MCI */
#define SAMA5D3_ID_HSMCI1 22 /* MCI */
#define SAMA5D3_ID_HSMCI2 23 /* MCI */
#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */
#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */
#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */
#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */
#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */
#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */
#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */
#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */
#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */
#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */
#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */
#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */
#define SAMA5D3_ID_LCDC 36 /* LCD Controller */
#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */
#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */
#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */
#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */
#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */
#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */
#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */
#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */
#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
/*
* Internal Memory
*/
#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */
#endif

27
arch/arm/mach-at91/include/mach/system_rev.h Normal file
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/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __ARCH_SYSTEM_REV_H__
#define __ARCH_SYSTEM_REV_H__
#include <asm/system_info.h>
/*
* board revision encoding
* mach specific
* the 16-31 bit are reserved for at91 generic information
*
* bit 31:
* 0 => nand 8 bit
* 1 => nand 16 bit
*/
#define BOARD_HAVE_NAND_16BIT (1 << 31)
static inline int board_have_nand_16bit(void)
{
return (system_rev & BOARD_HAVE_NAND_16BIT) ? 1 : 0;
}
#endif /* __ARCH_SYSTEM_REV_H__ */

37
arch/arm/mach-at91/include/mach/timex.h Normal file
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/*
* arch/arm/mach-at91/include/mach/timex.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#include <mach/hardware.h>
#ifdef CONFIG_ARCH_AT91X40
#define AT91X40_MASTER_CLOCK 40000000
#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
#else
#define CLOCK_TICK_RATE 12345678
#endif
#endif /* __ASM_ARCH_TIMEX_H */

199
arch/arm/mach-at91/include/mach/uncompress.h Normal file
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@@ -0,0 +1,199 @@
/*
* arch/arm/mach-at91/include/mach/uncompress.h
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <linux/io.h>
#include <linux/atmel_serial.h>
#include <mach/hardware.h>
#include <mach/at91_dbgu.h>
#include <mach/cpu.h>
void __iomem *at91_uart;
#if !defined(CONFIG_ARCH_AT91X40)
static const u32 uarts_rm9200[] = {
AT91_BASE_DBGU0,
AT91RM9200_BASE_US0,
AT91RM9200_BASE_US1,
AT91RM9200_BASE_US2,
AT91RM9200_BASE_US3,
0,
};
static const u32 uarts_sam9260[] = {
AT91_BASE_DBGU0,
AT91SAM9260_BASE_US0,
AT91SAM9260_BASE_US1,
AT91SAM9260_BASE_US2,
AT91SAM9260_BASE_US3,
AT91SAM9260_BASE_US4,
AT91SAM9260_BASE_US5,
0,
};
static const u32 uarts_sam9261[] = {
AT91_BASE_DBGU0,
AT91SAM9261_BASE_US0,
AT91SAM9261_BASE_US1,
AT91SAM9261_BASE_US2,
0,
};
static const u32 uarts_sam9263[] = {
AT91_BASE_DBGU1,
AT91SAM9263_BASE_US0,
AT91SAM9263_BASE_US1,
AT91SAM9263_BASE_US2,
0,
};
static const u32 uarts_sam9g45[] = {
AT91_BASE_DBGU1,
AT91SAM9G45_BASE_US0,
AT91SAM9G45_BASE_US1,
AT91SAM9G45_BASE_US2,
AT91SAM9G45_BASE_US3,
0,
};
static const u32 uarts_sam9rl[] = {
AT91_BASE_DBGU0,
AT91SAM9RL_BASE_US0,
AT91SAM9RL_BASE_US1,
AT91SAM9RL_BASE_US2,
AT91SAM9RL_BASE_US3,
0,
};
static const u32 uarts_sam9x5[] = {
AT91_BASE_DBGU0,
AT91SAM9X5_BASE_USART0,
AT91SAM9X5_BASE_USART1,
AT91SAM9X5_BASE_USART2,
0,
};
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{
u32 cidr, socid;
cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
socid = cidr & ~AT91_CIDR_VERSION;
switch (socid) {
case ARCH_ID_AT91RM9200:
return uarts_rm9200;
case ARCH_ID_AT91SAM9G20:
case ARCH_ID_AT91SAM9260:
return uarts_sam9260;
case ARCH_ID_AT91SAM9261:
return uarts_sam9261;
case ARCH_ID_AT91SAM9263:
return uarts_sam9263;
case ARCH_ID_AT91SAM9G45:
return uarts_sam9g45;
case ARCH_ID_AT91SAM9RL64:
return uarts_sam9rl;
case ARCH_ID_AT91SAM9X5:
return uarts_sam9x5;
}
/* at91sam9g10 */
if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
return uarts_sam9261;
}
/* at91sam9xe */
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
return uarts_sam9260;
}
return NULL;
}
static inline void arch_decomp_setup(void)
{
int i = 0;
const u32* usarts;
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
if (!usarts)
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
if (!usarts) {
at91_uart = NULL;
return;
}
do {
/* physical address */
at91_uart = (void __iomem *)usarts[i];
if (__raw_readl(at91_uart + ATMEL_US_BRGR))
return;
i++;
} while (usarts[i]);
at91_uart = NULL;
}
#else
static inline void arch_decomp_setup(void)
{
at91_uart = NULL;
}
#endif
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
*/
static void putc(int c)
{
if (!at91_uart)
return;
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
barrier();
__raw_writel(c, at91_uart + ATMEL_US_THR);
}
static inline void flush(void)
{
if (!at91_uart)
return;
/* wait for transmission to complete */
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
barrier();
}
#endif