nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
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35
Documentation/devicetree/bindings/usb/am33xx-usb.txt Normal file
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AM33XX MUSB GLUE
- compatible : Should be "ti,musb-am33xx"
- reg : offset and length of register sets, first usbss, then for musb instances
- interrupts : usbss, musb instance interrupts in order
- ti,hwmods : must be "usb_otg_hs"
- multipoint : Should be "1" indicating the musb controller supports
multipoint. This is a MUSB configuration-specific setting.
- num-eps : Specifies the number of endpoints. This is also a
MUSB configuration-specific setting. Should be set to "16"
- ram-bits : Specifies the ram address size. Should be set to "12"
- port0-mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
represents PERIPHERAL.
- port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
represents PERIPHERAL.
- power : Should be "250". This signifies the controller can supply upto
500mA when operating in host mode.
Example:
usb@47400000 {
compatible = "ti,musb-am33xx";
reg = <0x47400000 0x1000 /* usbss */
0x47401000 0x800 /* musb instance 0 */
0x47401800 0x800>; /* musb instance 1 */
interrupts = <17 /* usbss */
18 /* musb instance 0 */
19>; /* musb instance 1 */
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
port0-mode = <3>;
port1-mode = <3>;
power = <250>;
ti,hwmods = "usb_otg_hs";
};

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Atmel SOC USB controllers
OHCI
Required properties:
- compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
used in host mode.
- num-ports: Number of ports.
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
activated for the bus to be powered.
- atmel,oc-gpio: If present, specifies a gpio that needs to be
activated for the overcurrent detection.
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 4>;
num-ports = <2>;
};
EHCI
Required properties:
- compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
used in host mode.
usb1: ehci@00800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 4>;
};
AT91 USB device controller
Required properties:
- compatible: Should be "atmel,at91rm9200-udc"
- reg: Address and length of the register set for the device
- interrupts: Should contain macb interrupt
Optional properties:
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
activated for the bus to be powered.
usb1: gadget@fffa4000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 4>;
atmel,vbus-gpio = <&pioC 5 0>;
};

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* Freescale i.MX ci13xxx usb controllers
Required properties:
- compatible: Should be "fsl,imx27-usb"
- reg: Should contain registers location and length
- interrupts: Should contain controller interrupt
Optional properties:
- fsl,usbphy: phandler of usb phy that connects to the only one port
- fsl,usbmisc: phandler of non-core register device, with one argument
that indicate usb controller index
- vbus-supply: regulator for vbus
- disable-over-current: disable over current detect
- external-vbus-divider: enables off-chip resistor divider for Vbus
Examples:
usb@02184000 { /* USB OTG */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
disable-over-current;
external-vbus-divider;
};

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synopsys DWC3 CORE
DWC3- USB3 CONTROLLER
Required properties:
- compatible: must be "synopsys,dwc3"
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
- usb-phy : array of phandle for the PHY device
Optional properties:
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
This is usually a subnode to DWC3 glue to which it is connected.
dwc3@4a030000 {
compatible = "synopsys,dwc3";
reg = <0x4a030000 0xcfff>;
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
tx-fifo-resize;
};

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OMAP HS USB EHCI controller
This device is usually the child of the omap-usb-host
Documentation/devicetree/bindings/mfd/omap-usb-host.txt
Required properties:
- compatible: should be "ti,ehci-omap"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line
Optional properties:
- phys: list of phandles to PHY nodes.
This property is required if at least one of the ports are in
PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY
To specify the port mode, see
Documentation/devicetree/bindings/mfd/omap-usb-host.txt
Example for OMAP4:
usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap", "usb-ehci";
reg = <0x4a064c00 0x400>;
interrupts = <0 77 0x4>;
};
&usbhsehci {
phys = <&hsusb1_phy 0 &hsusb3_phy>;
};

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* EHCI controller, Orion Marvell variants
Required properties:
- compatible: must be "marvell,orion-ehci"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The EHCI interrupt
Example:
ehci@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x1000>;
interrupts = <19>;
};

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Samsung Exynos SoC USB controller
The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.
EHCI
Required properties:
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
EHCI controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
needs to be pulled up for the bus to be powered.
Example:
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
clocks = <&clock 285>;
clock-names = "usbhost";
};
OHCI
Required properties:
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
OHCI companion controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Example:
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
};

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Freescale SOC USB controllers
The device node for a USB controller that is part of a Freescale
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "fsl-usb2-mph" for multi port host USB
controllers, or "fsl-usb2-dr" for dual role USB controllers
or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121
- phy_type : For multi port host USB controllers, should be one of
"ulpi", or "serial". For dual role USB controllers, should be
one of "ulpi", "utmi", "utmi_wide", or "serial".
- reg : Offset and length of the register set for the device
- port0 : boolean; if defined, indicates port0 is connected for
fsl-usb2-mph compatible controllers. Either this property or
"port1" (or both) must be defined for "fsl-usb2-mph" compatible
controllers.
- port1 : boolean; if defined, indicates port1 is connected for
fsl-usb2-mph compatible controllers. Either this property or
"port0" (or both) must be defined for "fsl-usb2-mph" compatible
controllers.
- dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
controllers. Can be "host", "peripheral", or "otg". Default to
"host" if not defined for backward compatibility.
Recommended properties :
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
Optional properties :
- fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the
port power polarity of internal PHY signal DRVVBUS is inverted.
- fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates
the PWR_FAULT signal polarity is inverted.
Example multi port host USB controller device node :
usb@22000 {
compatible = "fsl-usb2-mph";
reg = <22000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <27 1>;
phy_type = "ulpi";
port0;
port1;
};
Example dual role USB controller device node :
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <23000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <26 1>;
dr_mode = "otg";
phy = "ulpi";
};
Example dual role USB controller device node for MPC5121ADS:
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = < &ipic >;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
fsl,invert-drvvbus;
fsl,invert-pwr-fault;
};

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Generic USB Properties
Optional properties:
- maximum-speed: tells USB controllers we want to work up to a certain
speed. Valid arguments are "super-speed", "high-speed",
"full-speed" and "low-speed". In case this isn't passed
via DT, USB controllers should default to their maximum
HW capability.
- dr_mode: tells Dual-Role USB controllers that we want to work on a
particular mode. Valid arguments are "host",
"peripheral" and "otg". In case this attribute isn't
passed via DT, USB DRD controllers should default to
OTG.
This is an attribute to a USB controller such as:
dwc3@4a030000 {
compatible = "synopsys,dwc3";
reg = <0x4a030000 0xcfff>;
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
maximum-speed = "super-speed";
dr_mode = "otg";
};

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* NXP ISP1301 USB transceiver
Required properties:
- compatible: must be "nxp,isp1301"
- reg: I2C address of the ISP1301 device
Optional properties of devices using ISP1301:
- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the
ISP1301 instance associated with the respective USB driver
Example:
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
transceiver = <&isp1301>;
status = "okay";
};

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* NXP LPC32xx SoC USB Device Controller (UDC)
Required properties:
- compatible: Must be "nxp,lpc3220-udc"
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupts: The USB interrupts:
* USB Device Low Priority Interrupt
* USB Device High Priority Interrupt
* USB Device DMA Interrupt
* External USB Transceiver Interrupt (OTG ATX)
- transceiver: phandle of the associated ISP1301 device - this is necessary for
the UDC controller for connecting to the USB physical layer
Example:
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
transceiver = <&isp1301>;
};

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* Freescale MXS USB Phy Device
Required properties:
- compatible: Should be "fsl,imx23-usbphy"
- reg: Should contain registers location and length
- interrupts: Should contain phy interrupt
Example:
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
};

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Tegra SOC XHCI controller
The device node for the Tegra XHCI host controller.
Required properties:
- compatible: Should be "nvidia,tegra114-xhci" or "nvidia,tegra124-xhci" for
XHCI controllers used in host mode.
- reg: Address and length of the register sets. There should be three
entries in the following order: XHCI host registers, FPCI registers, and
IPFS registers.
- interrupts: Interrupts used by the controller. There should be two
entries in the following order: XHCI host interrupt and firmware mailbox
interrupt.
- clocks: Handles to XUSB host, falcon, and EMC clocks.
- clock-names: Should be "xusb_host", "xusb_falcon_src", and "xusb.emc"
respectively.
- nvidia,xusb-phy: Handle to the corresponding XUSB PHY.
- s1p05v-supply: 1.05V supply regulator.
- s1p8v-supply: 1.8V supply regulator.
- s3p3v-supply: 3.3V supply regulator.
Example:
usb@70090000 {
compatible = "nvidia,tegra124-xhci";
reg = <0x0 0x70090000 0x8000>,
<0x0 0x70098000 0x1000>,
<0x0 0x70099000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_EMC>;
clock-names = "xusb_host", "xusb_falcon_src", "xusb.emc";
nvidia,xusb-phy = <&xusb_phy>;
s3p3v-supply = <&_3v3_lp0>;
s1p8v-supply = <&vddio_1v8>;
s1p05v-supply = <&avdd_hdmi_pex>;
status = "okay";
};

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Tegra SOC XUSB PHY
The device node for the Tegra SOC XUSB PHY:
Required properties:
- compatible: Should be "nvidia,tegra114-xusb-phy" or
"nvidia,tegra124-xusb-phy".
- reg: Address and length of the register sets. There should be two
entries in the following order: XUSB_PADCTL registers and USB2.0 PHY
registers.
- interrupts: PADCTL interrupt, used for wake from runtime and LP0 suspend.
- clocks: Handles to XUSB SS, SS source, PLL_U_480M, CLK_M, and pad clocks.
- clock-names: Should be "xusb_ss", "xusb_ss_src", "pll_u_480M", "clk_m",
and "pad_clk" respectively.
- nvidia,pmc: Handle to the PMC syscon node.
- nvidia,clkrst: Handle to the clock-reset module syscon node.
- nvidia,ss-pads: Bitmap of enabled SuperSpeed pads:
bit 0 - SuperSpeed port 0
bit 1 - SuperSpeed port 1
- nvidia,utmi-pads: Bitmap of enabled USB2.0 UTMI pads:
bit 0 - UTMI port 0
bit 1 - UTMI port 1
bit 2 - UTMI port 2
- nvidia,hsic-pads: Bitmap of enabled USB2.0 HSIC pads:
bit 0 - HSIC port 0
bit 1 - HSIC port 1
- nvidia,hsic{0,1}-config: byte array with 9 elements specifiying the
configuration for the corresponding HISC port:
byte 0 - rx_strobe_trim
byte 1 - rx_data_trim
byte 2 - tx_rtune_n
byte 3 - tx_rtune_p
byte 4 - tx_slew_n
byte 5 - tx_slew_p
byte 6 - auto_term_en
byte 7 - strb_trim_val
byte 8 - pretend_connect
Only required for enabled HISC ports.
- nvidia,ss-portmap: Mapping from SS ports to their corresponding USB2.0 port:
bits 3-0 - SuperSpeed port 0
bits 7-4 - SuperSpeed port 1
Both fields have valid values from 0 to 2 (USB2.0 ports 0, 1, 2).
- nvidia,lane-owner: Program ownership of lanes owned by USB3.0:
bit 0 - set when super-speed port 1 uses SATA lane. Valid for Tegra124.
= 0 (SATA lane owner = SATA)
= 1 (SATA lane owner = USB3_SS port1)
bit 1 - set when super-speed port 0 uses PCIe lane 0 (always).
= 0 (PCIe lane0 owner = PCIe),
= 1 (PCIe lane0 owner = USB3_SS port0)
bit 2 - set when super-speed port 1 uses PCIe lane 1.
= 0 (PCIe lane1 owner = PCIe),
= 1 (PCIe lane1 owner = USB3_SS port1)
- vbus{1,2,3}-supply: VBUS regulator for the corresponding UTMI pad.
Only required when the respective UTMI pad is enabled.
- vddio-hsic-supply: HSIC supply regulator. Only required when HSIC ports
are enabled.
Optional properties:
- nvidia,xusb-hs-xcvr-setup-offset: used for high-speed transceiver setup
and for data eye swing.
bit 7-0: for PAD0 (port0)
bit 15-8: for PAD1 (port1)
bit 23-16: for PAD2 (port2)
USB parameter HS_CURR_LEVEL is calibrated and fused. Software reads
the fuse value and programs it to the correct level.
Actual product may have additional losses on the PCB (connectors).
This reduces the actual signal at the USB connector.
Software has the option of adding an offset to the FUSE value before
it is programmed to register.
Programmed value = Fuse value + Offset
This corrects any losses.
The objective is to get the data eye swing as close as possible to 400mv
without falling below the mark under typical operating conditions.
Offset (nvidia,xusb-hs-xcvr-setup-offset) is design dependant
(PCB type, length of PCB, switches used, etc).
If "nvidia,xusb-hs-xcvr-setup-offset" is not defined or has
value 0 for the pad, then
Programmed value = Fuse value
usb@70090000 {
...
nvidia,xusb-phy = <&xusb_phy>;
...
};
xusb_phy: phy@7009f000 {
compatible = "nvidia,tegra124-xusb-phy";
reg = <0x0 0x7009f000 0x1000>,
<0x0 0x7000e400 0x800>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_XUSB_SS>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
<&tegra_car TEGRA124_CLK_CLK_M>,
<&tegra_car TEGRA124_CLK_USBD>;
clock-names = "xusb_ss", "xusb_ss_src", "pll_u_480M",
"clk_m", "pad_clk";
nvidia,pmc = <&pmc>;
nvidia,clkrst = <&tegra_car>;
nvidia,ss-pads = <0x3>; /* SSP0, SSP1 */
nvidia,hsic-pads = <0x0>;
nvidia,utmi-pads = <0x7>; /* USB2P0, USB2P1, USB2P2 */
nvidia,ss-portmap = <0x20>; /* SSP0->USB2P0, SSP1->USB2P2 */
nvidia,lane-owner = <0x6>; /* USB3P0 USB3P1 */
vbus1-supply = <&usb1_vbus_reg>;
vbus2-supply = <&run_cam_2v8>;
vbus3-supply = <&usb3_vbus_reg>;
vddio-hsic-supply = <&gen_avdd_1v2>;
nvidia,xusb-hs-xcvr-setup-offset = <0x020004>;
};

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Tegra SOC USB controllers
The device node for a USB controller that is part of a Tegra
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "nvidia,tegra20-ehci" for USB controllers
used in host mode.
- phy_type : Should be one of "ulpi" or "utmi".
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
activated for the bus to be powered.
- nvidia,phy : phandle of the PHY instance, the controller is connected to.
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
Optional properties:
- dr_mode : dual role mode. Indicates the working mode for
nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral",
or "otg". Default to "host" if not defined for backward compatibility.
host means this is a host controller
peripheral means it is device controller
otg means it can operate as either ("on the go")
- nvidia,has-legacy-mode : boolean indicates whether this controller can
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
registers are accessed through the APB_MISC base address instead of
the USB controller. Since this is a legacy issue it probably does not
warrant a compatible string of its own.
- nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
USB ports, which need reset twice due to hardware issues.

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Tegra SOC USB PHY
The device node for Tegra SOC USB PHY:
Required properties :
- compatible : Should be "nvidia,tegra20-usb-phy".
- reg : Address and length of the register set for the USB PHY interface.
- phy_type : Should be one of "ulpi" or "utmi".
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
Optional properties:
- nvidia,has-legacy-mode : boolean indicates whether this controller can
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
registers are accessed through the APB_MISC base address instead of
the USB controller.

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* OHCI controller, NXP ohci-nxp variant
Required properties:
- compatible: must be "nxp,ohci-nxp"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The OHCI interrupt
- transceiver: phandle of the associated ISP1301 device - this is necessary for
the UDC controller for connecting to the USB physical layer
Example (LPC32xx):
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
ohci@31020000 {
compatible = "nxp,ohci-nxp";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3b 0>;
transceiver = <&isp1301>;
};

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OMAP HS USB OHCI controller (OMAP3 and later)
Required properties:
- compatible: should be "ti,ohci-omap3"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line
Example for OMAP4:
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3", "usb-ohci";
reg = <0x4a064800 0x400>;
interrupts = <0 76 0x4>;
};

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OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
OMAP MUSB GLUE
- compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
- ti,hwmods : must be "usb_otg_hs"
- ti,has-mailbox : to specify that omap uses an external mailbox
(in control module) to communicate with the musb core during device connect
and disconnect.
- multipoint : Should be "1" indicating the musb controller supports
multipoint. This is a MUSB configuration-specific setting.
- num-eps : Specifies the number of endpoints. This is also a
MUSB configuration-specific setting. Should be set to "16"
- ram-bits : Specifies the ram address size. Should be set to "12"
- interface-type : This is a board specific setting to describe the type of
interface between the controller and the phy. It should be "0" or "1"
specifying ULPI and UTMI respectively.
- mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
represents PERIPHERAL.
- power : Should be "50". This signifies the controller can supply upto
100mA when operating in host mode.
- usb-phy : the phandle for the PHY device
Optional properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = "ti,omap4-musb";
ti,hwmods = "usb_otg_hs";
ti,has-mailbox;
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
ctrl-module = <&omap_control_usb>;
};
Board specific device node entry
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
OMAP DWC3 GLUE
- compatible : Should be "ti,dwc3"
- ti,hwmods : Should be "usb_otg_ss"
- reg : Address and length of the register set for the device.
- interrupts : The irq number of this device that is used to interrupt the
MPU
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
It should be set to "1" for HW mode and "2" for SW mode.
- ranges: the child address space are mapped 1:1 onto the parent address space
Sub-nodes:
The dwc3 core should be added as subnode to omap dwc3 glue.
- dwc3 :
The binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt
omap_dwc3 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss";
reg = <0x4a020000 0x1ff>;
interrupts = <0 93 4>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
};
OMAP CONTROL USB
Required properties:
- compatible: Should be "ti,omap-control-usb"
- reg : Address and length of the register set for the device. It contains
the address of "control_dev_conf" and "otghs_control" or "phy_power_usb"
depending upon omap4 or omap5.
- reg-names: The names of the register addresses corresponding to the registers
filled in "reg".
- ti,type: This is used to differentiate whether the control module has
usb mailbox or usb3 phy power. omap4 has usb mailbox in control module to
notify events to the musb core and omap5 has usb3 phy power register to
power on usb3 phy. Should be "1" if it has mailbox and "2" if it has usb3
phy power.
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,omap-control-usb";
reg = <0x4a002300 0x4>,
<0x4a00233c 0x4>;
reg-names = "control_dev_conf", "otghs_control";
ti,type = <1>;
};

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Generic Platform UHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "platform-uhci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
Example:
uhci@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
};

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PXA USB controllers
OHCI
Required properties:
- compatible: Should be "marvell,pxa-ohci" for USB controllers
used in host mode.
Optional properties:
- "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
If present, enables the appropriate USB port of the controller.
- "marvell,port-mode" selects the mode of the ports:
1 = PMM_NPS_MODE
2 = PMM_GLOBAL_MODE
3 = PMM_PERPORT_MODE
- "marvell,power-sense-low" - power sense pin is low-active.
- "marvell,power-control-low" - power control pin is low-active.
- "marvell,no-oc-protection" - disable over-current protection.
- "marvell,oc-mode-perport" - enable per-port over-current protection.
- "marvell,power_on_delay" Power On to Power Good time - in ms.
Example:
usb0: ohci@4c000000 {
compatible = "marvell,pxa-ohci", "usb-ohci";
reg = <0x4c000000 0x100000>;
interrupts = <18>;
marvell,enable-port1;
marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
};

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SAMSUNG USB-PHY controllers
** Samsung's usb 2.0 phy transceiver
The Samsung's usb 2.0 phy transceiver is used for controlling
usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
usb controllers across Samsung SOCs.
TODO: Adding the PHY binding with controller(s) according to the under
development generic PHY driver.
Required properties:
Exynos4210:
- compatible : should be "samsung,exynos4210-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clock correseponding IDs clock property as requested
by the controller driver.
Exynos5250:
- compatible : should be "samsung,exynos5250-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
Optional properties:
- #address-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- #size-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- ranges: allows valid translation between child's address space and parent's
address space.
- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
interface for usb-phy. It should provide the following information required by
usb-phy controller to control phy.
- reg : base physical address of PHY_CONTROL registers.
The size of this register is the total sum of size of all PHY_CONTROL
registers that the SoC has. For example, the size will be
'0x4' in case we have only one PHY_CONTROL register (e.g.
OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
and, '0x8' in case we have two PHY_CONTROL registers (e.g.
USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
and so on.
Example:
- Exynos4210
usbphy@125B0000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "samsung,exynos4210-usb2phy";
reg = <0x125B0000 0x100>;
ranges;
clocks = <&clock 2>, <&clock 305>;
clock-names = "xusbxti", "otg";
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = <0x10020704 0x8>;
};
};
** Samsung's usb 3.0 phy transceiver
Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
controllers across Samsung SOCs.
Required properties:
Exynos5250:
- compatible : should be "samsung,exynos5250-usb3phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clocks correseponding to IDs in the clock property
as requested by the controller driver.
Optional properties:
- #address-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- #size-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- ranges: allows valid translation between child's address space and parent's
address space.
- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
interface for usb-phy. It should provide the following information required by
usb-phy controller to control phy.
- reg : base physical address of PHY_CONTROL registers.
The size of this register is the total sum of size of all PHY_CONTROL
registers that the SoC has. For example, the size will be
'0x4' in case we have only one PHY_CONTROL register (e.g.
OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
and, '0x8' in case we have two PHY_CONTROL registers (e.g.
USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
and so on.
Example:
usbphy@12100000 {
compatible = "samsung,exynos5250-usb3phy";
reg = <0x12100000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&clock 1>, <&clock 286>;
clock-names = "ext_xtal", "usbdrd30";
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = <0x10040704 0x8>;
};
};

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ST SPEAr SoC USB controllers:
-----------------------------
EHCI:
-----
Required properties:
- compatible: "st,spear600-ehci"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the EHCI interrupt
Example:
ehci@e1800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <27>;
};
OHCI:
-----
Required properties:
- compatible: "st,spear600-ohci"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the OHCI interrupt
Example:
ohci@e1900000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <26>;
};

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USB COMPARATOR OF TWL CHIPS
TWL6030 USB COMPARATOR
- compatible : Should be "ti,twl6030-usb"
- interrupts : Two interrupt numbers to the cpu should be specified. First
interrupt number is the otg interrupt number that raises ID interrupts when
the controller has to act as host and the second interrupt number is the
usb interrupt number that raises VBUS interrupts when the controller has to
act as device
- usb-supply : phandle to the regulator device tree node. It should be vusb
if it is twl6030 or ldousb if it is twl6025 subclass.
twl6030-usb {
compatible = "ti,twl6030-usb";
interrupts = < 4 10 >;
};
Board specific device node entry
&twl6030-usb {
usb-supply = <&vusb>;
};
TWL4030 USB PHY AND COMPARATOR
- compatible : Should be "ti,twl4030-usb"
- interrupts : The interrupt numbers to the cpu should be specified. First
interrupt number is the otg interrupt number that raises ID interrupts
and VBUS interrupts. The second interrupt number is optional.
- <supply-name>-supply : phandle to the regulator device tree node.
<supply-name> should be vusb1v5, vusb1v8 and vusb3v1
- usb_mode : The mode used by the phy to connect to the controller. "1"
specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
twl4030-usb {
compatible = "ti,twl4030-usb";
interrupts = < 10 4 >;
usb1v5-supply = <&vusb1v5>;
usb1v8-supply = <&vusb1v8>;
usb3v1-supply = <&vusb3v1>;
usb_mode = <1>;
};

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USB EHCI controllers
Required properties:
- compatible : should be "usb-ehci".
- reg : should contain at least address and length of the standard EHCI
register set for the device. Optional platform-dependent registers
(debug-port or other) can be also specified here, but only after
definition of standard EHCI registers.
- interrupts : one EHCI interrupt should be described here.
If device registers are implemented in big endian mode, the device
node should have "big-endian-regs" property.
If controller implementation operates with big endian descriptors,
"big-endian-desc" property should be specified.
If both big endian registers and descriptors are used by the controller
implementation, "big-endian" property can be specified instead of having
both "big-endian-regs" and "big-endian-desc".
Example (Sequoia 440EPx):
ehci@e0000300 {
compatible = "ibm,usb-ehci-440epx", "usb-ehci";
interrupt-parent = <&UIC0>;
interrupts = <1a 4>;
reg = <0 e0000300 90 0 e0000390 70>;
big-endian;
};

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USB NOP PHY
Required properties:
- compatible: should be usb-nop-xceiv
Optional properties:
- clocks: phandle to the PHY clock. Use as per Documentation/devicetree
/bindings/clock/clock-bindings.txt
This property is required if clock-frequency is specified.
- clock-names: Should be "main_clk"
- clock-frequency: the clock frequency (in Hz) that the PHY clock must
be configured to.
- vcc-supply: phandle to the regulator that provides RESET to the PHY.
- reset-supply: phandle to the regulator that provides power to the PHY.
Example:
hsusb1_phy {
compatible = "usb-nop-xceiv";
clock-frequency = <19200000>;
clocks = <&osc 0>;
clock-names = "main_clk";
vcc-supply = <&hsusb1_vcc_regulator>;
reset-supply = <&hsusb1_reset_regulator>;
};
hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
hsusb1_vcc_regulator provides power to the PHY and hsusb1_reset_regulator
controls RESET.

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USB PHY
OMAP USB2 PHY
Required properties:
- compatible: Should be "ti,omap-usb2"
- reg : Address and length of the register set for the device.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb>;
};
OMAP USB3 PHY
Required properties:
- compatible: Should be "ti,omap-usb3"
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the registers
filled in "reg".
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
This is usually a subnode of ocp2scp to which it is connected.
usb3phy@4a084400 {
compatible = "ti,omap-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb>;
};

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SMSC USB3503 High-Speed Hub Controller
Required properties:
- compatible: Should be "smsc,usb3503".
- reg: Specifies the i2c slave address, it should be 0x08.
- connect-gpios: Should specify GPIO for connect.
- intn-gpios: Should specify GPIO for interrupt.
- reset-gpios: Should specify GPIO for reset.
- initial-mode: Should specify initial mode.
(1 for HUB mode, 2 for STANDBY mode)
Examples:
usb3503@08 {
compatible = "smsc,usb3503";
reg = <0x08>;
connect-gpios = <&gpx3 0 1>;
intn-gpios = <&gpx3 4 1>;
reset-gpios = <&gpx3 5 1>;
initial-mode = <1>;
};

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* Freescale i.MX non-core registers
Required properties:
- #index-cells: Cells used to descibe usb controller index. Should be <1>
- compatible: Should be one of below:
"fsl,imx6q-usbmisc" for imx6q
- reg: Should contain registers location and length
Examples:
usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
};

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VIA/Wondermedia VT8500 EHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-ehci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : ehci controller interrupt
Example:
ehci@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
interrupts = <43>;
};

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VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
Required properties:
- compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
- reg: Address range of the ehci registers. size should be 0x200
- interrupts: Should contain the ehci interrupt.
usb: ehci@D8007100 {
compatible = "wm,prizm-ehci", "usb-ehci";
reg = <0xD8007100 0x200>;
interrupts = <1>;
};