nathan/Chromebook-Device-Nyan-NVIDIA-Tegra-K1-T124-Upstream-Linux-3.10-LTS-Kernel
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Initial commit; kernel source import

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Nathan
2025-04-06 23:50:55 -05:00
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Tegra124 External Memory Controller
Properties:
- compatible : Should contain "nvidia,tegra124-emc".
- reg : Should contain the register range of the device
- #address-cells : Should be 1
- #size-cells : Should be 0
- nvidia,mc : phandle to the mc bus connected to EMC.
- clocks : phandle to EMC, EMC shared bus override, and all parent clocks.
- clock-names : name of each clock.
- nvidia,pmc : phandle to the PMC syscon node.
- max-clock-frequency : optional, specifies the maximum EMC rate in kHz.
Child device nodes describe the memory settings for different configurations and
clock rates.
Example:
memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x7001b000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
nvidia,mc = <&mc>;
nvidia,pmc = <&pmc>;
clocks = <&tegra_car TEGRA124_CLK_EMC>,
<&tegra_car TEGRA124_CLK_PLL_M>,
<&tegra_car TEGRA124_CLK_PLL_C>,
<&tegra_car TEGRA124_CLK_PLL_P>,
<&tegra_car TEGRA124_CLK_CLK_M>,
<&tegra_car TEGRA124_CLK_PLL_M_UD>,
<&tegra_car TEGRA124_CLK_PLL_C2>,
<&tegra_car TEGRA124_CLK_PLL_C3>,
<&tegra_car TEGRA124_CLK_PLL_C_UD>,
<&tegra_car TEGRA124_CLK_OVERRIDE_EMC>;
clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
"pll_m_ud", "pll_c2", "pll_c3", "pll_c_ud",
"emc_override";
};
External Memory Controller ram-code table
If the emc node has the nvidia,ram-code property present, then the next level
of nodes below the emc table are used to specify which settings apply for
which ram-code settings.
If the emc node lacks the nvidia,use-ram-code property, this level is omitted
and the tables are stored directly under the emc node (see below).
Properties:
- name : Should be emc-tables
- nvidia,ram-code : the binary representation of the ram-code board strappings
for which this node (and children) are valid.
External Memory Controller configuration table
This is a table containing the EMC register settings for the various operating
speeds of the memory controller. They are always located as subnodes of the emc
controller node.
Properties:
- compatible : Should contain "nvidia,tegra12-emc-table".
- clock-frequency : the clock frequency for the EMC at which this
table should be used (in KHz).
- nvidia,revision : The revision of emc table
- nvidia,emc-min-mv : min voltage
- nvidia,gk20a-min-mv : GPU min voltage
- nvidia,emc-src-sel-reg : CLK_SOURCE_EMC
- nvidia,burst-regs-num : number of emc burst regs
- nvidia,burst-up-down-regs-num : number of up_down regs
- nvidia,emc-zcal-wait-cnt : EMC_ZCAL_WAIT_CNT after clock change
- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL
- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
- nvidia,emc-cfg : EMC_CFG
- nvidia,emc-cfg-2 : EMC_CFG_2
- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
- nvidia,emc-cfg-dig-dll : EMC_CFG_DIG_DLL
- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
- nvidia,emc-auto-cal-config2 = EMC_AUTO_CAL_CONFIG2;
- nvidia,emc-auto-cal-config3 = EMC_AUTO_CAL_CONFIG3;
- nvidia,emc-auto-cal-config = EMC_AUTO_CAL_CONFIG;
- nvidia,emc-mode-reset : Mode Register 0
- nvidia,emc-mode-1 : Mode Register 1
- nvidia,emc-mode-2 : Mode Register 2
- nvidia,emc-mode-4 : Mode Register 4
- nvidia,emc-latency : expected dvfs latency (ns)
- nvidia,emc-registers : a 164 word array of EMC/MC registers to be
programmed for operation at the 'clock-frequency' setting.
The order and contents of the registers are:
EMC_RC, EMC_RFC, EMC_RFC_SLR, EMC_RAS, EMC_RP, EMC_R2W, EMC_W2R,
EMC_R2P, EMC_W2P, EMC_RD_RCD, EMC_WR_RCD, EMC_RRD, EMC_REXT, EMC_WEXT,
EMC_WDV, EMC_WDV_MASK, EMC_QUSE, EMC_QUSE_WIDTH, EMC_IBDLY, EMC_EINPUT,
EMC_EINPUT_DURATION, EMC_PUTERM_EXTRA, EMC_PUTERM_WIDTH,
EMC_PUTERM_ADJ, EMC_CDB_CNTL_1, EMC_CDB_CNTL_2, EMC_CDB_CNTL_3,
EMC_QSAFE, EMC_RDV, EMC_RDV_MASK, EMC_REFRESH, EMC_BURST_REFRESH_NUM,
EMC_PRE_REFRESH_REQ_CNT, EMC_PDEX2WR, EMC_PDEX2RD, EMC_PCHG2PDEN,
EMC_ACT2PDEN, EMC_AR2PDEN, EMC_RW2PDEN, EMC_TXSR, EMC_TXSRDLL,
EMC_TCKE, EMC_TCKESR, EMC_TPD, EMC_TFAW, EMC_TRPAB, EMC_TCLKSTABLE,
EMC_TCLKSTOP, EMC_TREFBW, EMC_FBIO_CFG6, EMC_ODT_WRITE, EMC_ODT_READ,
EMC_FBIO_CFG5, EMC_CFG_DIG_DLL, EMC_CFG_DIG_DLL_PERIOD,
EMC_DLL_XFORM_DQS0, EMC_DLL_XFORM_DQS1, EMC_DLL_XFORM_DQS2,
EMC_DLL_XFORM_DQS3, EMC_DLL_XFORM_DQS4, EMC_DLL_XFORM_DQS5,
EMC_DLL_XFORM_DQS6, EMC_DLL_XFORM_DQS7, EMC_DLL_XFORM_DQS8,
EMC_DLL_XFORM_DQS9, EMC_DLL_XFORM_DQS10, EMC_DLL_XFORM_DQS11,
EMC_DLL_XFORM_DQS12, EMC_DLL_XFORM_DQS13, EMC_DLL_XFORM_DQS14,
EMC_DLL_XFORM_DQS15, EMC_DLL_XFORM_QUSE0, EMC_DLL_XFORM_QUSE1,
EMC_DLL_XFORM_QUSE2, EMC_DLL_XFORM_QUSE3, EMC_DLL_XFORM_QUSE4,
EMC_DLL_XFORM_QUSE5, EMC_DLL_XFORM_QUSE6, EMC_DLL_XFORM_QUSE7,
EMC_DLL_XFORM_ADDR0, EMC_DLL_XFORM_ADDR1, EMC_DLL_XFORM_ADDR2,
EMC_DLL_XFORM_ADDR3, EMC_DLL_XFORM_ADDR4, EMC_DLL_XFORM_ADDR5,
EMC_DLL_XFORM_QUSE8, EMC_DLL_XFORM_QUSE9, EMC_DLL_XFORM_QUSE10,
EMC_DLL_XFORM_QUSE11, EMC_DLL_XFORM_QUSE12, EMC_DLL_XFORM_QUSE13,
EMC_DLL_XFORM_QUSE14, EMC_DLL_XFORM_QUSE15, EMC_DLI_TRIM_TXDQS0,
EMC_DLI_TRIM_TXDQS1, EMC_DLI_TRIM_TXDQS2, EMC_DLI_TRIM_TXDQS3,
EMC_DLI_TRIM_TXDQS4, EMC_DLI_TRIM_TXDQS5, EMC_DLI_TRIM_TXDQS6,
EMC_DLI_TRIM_TXDQS7, EMC_DLI_TRIM_TXDQS8, EMC_DLI_TRIM_TXDQS9,
EMC_DLI_TRIM_TXDQS10, EMC_DLI_TRIM_TXDQS11, EMC_DLI_TRIM_TXDQS12,
EMC_DLI_TRIM_TXDQS13, EMC_DLI_TRIM_TXDQS14, EMC_DLI_TRIM_TXDQS15,
EMC_DLL_XFORM_DQ0, EMC_DLL_XFORM_DQ1, EMC_DLL_XFORM_DQ2,
EMC_DLL_XFORM_DQ3, EMC_DLL_XFORM_DQ4, EMC_DLL_XFORM_DQ5,
EMC_DLL_XFORM_DQ6, EMC_DLL_XFORM_DQ7, EMC_XM2CMDPADCTRL,
EMC_XM2CMDPADCTRL4, EMC_XM2CMDPADCTRL5, EMC_XM2DQSPADCTRL2,
EMC_XM2DQPADCTRL2, EMC_XM2DQPADCTRL3, EMC_XM2CLKPADCTRL,
EMC_XM2CLKPADCTRL2, EMC_XM2COMPPADCTRL, EMC_XM2VTTGENPADCTRL,
EMC_XM2VTTGENPADCTRL2, EMC_XM2VTTGENPADCTRL3, EMC_XM2DQSPADCTRL3,
EMC_XM2DQSPADCTRL4, EMC_XM2DQSPADCTRL5, EMC_XM2DQSPADCTRL6,
EMC_DSR_VTTGEN_DRV, EMC_TXDSRVTTGEN, EMC_FBIO_SPARE, EMC_ZCAL_INTERVAL,
EMC_ZCAL_WAIT_CNT, EMC_MRS_WAIT_CNT, EMC_MRS_WAIT_CNT2,
EMC_CTT, EMC_CTT_DURATION, EMC_CFG_PIPE, EMC_DYN_SELF_REF_CONTROL,
EMC_QPOP, MC_EMEM_ARB_CFG, MC_EMEM_ARB_OUTSTANDING_REQ,
MC_EMEM_ARB_TIMING_RCD, MC_EMEM_ARB_TIMING_RP, MC_EMEM_ARB_TIMING_RC,
MC_EMEM_ARB_TIMING_RAS, MC_EMEM_ARB_TIMING_FAW, MC_EMEM_ARB_TIMING_RRD,
MC_EMEM_ARB_TIMING_RAP2PRE, MC_EMEM_ARB_TIMING_WAP2PRE,
MC_EMEM_ARB_TIMING_R2R, MC_EMEM_ARB_TIMING_W2W, MC_EMEM_ARB_TIMING_R2W,
MC_EMEM_ARB_TIMING_W2R, MC_EMEM_ARB_DA_TURNS, MC_EMEM_ARB_DA_COVERS,
MC_EMEM_ARB_MISC0, MC_EMEM_ARB_RING1_THROTTLE
- nvidia,emc-burst-up-down-regs : a 31 word array of EMC/MC registers to be
programmed for operation at the 'clock-frequency' setting.
The order and contents of the registers are:
MC_MLL_MPCORER_PTSA_RATE, MC_PTSA_GRANT_DECREMENT,
MC_LATENCY_ALLOWANCE_XUSB_0, MC_LATENCY_ALLOWANCE_XUSB_1,
MC_LATENCY_ALLOWANCE_TSEC_0, MC_LATENCY_ALLOWANCE_SDMMCA_0,
MC_LATENCY_ALLOWANCE_SDMMCAA_0, MC_LATENCY_ALLOWANCE_SDMMC_0,
MC_LATENCY_ALLOWANCE_SDMMCAB_0, MC_LATENCY_ALLOWANCE_PPCS_0,
MC_LATENCY_ALLOWANCE_PPCS_1, MC_LATENCY_ALLOWANCE_MPCORE_0,
MC_LATENCY_ALLOWANCE_MPCORELP_0, MC_LATENCY_ALLOWANCE_HC_0,
MC_LATENCY_ALLOWANCE_HC_1, MC_LATENCY_ALLOWANCE_AVPC_0,
MC_LATENCY_ALLOWANCE_GPU_0, MC_LATENCY_ALLOWANCE_MSENC_0,
MC_LATENCY_ALLOWANCE_HDA_0, MC_LATENCY_ALLOWANCE_VIC_0,
MC_LATENCY_ALLOWANCE_VI2_0, MC_LATENCY_ALLOWANCE_ISP2_0,
MC_LATENCY_ALLOWANCE_ISP2_1, MC_LATENCY_ALLOWANCE_ISP2B_0,
MC_LATENCY_ALLOWANCE_ISP2B_1, MC_LATENCY_ALLOWANCE_VDE_0,
MC_LATENCY_ALLOWANCE_VDE_1, MC_LATENCY_ALLOWANCE_VDE_2,
MC_LATENCY_ALLOWANCE_VDE_3, MC_LATENCY_ALLOWANCE_SATA_0,
MC_LATENCY_ALLOWANCE_AFI_0
Example:
emc-table@12750 {
compatible = "nvidia,tegra12-emc-table";
reg = <0>;
clock-frequency = <0>;
nvidia,revision = <0>;
nvidia,emc-min-mv = <0>;
nvidia,gk20a-min-mv = <0>;
nvidia,source = "pllp_out0";
nvidia,src-sel-reg = <0>;
nvidia,burst-regs-num = <0>;
nvidia,burst-up-down-regs-num = <0>;
nvidia,emc-registers = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0>;
nvidia,emc-burst-up-down-regs = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
>;
nvidia,emc-zcal-cnt-long = <0>;
nvidia,emc-acal-interval = <0>;
nvidia,emc-ctt-term-ctrl = <0>;
nvidia,emc-cfg = <0>;
nvidia,emc-cfg-2 = <0>;
nvidia,emc-sel-dpd-ctrl = <0>;
nvidia,emc-cfg-dig-dll = <0>;
nvidia,emc-bgbias-ctl0 = <0>;
nvidia,emc-auto-cal-config2 = <0>;
nvidia,emc-auto-cal-config3 = <0>;
nvidia,emc-auto-cal-config = <0>;
nvidia,emc-mode-reset = <0>;
nvidia,emc-mode-1 = <0>;
nvidia,emc-mode-2 = <0>;
nvidia,emc-mode-4 = <0>;
nvidia,emc-clock-latency-change = <0>;
};
emc-table@20400 {
compatible = "nvidia,tegra12-emc-table";
reg = <0>;
clock-frequency = <0>;
nvidia,revision = <0>;
nvidia,emc-min-mv = <0>;
nvidia,gk20a-min-mv = <0>;
nvidia,source = "pllp_out0";
nvidia,src-sel-reg = <0>;
nvidia,burst-regs-num = <0>;
nvidia,burst-up-down-regs-num = <0>;
nvidia,emc-registers = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0>;
nvidia,emc-burst-up-down-regs = <0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0>;
nvidia,emc-zcal-cnt-long = <0>;
nvidia,emc-acal-interval = <0>;
nvidia,emc-ctt-term-ctrl = <0>;
nvidia,emc-cfg = <0>;
nvidia,emc-cfg-2 = <0>;
nvidia,emc-sel-dpd-ctrl = <0>;
nvidia,emc-cfg-dig-dll = <0>;
nvidia,emc-bgbias-ctl0 = <0>;
nvidia,emc-auto-cal-config2 = <0>;
nvidia,emc-auto-cal-config3 = <0>;
nvidia,emc-auto-cal-config = <0>;
nvidia,emc-mode-reset = <0>;
nvidia,emc-mode-1 = <0>;
nvidia,emc-mode-2 = <0>;
nvidia,emc-mode-4 = <0>;
nvidia,emc-clock-latency-change = <0>;
};

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NVIDIA Tegra124 MC(Memory Controller)
Required properties:
- compatible : "nvidia,tegra124-mc"
- reg : Should contain the register range of the device.
- #address-cells : Should be 1
- #size-cells : Should be 0
Example:
memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x70019000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};

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NVIDIA Tegra AHB
Required properties:
- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
- reg : Should contain 1 register ranges(address and length)
Example:
ahb: ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
};

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Embedded Memory Controller
Properties:
- name : Should be emc
- #address-cells : Should be 1
- #size-cells : Should be 0
- compatible : Should contain "nvidia,tegra20-emc".
- reg : Offset and length of the register set for the device
- nvidia,use-ram-code : If present, the sub-nodes will be addressed
and chosen using the ramcode board selector. If omitted, only one
set of tables can be present and said tables will be used
irrespective of ram-code configuration.
Child device nodes describe the memory settings for different configurations and clock rates.
Example:
memory-controller@7000f400 {
#address-cells = < 1 >;
#size-cells = < 0 >;
compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>;
}
Embedded Memory Controller ram-code table
If the emc node has the nvidia,use-ram-code property present, then the
next level of nodes below the emc table are used to specify which settings
apply for which ram-code settings.
If the emc node lacks the nvidia,use-ram-code property, this level is omitted
and the tables are stored directly under the emc node (see below).
Properties:
- name : Should be emc-tables
- nvidia,ram-code : the binary representation of the ram-code board strappings
for which this node (and children) are valid.
Embedded Memory Controller configuration table
This is a table containing the EMC register settings for the various
operating speeds of the memory controller. They are always located as
subnodes of the emc controller node.
There are two ways of specifying which tables to use:
* The simplest is if there is just one set of tables in the device tree,
and they will always be used (based on which frequency is used).
This is the preferred method, especially when firmware can fill in
this information based on the specific system information and just
pass it on to the kernel.
* The slightly more complex one is when more than one memory configuration
might exist on the system. The Tegra20 platform handles this during
early boot by selecting one out of possible 4 memory settings based
on a 2-pin "ram code" bootstrap setting on the board. The values of
these strappings can be read through a register in the SoC, and thus
used to select which tables to use.
Properties:
- name : Should be emc-table
- compatible : Should contain "nvidia,tegra20-emc-table".
- reg : either an opaque enumerator to tell different tables apart, or
the valid frequency for which the table should be used (in kHz).
- clock-frequency : the clock frequency for the EMC at which this
table should be used (in kHz).
- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
for operation at the 'clock-frequency' setting.
The order and contents of the registers are:
RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
CFG_CLKTRIM_1, CFG_CLKTRIM_2
emc-table@166000 {
reg = <166000>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = < 166000 >;
nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 >;
};
emc-table@333000 {
reg = <333000>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = < 333000 >;
nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 >;
};

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NVIDIA Tegra20 MC(Memory Controller)
Required properties:
- compatible : "nvidia,tegra20-mc"
- reg : Should contain 2 register ranges(address and length); see the
example below. Note that the MC registers are interleaved with the
GART registers, and hence must be represented as multiple ranges.
- interrupts : Should contain MC General interrupt.
Example:
memory-controller@0x7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <0 77 0x04>;
};

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NVIDIA Tegra Power Management Controller (PMC)
The PMC block interacts with an external Power Management Unit. The PMC
mostly controls the entry and exit of the system from different sleep
modes. It provides power-gating controllers for SoC and CPU power-islands.
Required properties:
- name : Should be pmc
- compatible : Should contain "nvidia,tegra<chip>-pmc".
- reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pclk" (The Tegra clock of that name),
"clk32k_in" (The 32KHz clock input to Tegra).
Optional properties:
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
The PMU is an external Power Management Unit, whose interrupt output
signal is fed into the PMC. This signal is optionally inverted, and then
fed into the ARM GIC. The PMC is not involved in the detection or
handling of this interrupt signal, merely its inversion.
- nvidia,suspend-mode : The suspend mode that the platform should use.
Valid values are 0, 1 and 2:
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
1 (LP1): CPU voltage off and DRAM in self-refresh
2 (LP2): CPU voltage off
- nvidia,core-power-req-active-high : Boolean, core power request active-high
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
is enabled.
- nvidia,reset-gpio : GPIO that can be used to warm reset the system.
Required properties when nvidia,suspend-mode is specified:
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
Core power good time in uS.
- nvidia,core-pwr-off-time : Core power off time in uS.
Required properties when nvidia,suspend-mode=<0>:
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
The LP0 vector contains the warm boot code that is executed by AVP when
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
processor and always being the first boot processor when chip is power on
or resume from deep sleep mode. When the system is resumed from the deep
sleep mode, the warm boot code will restore some PLLs, clocks and then
bring up CPU0 for resuming the system.
Example:
/ SoC dts including file
pmc@7000f400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 110>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <100>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
nvidia,lp0-vec = <0xbdffd000 0x2000>;
};
/ Tegra board dts file
{
...
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
...
};
Wake up events
The PMC is the only device that can wake up the system from deep sleep
mode (i.e. LP0). There are some wake up events that in the PMC wake mask
register can be used to trigger PMC to wake up the system. The PMC wake
mask register defines which devices or siganls can be the source to
trigger PMC waking up. If the devices support waking up system from deep
sleep mode, then it needs to describe a property for PMC wake up events.
Here is the property defines the usage.
Required properties when nvidia,suspend-mode=<0>:
- nvidia,pmc-wakeup : <pmc_phandle event_type event_offset trigger_type>
pmc_phandle: the phandle of PMC device tree node
event_type: 0 = PMC_WAKE_TYPE_GPIO
1 = PMC_WAKE_TYPE_EVENT
event_offset: the offset of PMC wake mask register
trigger_type: set 0 when event_type is PMC_WAKE_TYPE_GPIO
if event_type is PMC_WAKE_TYPE_EVENT
0 = PMC_TRIGGER_TYPE_NONE
1 = PMC_TRIGGER_TYPE_RISING
2 = PMC_TRIGGER_TYPE_FALLING
4 = PMC_TRIGGER_TYPE_HIGH
8 = PMC_TRIGGER_TYPE_LOW
- #wake-cells : should be 3
Example:
/ SoC dts including file
pmc: pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 261>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
/ Tegra board dts file
{
...
pmc {
...
nvidia,suspend-mode = <0>;
#wake-cells = <3>;
...
};
...
pmic {
...
nvidia,pmc-wakeup = <&pmc 1 18 8>;
...
};
...
rtc {
...
nvidia,pmc-wakeup = <&pmc 0 16 0>;
...
};
};

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Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt Normal file
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@@ -0,0 +1,18 @@
NVIDIA Tegra30 MC(Memory Controller)
Required properties:
- compatible : "nvidia,tegra30-mc"
- reg : Should contain 4 register ranges(address and length); see the
example below. Note that the MC registers are interleaved with the
SMMU registers, and hence must be represented as multiple ranges.
- interrupts : Should contain MC General interrupt.
Example:
memory-controller {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x010
0x7000f03c 0x1b4
0x7000f200 0x028
0x7000f284 0x17c>;
interrupts = <0 77 0x04>;
};